[llvm-branch-commits] [llvm-branch] r84581 - in /llvm/branches/Apple/Leela: include/llvm/CodeGen/ include/llvm/Target/ lib/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/ARM/ lib/Target/X86/ test/CodeGen/X86/ tools/llc/ tools/lli/
Bill Wendling
isanbard at gmail.com
Mon Oct 19 17:54:26 PDT 2009
Author: void
Date: Mon Oct 19 19:54:25 2009
New Revision: 84581
URL: http://llvm.org/viewvc/llvm-project?rev=84581&view=rev
Log:
$ svn merge -c 84272 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r84272 into '.':
$ svn merge -c 84273 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r84273 into '.':
$ svn merge -c 84311 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r84311 into '.':
$ svn merge -c 84315 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r84315 into '.':
$ svn merge -c 84321 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r84321 into '.':
$ svn merge -c 84324 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r84324 into '.':
$ svn merge -c 84326 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r84326 into '.':
$ svn merge -c 84411 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r84411 into '.':
$ svn merge -c 84424 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r84424 into '.':
$ svn merge -c 84425 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r84425 into '.':
$ svn merge -c 84431 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r84431 into '.':
$ svn merge -c 84432 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r84432 into '.':
Modified:
llvm/branches/Apple/Leela/include/llvm/CodeGen/MachineFrameInfo.h
llvm/branches/Apple/Leela/include/llvm/CodeGen/Passes.h
llvm/branches/Apple/Leela/include/llvm/CodeGen/PseudoSourceValue.h
llvm/branches/Apple/Leela/include/llvm/Target/TargetMachine.h
llvm/branches/Apple/Leela/include/llvm/Target/TargetSubtarget.h
llvm/branches/Apple/Leela/lib/CodeGen/LLVMTargetMachine.cpp
llvm/branches/Apple/Leela/lib/CodeGen/PostRASchedulerList.cpp
llvm/branches/Apple/Leela/lib/CodeGen/PreAllocSplitting.cpp
llvm/branches/Apple/Leela/lib/CodeGen/PrologEpilogInserter.cpp
llvm/branches/Apple/Leela/lib/CodeGen/PseudoSourceValue.cpp
llvm/branches/Apple/Leela/lib/CodeGen/RegAllocLocal.cpp
llvm/branches/Apple/Leela/lib/CodeGen/ScheduleDAGInstrs.cpp
llvm/branches/Apple/Leela/lib/CodeGen/ScheduleDAGInstrs.h
llvm/branches/Apple/Leela/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
llvm/branches/Apple/Leela/lib/CodeGen/VirtRegMap.cpp
llvm/branches/Apple/Leela/lib/Target/ARM/ARMSubtarget.h
llvm/branches/Apple/Leela/lib/Target/X86/X86Subtarget.h
llvm/branches/Apple/Leela/test/CodeGen/X86/2007-01-08-InstrSched.ll
llvm/branches/Apple/Leela/test/CodeGen/X86/2008-07-11-SpillerBug.ll
llvm/branches/Apple/Leela/test/CodeGen/X86/2009-04-21-NoReloadImpDef.ll
llvm/branches/Apple/Leela/test/CodeGen/X86/2009-09-19-SchedCustomLoweringBug.ll
llvm/branches/Apple/Leela/test/CodeGen/X86/abi-isel.ll
llvm/branches/Apple/Leela/test/CodeGen/X86/fastcc.ll
llvm/branches/Apple/Leela/test/CodeGen/X86/peep-test-3.ll
llvm/branches/Apple/Leela/test/CodeGen/X86/pic.ll
llvm/branches/Apple/Leela/test/CodeGen/X86/sink-hoist.ll
llvm/branches/Apple/Leela/test/CodeGen/X86/sse2.ll
llvm/branches/Apple/Leela/test/CodeGen/X86/sse3.ll
llvm/branches/Apple/Leela/test/CodeGen/X86/tailcallstack64.ll
llvm/branches/Apple/Leela/test/CodeGen/X86/widen_arith-3.ll
llvm/branches/Apple/Leela/tools/llc/llc.cpp
llvm/branches/Apple/Leela/tools/lli/lli.cpp
Modified: llvm/branches/Apple/Leela/include/llvm/CodeGen/MachineFrameInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/include/llvm/CodeGen/MachineFrameInfo.h?rev=84581&r1=84580&r2=84581&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/include/llvm/CodeGen/MachineFrameInfo.h (original)
+++ llvm/branches/Apple/Leela/include/llvm/CodeGen/MachineFrameInfo.h Mon Oct 19 19:54:25 2009
@@ -86,6 +86,10 @@
// StackObject - Represent a single object allocated on the stack.
struct StackObject {
+ // SPOffset - The offset of this object from the stack pointer on entry to
+ // the function. This field has no meaning for a variable sized element.
+ int64_t SPOffset;
+
// The size of this object on the stack. 0 means a variable sized object,
// ~0ULL means a dead object.
uint64_t Size;
@@ -98,12 +102,14 @@
// default, fixed objects are immutable unless marked otherwise.
bool isImmutable;
- // SPOffset - The offset of this object from the stack pointer on entry to
- // the function. This field has no meaning for a variable sized element.
- int64_t SPOffset;
-
- StackObject(uint64_t Sz, unsigned Al, int64_t SP = 0, bool IM = false)
- : Size(Sz), Alignment(Al), isImmutable(IM), SPOffset(SP) {}
+ // isSpillSlot - If true, the stack object is used as spill slot. It
+ // cannot alias any other memory objects.
+ bool isSpillSlot;
+
+ StackObject(uint64_t Sz, unsigned Al, int64_t SP = 0, bool IM = false,
+ bool isSS = false)
+ : SPOffset(SP), Size(Sz), Alignment(Al), isImmutable(IM),
+ isSpillSlot(isSS) {}
};
/// Objects - The list of stack objects allocated...
@@ -352,6 +358,14 @@
return Objects[ObjectIdx+NumFixedObjects].isImmutable;
}
+ /// isSpillSlotObjectIndex - Returns true if the specified index corresponds
+ /// to a spill slot..
+ bool isSpillSlotObjectIndex(int ObjectIdx) const {
+ assert(unsigned(ObjectIdx+NumFixedObjects) < Objects.size() &&
+ "Invalid Object Idx!");
+ return Objects[ObjectIdx+NumFixedObjects].isSpillSlot;;
+ }
+
/// isDeadObjectIndex - Returns true if the specified index corresponds to
/// a dead object.
bool isDeadObjectIndex(int ObjectIdx) const {
@@ -363,9 +377,9 @@
/// CreateStackObject - Create a new statically sized stack object, returning
/// a nonnegative identifier to represent it.
///
- int CreateStackObject(uint64_t Size, unsigned Alignment) {
+ int CreateStackObject(uint64_t Size, unsigned Alignment, bool isSS = false) {
assert(Size != 0 && "Cannot allocate zero size stack objects!");
- Objects.push_back(StackObject(Size, Alignment));
+ Objects.push_back(StackObject(Size, Alignment, 0, false, isSS));
return (int)Objects.size()-NumFixedObjects-1;
}
Modified: llvm/branches/Apple/Leela/include/llvm/CodeGen/Passes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/include/llvm/CodeGen/Passes.h?rev=84581&r1=84580&r2=84581&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/include/llvm/CodeGen/Passes.h (original)
+++ llvm/branches/Apple/Leela/include/llvm/CodeGen/Passes.h Mon Oct 19 19:54:25 2009
@@ -15,13 +15,13 @@
#ifndef LLVM_CODEGEN_PASSES_H
#define LLVM_CODEGEN_PASSES_H
+#include "llvm/Target/TargetMachine.h"
#include <string>
namespace llvm {
class FunctionPass;
class PassInfo;
- class TargetMachine;
class TargetLowering;
class RegisterCoalescer;
class raw_ostream;
@@ -119,8 +119,9 @@
///
FunctionPass *createLowerSubregsPass();
- /// createPostRAScheduler - under development.
- FunctionPass *createPostRAScheduler();
+ /// createPostRAScheduler - This pass performs post register allocation
+ /// scheduling.
+ FunctionPass *createPostRAScheduler(CodeGenOpt::Level OptLevel);
/// BranchFolding Pass - This pass performs machine code CFG based
/// optimizations to delete branches to branches, eliminate branches to
Modified: llvm/branches/Apple/Leela/include/llvm/CodeGen/PseudoSourceValue.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/include/llvm/CodeGen/PseudoSourceValue.h?rev=84581&r1=84580&r2=84581&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/include/llvm/CodeGen/PseudoSourceValue.h (original)
+++ llvm/branches/Apple/Leela/include/llvm/CodeGen/PseudoSourceValue.h Mon Oct 19 19:54:25 2009
@@ -39,6 +39,10 @@
///
virtual bool isConstant(const MachineFrameInfo *) const;
+ /// isAliased - Test whether the memory pointed to by this
+ /// PseudoSourceValue may also be pointed to by an LLVM IR Value.
+ virtual bool isAliased(const MachineFrameInfo *) const;
+
/// classof - Methods for support type inquiry through isa, cast, and
/// dyn_cast:
///
Modified: llvm/branches/Apple/Leela/include/llvm/Target/TargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/include/llvm/Target/TargetMachine.h?rev=84581&r1=84580&r2=84581&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/include/llvm/Target/TargetMachine.h (original)
+++ llvm/branches/Apple/Leela/include/llvm/Target/TargetMachine.h Mon Oct 19 19:54:25 2009
@@ -74,9 +74,10 @@
// Code generation optimization level.
namespace CodeGenOpt {
enum Level {
- Default,
- None,
- Aggressive
+ None, // -O0
+ Less, // -O1
+ Default, // -O2, -Os
+ Aggressive // -O3
};
}
Modified: llvm/branches/Apple/Leela/include/llvm/Target/TargetSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/include/llvm/Target/TargetSubtarget.h?rev=84581&r1=84580&r2=84581&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/include/llvm/Target/TargetSubtarget.h (original)
+++ llvm/branches/Apple/Leela/include/llvm/Target/TargetSubtarget.h Mon Oct 19 19:54:25 2009
@@ -14,6 +14,8 @@
#ifndef LLVM_TARGET_TARGETSUBTARGET_H
#define LLVM_TARGET_TARGETSUBTARGET_H
+#include "llvm/Target/TargetMachine.h"
+
namespace llvm {
class SDep;
@@ -39,9 +41,12 @@
/// should be attempted.
virtual unsigned getSpecialAddressLatency() const { return 0; }
- // enablePostRAScheduler - Return true to enable
- // post-register-allocation scheduling.
- virtual bool enablePostRAScheduler() const { return false; }
+ // enablePostRAScheduler - If the target can benefit from post-regalloc
+ // scheduling and the specified optimization level meets the requirement
+ // return true to enable post-register-allocation scheduling.
+ virtual bool enablePostRAScheduler(CodeGenOpt::Level OptLevel) const {
+ return false;
+ }
// adjustSchedDependency - Perform target specific adjustments to
// the latency of a schedule dependency.
Modified: llvm/branches/Apple/Leela/lib/CodeGen/LLVMTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/CodeGen/LLVMTargetMachine.cpp?rev=84581&r1=84580&r2=84581&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/CodeGen/LLVMTargetMachine.cpp (original)
+++ llvm/branches/Apple/Leela/lib/CodeGen/LLVMTargetMachine.cpp Mon Oct 19 19:54:25 2009
@@ -323,7 +323,7 @@
// Second pass scheduler.
if (OptLevel != CodeGenOpt::None) {
- PM.add(createPostRAScheduler());
+ PM.add(createPostRAScheduler(OptLevel));
printAndVerify(PM);
}
Modified: llvm/branches/Apple/Leela/lib/CodeGen/PostRASchedulerList.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/CodeGen/PostRASchedulerList.cpp?rev=84581&r1=84580&r2=84581&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/CodeGen/PostRASchedulerList.cpp (original)
+++ llvm/branches/Apple/Leela/lib/CodeGen/PostRASchedulerList.cpp Mon Oct 19 19:54:25 2009
@@ -78,10 +78,12 @@
namespace {
class VISIBILITY_HIDDEN PostRAScheduler : public MachineFunctionPass {
AliasAnalysis *AA;
+ CodeGenOpt::Level OptLevel;
public:
static char ID;
- PostRAScheduler() : MachineFunctionPass(&ID) {}
+ PostRAScheduler(CodeGenOpt::Level ol) :
+ MachineFunctionPass(&ID), OptLevel(ol) {}
void getAnalysisUsage(AnalysisUsage &AU) const {
AU.setPreservesCFG();
@@ -238,7 +240,7 @@
} else {
// Check that post-RA scheduling is enabled for this function
const TargetSubtarget &ST = Fn.getTarget().getSubtarget<TargetSubtarget>();
- if (!ST.enablePostRAScheduler())
+ if (!ST.enablePostRAScheduler(OptLevel))
return true;
}
@@ -1195,6 +1197,6 @@
// Public Constructor Functions
//===----------------------------------------------------------------------===//
-FunctionPass *llvm::createPostRAScheduler() {
- return new PostRAScheduler();
+FunctionPass *llvm::createPostRAScheduler(CodeGenOpt::Level OptLevel) {
+ return new PostRAScheduler(OptLevel);
}
Modified: llvm/branches/Apple/Leela/lib/CodeGen/PreAllocSplitting.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/CodeGen/PreAllocSplitting.cpp?rev=84581&r1=84580&r2=84581&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/CodeGen/PreAllocSplitting.cpp (original)
+++ llvm/branches/Apple/Leela/lib/CodeGen/PreAllocSplitting.cpp Mon Oct 19 19:54:25 2009
@@ -952,7 +952,7 @@
if (I != IntervalSSMap.end()) {
SS = I->second;
} else {
- SS = MFI->CreateStackObject(RC->getSize(), RC->getAlignment());
+ SS = MFI->CreateStackObject(RC->getSize(), RC->getAlignment());
}
MachineInstr* FMI = TII->foldMemoryOperand(*MBB->getParent(),
Modified: llvm/branches/Apple/Leela/lib/CodeGen/PrologEpilogInserter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/CodeGen/PrologEpilogInserter.cpp?rev=84581&r1=84580&r2=84581&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/CodeGen/PrologEpilogInserter.cpp (original)
+++ llvm/branches/Apple/Leela/lib/CodeGen/PrologEpilogInserter.cpp Mon Oct 19 19:54:25 2009
@@ -259,7 +259,7 @@
// the TargetRegisterClass if the stack alignment is smaller. Use the
// min.
Align = std::min(Align, StackAlign);
- FrameIdx = FFI->CreateStackObject(RC->getSize(), Align);
+ FrameIdx = FFI->CreateStackObject(RC->getSize(), Align, true);
if ((unsigned)FrameIdx < MinCSFrameIndex) MinCSFrameIndex = FrameIdx;
if ((unsigned)FrameIdx > MaxCSFrameIndex) MaxCSFrameIndex = FrameIdx;
} else {
Modified: llvm/branches/Apple/Leela/lib/CodeGen/PseudoSourceValue.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/CodeGen/PseudoSourceValue.cpp?rev=84581&r1=84580&r2=84581&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/CodeGen/PseudoSourceValue.cpp (original)
+++ llvm/branches/Apple/Leela/lib/CodeGen/PseudoSourceValue.cpp Mon Oct 19 19:54:25 2009
@@ -63,6 +63,8 @@
virtual bool isConstant(const MachineFrameInfo *MFI) const;
+ virtual bool isAliased(const MachineFrameInfo *MFI) const;
+
virtual void printCustom(raw_ostream &OS) const {
OS << "FixedStack" << FI;
}
@@ -89,6 +91,26 @@
return false;
}
+bool PseudoSourceValue::isAliased(const MachineFrameInfo *MFI) const {
+ if (this == getStack() ||
+ this == getGOT() ||
+ this == getConstantPool() ||
+ this == getJumpTable())
+ return false;
+ llvm_unreachable("Unknown PseudoSourceValue!");
+ return true;
+}
+
bool FixedStackPseudoSourceValue::isConstant(const MachineFrameInfo *MFI) const{
return MFI && MFI->isImmutableObjectIndex(FI);
}
+
+bool FixedStackPseudoSourceValue::isAliased(const MachineFrameInfo *MFI) const {
+ // Negative frame indices are used for special things that don't
+ // appear in LLVM IR. Non-negative indices may be used for things
+ // like static allocas.
+ if (!MFI)
+ return FI >= 0;
+ // Spill slots should not alias others.
+ return !MFI->isFixedObjectIndex(FI) && !MFI->isSpillSlotObjectIndex(FI);
+}
Modified: llvm/branches/Apple/Leela/lib/CodeGen/RegAllocLocal.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/CodeGen/RegAllocLocal.cpp?rev=84581&r1=84580&r2=84581&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/CodeGen/RegAllocLocal.cpp (original)
+++ llvm/branches/Apple/Leela/lib/CodeGen/RegAllocLocal.cpp Mon Oct 19 19:54:25 2009
@@ -263,7 +263,7 @@
// Allocate a new stack object for this spill location...
int FrameIdx = MF->getFrameInfo()->CreateStackObject(RC->getSize(),
- RC->getAlignment());
+ RC->getAlignment(),true);
// Assign the slot...
StackSlotForVirtReg[VirtReg] = FrameIdx;
Modified: llvm/branches/Apple/Leela/lib/CodeGen/ScheduleDAGInstrs.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/CodeGen/ScheduleDAGInstrs.cpp?rev=84581&r1=84580&r2=84581&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/CodeGen/ScheduleDAGInstrs.cpp (original)
+++ llvm/branches/Apple/Leela/lib/CodeGen/ScheduleDAGInstrs.cpp Mon Oct 19 19:54:25 2009
@@ -32,7 +32,9 @@
ScheduleDAGInstrs::ScheduleDAGInstrs(MachineFunction &mf,
const MachineLoopInfo &mli,
const MachineDominatorTree &mdt)
- : ScheduleDAG(mf), MLI(mli), MDT(mdt), LoopRegs(MLI, MDT) {}
+ : ScheduleDAG(mf), MLI(mli), MDT(mdt), LoopRegs(MLI, MDT) {
+ MFI = mf.getFrameInfo();
+}
/// Run - perform scheduling.
///
@@ -95,7 +97,8 @@
/// getUnderlyingObjectForInstr - If this machine instr has memory reference
/// information and it can be tracked to a normal reference to a known
/// object, return the Value for that object. Otherwise return null.
-static const Value *getUnderlyingObjectForInstr(const MachineInstr *MI) {
+static const Value *getUnderlyingObjectForInstr(const MachineInstr *MI,
+ const MachineFrameInfo *MFI) {
if (!MI->hasOneMemOperand() ||
!(*MI->memoperands_begin())->getValue() ||
(*MI->memoperands_begin())->isVolatile())
@@ -106,10 +109,19 @@
return 0;
V = getUnderlyingObject(V);
- if (!isa<PseudoSourceValue>(V) && !isIdentifiedObject(V))
- return 0;
+ if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V)) {
+ // For now, ignore PseudoSourceValues which may alias LLVM IR values
+ // because the code that uses this function has no way to cope with
+ // such aliases.
+ if (PSV->isAliased(MFI))
+ return 0;
+ return V;
+ }
- return V;
+ if (isIdentifiedObject(V))
+ return V;
+
+ return 0;
}
void ScheduleDAGInstrs::StartBlock(MachineBasicBlock *BB) {
@@ -344,7 +356,7 @@
// Unknown memory accesses. Assume the worst.
ChainMMO = 0;
} else if (TID.mayStore()) {
- if (const Value *V = getUnderlyingObjectForInstr(MI)) {
+ if (const Value *V = getUnderlyingObjectForInstr(MI, MFI)) {
// A store to a specific PseudoSourceValue. Add precise dependencies.
// Handle the def in MemDefs, if there is one.
std::map<const Value *, SUnit *>::iterator I = MemDefs.find(V);
@@ -377,7 +389,7 @@
} else if (TID.mayLoad()) {
if (MI->isInvariantLoad(AA)) {
// Invariant load, no chain dependencies needed!
- } else if (const Value *V = getUnderlyingObjectForInstr(MI)) {
+ } else if (const Value *V = getUnderlyingObjectForInstr(MI, MFI)) {
// A load from a specific PseudoSourceValue. Add precise dependencies.
std::map<const Value *, SUnit *>::iterator I = MemDefs.find(V);
if (I != MemDefs.end())
Modified: llvm/branches/Apple/Leela/lib/CodeGen/ScheduleDAGInstrs.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/CodeGen/ScheduleDAGInstrs.h?rev=84581&r1=84580&r2=84581&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/CodeGen/ScheduleDAGInstrs.h (original)
+++ llvm/branches/Apple/Leela/lib/CodeGen/ScheduleDAGInstrs.h Mon Oct 19 19:54:25 2009
@@ -98,6 +98,7 @@
class VISIBILITY_HIDDEN ScheduleDAGInstrs : public ScheduleDAG {
const MachineLoopInfo &MLI;
const MachineDominatorTree &MDT;
+ const MachineFrameInfo *MFI;
/// Defs, Uses - Remember where defs and uses of each physical register
/// are as we iterate upward through the instructions. This is allocated
Modified: llvm/branches/Apple/Leela/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp?rev=84581&r1=84580&r2=84581&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp (original)
+++ llvm/branches/Apple/Leela/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp Mon Oct 19 19:54:25 2009
@@ -115,7 +115,8 @@
// Create the stack frame object. Make sure it is aligned for both
// the source and expanded destination types.
unsigned Alignment =
- TLI.getTargetData()->getPrefTypeAlignment(NOutVT.getTypeForEVT(*DAG.getContext()));
+ TLI.getTargetData()->getPrefTypeAlignment(NOutVT.
+ getTypeForEVT(*DAG.getContext()));
SDValue StackPtr = DAG.CreateStackTemporary(InVT, Alignment);
int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
const Value *SV = PseudoSourceValue::getFixedStack(SPFI);
Modified: llvm/branches/Apple/Leela/lib/CodeGen/VirtRegMap.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/CodeGen/VirtRegMap.cpp?rev=84581&r1=84580&r2=84581&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/CodeGen/VirtRegMap.cpp (original)
+++ llvm/branches/Apple/Leela/lib/CodeGen/VirtRegMap.cpp Mon Oct 19 19:54:25 2009
@@ -118,7 +118,7 @@
"attempt to assign stack slot to already spilled register");
const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtReg);
int SS = MF->getFrameInfo()->CreateStackObject(RC->getSize(),
- RC->getAlignment());
+ RC->getAlignment(), /*isSS*/true);
if (LowSpillSlot == NO_STACK_SLOT)
LowSpillSlot = SS;
if (HighSpillSlot == NO_STACK_SLOT || SS > HighSpillSlot)
@@ -162,7 +162,7 @@
if (I != EmergencySpillSlots.end())
return I->second;
int SS = MF->getFrameInfo()->CreateStackObject(RC->getSize(),
- RC->getAlignment());
+ RC->getAlignment(), /*isSS*/true);
if (LowSpillSlot == NO_STACK_SLOT)
LowSpillSlot = SS;
if (HighSpillSlot == NO_STACK_SLOT || SS > HighSpillSlot)
Modified: llvm/branches/Apple/Leela/lib/Target/ARM/ARMSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/ARM/ARMSubtarget.h?rev=84581&r1=84580&r2=84581&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/ARM/ARMSubtarget.h (original)
+++ llvm/branches/Apple/Leela/lib/Target/ARM/ARMSubtarget.h Mon Oct 19 19:54:25 2009
@@ -126,9 +126,11 @@
const std::string & getCPUString() const { return CPUString; }
- /// enablePostRAScheduler - From TargetSubtarget, return true to
- /// enable post-RA scheduler.
- bool enablePostRAScheduler() const { return PostRAScheduler; }
+ /// enablePostRAScheduler - True at 'More' optimization except
+ /// for Thumb1.
+ bool enablePostRAScheduler(CodeGenOpt::Level OptLevel) const {
+ return PostRAScheduler && OptLevel >= CodeGenOpt::Default;
+ }
/// getInstrItins - Return the instruction itineraies based on subtarget
/// selection.
Modified: llvm/branches/Apple/Leela/lib/Target/X86/X86Subtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/X86/X86Subtarget.h?rev=84581&r1=84580&r2=84581&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/X86/X86Subtarget.h (original)
+++ llvm/branches/Apple/Leela/lib/Target/X86/X86Subtarget.h Mon Oct 19 19:54:25 2009
@@ -222,6 +222,12 @@
/// indicating the number of scheduling cycles of backscheduling that
/// should be attempted.
unsigned getSpecialAddressLatency() const;
+
+ /// enablePostRAScheduler - X86 target is enabling post-alloc scheduling
+ /// at 'More' optimization level.
+ bool enablePostRAScheduler(CodeGenOpt::Level OptLevel) const {
+ return OptLevel >= CodeGenOpt::Default;
+ }
};
} // End llvm namespace
Modified: llvm/branches/Apple/Leela/test/CodeGen/X86/2007-01-08-InstrSched.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/test/CodeGen/X86/2007-01-08-InstrSched.ll?rev=84581&r1=84580&r2=84581&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/test/CodeGen/X86/2007-01-08-InstrSched.ll (original)
+++ llvm/branches/Apple/Leela/test/CodeGen/X86/2007-01-08-InstrSched.ll Mon Oct 19 19:54:25 2009
@@ -11,9 +11,12 @@
%tmp14 = fadd float %tmp12, %tmp7
ret float %tmp14
-; CHECK: mulss LCPI1_2(%rip)
+; CHECK: mulss LCPI1_3(%rip)
+; CHECK-NEXT: mulss LCPI1_0(%rip)
+; CHECK-NEXT: mulss LCPI1_1(%rip)
+; CHECK-NEXT: mulss LCPI1_2(%rip)
+; CHECK-NEXT: addss
; CHECK-NEXT: addss
-; CHECK-NEXT: mulss LCPI1_3(%rip)
; CHECK-NEXT: addss
; CHECK-NEXT: ret
}
Modified: llvm/branches/Apple/Leela/test/CodeGen/X86/2008-07-11-SpillerBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/test/CodeGen/X86/2008-07-11-SpillerBug.ll?rev=84581&r1=84580&r2=84581&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/test/CodeGen/X86/2008-07-11-SpillerBug.ll (original)
+++ llvm/branches/Apple/Leela/test/CodeGen/X86/2008-07-11-SpillerBug.ll Mon Oct 19 19:54:25 2009
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86 -relocation-model=static -disable-fp-elim | FileCheck %s
+; RUN: llc < %s -march=x86 -relocation-model=static -disable-fp-elim -post-RA-scheduler=false | FileCheck %s
; PR2536
Modified: llvm/branches/Apple/Leela/test/CodeGen/X86/2009-04-21-NoReloadImpDef.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/test/CodeGen/X86/2009-04-21-NoReloadImpDef.ll?rev=84581&r1=84580&r2=84581&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/test/CodeGen/X86/2009-04-21-NoReloadImpDef.ll (original)
+++ llvm/branches/Apple/Leela/test/CodeGen/X86/2009-04-21-NoReloadImpDef.ll Mon Oct 19 19:54:25 2009
@@ -1,5 +1,5 @@
; RUN: llc -mtriple=i386-apple-darwin10.0 -relocation-model=pic \
-; RUN: -disable-fp-elim -mattr=-sse41,-sse3,+sse2 < %s | \
+; RUN: -disable-fp-elim -mattr=-sse41,-sse3,+sse2 -post-RA-scheduler=false < %s | \
; RUN: FileCheck %s
; rdar://6808032
Modified: llvm/branches/Apple/Leela/test/CodeGen/X86/2009-09-19-SchedCustomLoweringBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/test/CodeGen/X86/2009-09-19-SchedCustomLoweringBug.ll?rev=84581&r1=84580&r2=84581&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/test/CodeGen/X86/2009-09-19-SchedCustomLoweringBug.ll (original)
+++ llvm/branches/Apple/Leela/test/CodeGen/X86/2009-09-19-SchedCustomLoweringBug.ll Mon Oct 19 19:54:25 2009
@@ -9,9 +9,7 @@
br label %bb
bb: ; preds = %bb1, %entry
-; CHECK: movl %e
-; CHECK-NEXT: addl $1
-; CHECK-NEXT: movl %e
+; CHECK: addl $1
; CHECK-NEXT: adcl $0
%i.0 = phi i64 [ 0, %entry ], [ %0, %bb1 ] ; <i64> [#uses=1]
%0 = add nsw i64 %i.0, 1 ; <i64> [#uses=2]
Modified: llvm/branches/Apple/Leela/test/CodeGen/X86/abi-isel.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/test/CodeGen/X86/abi-isel.ll?rev=84581&r1=84580&r2=84581&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/test/CodeGen/X86/abi-isel.ll (original)
+++ llvm/branches/Apple/Leela/test/CodeGen/X86/abi-isel.ll Mon Oct 19 19:54:25 2009
@@ -1,16 +1,16 @@
-; RUN: llc < %s -asm-verbose=0 -mtriple=i686-unknown-linux-gnu -march=x86 -relocation-model=static -code-model=small | FileCheck %s -check-prefix=LINUX-32-STATIC
-; RUN: llc < %s -asm-verbose=0 -mtriple=i686-unknown-linux-gnu -march=x86 -relocation-model=static -code-model=small | FileCheck %s -check-prefix=LINUX-32-PIC
+; RUN: llc < %s -asm-verbose=0 -mtriple=i686-unknown-linux-gnu -march=x86 -relocation-model=static -code-model=small -post-RA-scheduler=false | FileCheck %s -check-prefix=LINUX-32-STATIC
+; RUN: llc < %s -asm-verbose=0 -mtriple=i686-unknown-linux-gnu -march=x86 -relocation-model=static -code-model=small -post-RA-scheduler=false | FileCheck %s -check-prefix=LINUX-32-PIC
-; RUN: llc < %s -asm-verbose=0 -mtriple=x86_64-unknown-linux-gnu -march=x86-64 -relocation-model=static -code-model=small | FileCheck %s -check-prefix=LINUX-64-STATIC
-; RUN: llc < %s -asm-verbose=0 -mtriple=x86_64-unknown-linux-gnu -march=x86-64 -relocation-model=pic -code-model=small | FileCheck %s -check-prefix=LINUX-64-PIC
+; RUN: llc < %s -asm-verbose=0 -mtriple=x86_64-unknown-linux-gnu -march=x86-64 -relocation-model=static -code-model=small -post-RA-scheduler=false | FileCheck %s -check-prefix=LINUX-64-STATIC
+; RUN: llc < %s -asm-verbose=0 -mtriple=x86_64-unknown-linux-gnu -march=x86-64 -relocation-model=pic -code-model=small -post-RA-scheduler=false | FileCheck %s -check-prefix=LINUX-64-PIC
-; RUN: llc < %s -asm-verbose=0 -mtriple=i686-apple-darwin -march=x86 -relocation-model=static -code-model=small | FileCheck %s -check-prefix=DARWIN-32-STATIC
-; RUN: llc < %s -asm-verbose=0 -mtriple=i686-apple-darwin -march=x86 -relocation-model=dynamic-no-pic -code-model=small | FileCheck %s -check-prefix=DARWIN-32-DYNAMIC
-; RUN: llc < %s -asm-verbose=0 -mtriple=i686-apple-darwin -march=x86 -relocation-model=pic -code-model=small | FileCheck %s -check-prefix=DARWIN-32-PIC
-
-; RUN: llc < %s -asm-verbose=0 -mtriple=x86_64-apple-darwin -march=x86-64 -relocation-model=static -code-model=small | FileCheck %s -check-prefix=DARWIN-64-STATIC
-; RUN: llc < %s -asm-verbose=0 -mtriple=x86_64-apple-darwin -march=x86-64 -relocation-model=dynamic-no-pic -code-model=small | FileCheck %s -check-prefix=DARWIN-64-DYNAMIC
-; RUN: llc < %s -asm-verbose=0 -mtriple=x86_64-apple-darwin -march=x86-64 -relocation-model=pic -code-model=small | FileCheck %s -check-prefix=DARWIN-64-PIC
+; RUN: llc < %s -asm-verbose=0 -mtriple=i686-apple-darwin -march=x86 -relocation-model=static -code-model=small -post-RA-scheduler=false | FileCheck %s -check-prefix=DARWIN-32-STATIC
+; RUN: llc < %s -asm-verbose=0 -mtriple=i686-apple-darwin -march=x86 -relocation-model=dynamic-no-pic -code-model=small -post-RA-scheduler=false | FileCheck %s -check-prefix=DARWIN-32-DYNAMIC
+; RUN: llc < %s -asm-verbose=0 -mtriple=i686-apple-darwin -march=x86 -relocation-model=pic -code-model=small -post-RA-scheduler=false | FileCheck %s -check-prefix=DARWIN-32-PIC
+
+; RUN: llc < %s -asm-verbose=0 -mtriple=x86_64-apple-darwin -march=x86-64 -relocation-model=static -code-model=small -post-RA-scheduler=false | FileCheck %s -check-prefix=DARWIN-64-STATIC
+; RUN: llc < %s -asm-verbose=0 -mtriple=x86_64-apple-darwin -march=x86-64 -relocation-model=dynamic-no-pic -code-model=small -post-RA-scheduler=false | FileCheck %s -check-prefix=DARWIN-64-DYNAMIC
+; RUN: llc < %s -asm-verbose=0 -mtriple=x86_64-apple-darwin -march=x86-64 -relocation-model=pic -code-model=small -post-RA-scheduler=false | FileCheck %s -check-prefix=DARWIN-64-PIC
@src = external global [131072 x i32]
@dst = external global [131072 x i32]
Modified: llvm/branches/Apple/Leela/test/CodeGen/X86/fastcc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/test/CodeGen/X86/fastcc.ll?rev=84581&r1=84580&r2=84581&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/test/CodeGen/X86/fastcc.ll (original)
+++ llvm/branches/Apple/Leela/test/CodeGen/X86/fastcc.ll Mon Oct 19 19:54:25 2009
@@ -1,5 +1,6 @@
-; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+sse2 | grep mov | grep ecx | grep 0
-; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+sse2 | grep mov | grep xmm0 | grep 8
+; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+sse2 -post-RA-scheduler=false | FileCheck %s
+; CHECK: movsd %xmm0, 8(%esp)
+; CHECK: xorl %ecx, %ecx
@d = external global double ; <double*> [#uses=1]
@c = external global double ; <double*> [#uses=1]
Modified: llvm/branches/Apple/Leela/test/CodeGen/X86/peep-test-3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/test/CodeGen/X86/peep-test-3.ll?rev=84581&r1=84580&r2=84581&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/test/CodeGen/X86/peep-test-3.ll (original)
+++ llvm/branches/Apple/Leela/test/CodeGen/X86/peep-test-3.ll Mon Oct 19 19:54:25 2009
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86 | FileCheck %s
+; RUN: llc < %s -march=x86 -post-RA-scheduler=false | FileCheck %s
; rdar://7226797
; LLVM should omit the testl and use the flags result from the orl.
Modified: llvm/branches/Apple/Leela/test/CodeGen/X86/pic.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/test/CodeGen/X86/pic.ll?rev=84581&r1=84580&r2=84581&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/test/CodeGen/X86/pic.ll (original)
+++ llvm/branches/Apple/Leela/test/CodeGen/X86/pic.ll Mon Oct 19 19:54:25 2009
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=i686-pc-linux-gnu -relocation-model=pic -asm-verbose=false | FileCheck %s -check-prefix=LINUX
+; RUN: llc < %s -mtriple=i686-pc-linux-gnu -relocation-model=pic -asm-verbose=false -post-RA-scheduler=false | FileCheck %s -check-prefix=LINUX
@ptr = external global i32*
@dst = external global i32
Modified: llvm/branches/Apple/Leela/test/CodeGen/X86/sink-hoist.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/test/CodeGen/X86/sink-hoist.ll?rev=84581&r1=84580&r2=84581&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/test/CodeGen/X86/sink-hoist.ll (original)
+++ llvm/branches/Apple/Leela/test/CodeGen/X86/sink-hoist.ll Mon Oct 19 19:54:25 2009
@@ -6,10 +6,10 @@
; that it's conditionally evaluated.
; CHECK: foo:
-; CHECK-NEXT: divsd
-; CHECK: testb $1, %dil
-; CHECK-NEXT: jne
; CHECK: divsd
+; CHECK-NEXT: testb $1, %dil
+; CHECK-NEXT: jne
+; CHECK-NEXT: divsd
define double @foo(double %x, double %y, i1 %c) nounwind {
%a = fdiv double %x, 3.2
Modified: llvm/branches/Apple/Leela/test/CodeGen/X86/sse2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/test/CodeGen/X86/sse2.ll?rev=84581&r1=84580&r2=84581&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/test/CodeGen/X86/sse2.ll (original)
+++ llvm/branches/Apple/Leela/test/CodeGen/X86/sse2.ll Mon Oct 19 19:54:25 2009
@@ -10,10 +10,10 @@
; CHECK: t1:
; CHECK: movl 8(%esp), %eax
+; CHECK-NEXT: movl 4(%esp), %ecx
; CHECK-NEXT: movapd (%eax), %xmm0
; CHECK-NEXT: movlpd 12(%esp), %xmm0
-; CHECK-NEXT: movl 4(%esp), %eax
-; CHECK-NEXT: movapd %xmm0, (%eax)
+; CHECK-NEXT: movapd %xmm0, (%ecx)
; CHECK-NEXT: ret
}
@@ -26,9 +26,9 @@
; CHECK: t2:
; CHECK: movl 8(%esp), %eax
+; CHECK-NEXT: movl 4(%esp), %ecx
; CHECK-NEXT: movapd (%eax), %xmm0
; CHECK-NEXT: movhpd 12(%esp), %xmm0
-; CHECK-NEXT: movl 4(%esp), %eax
-; CHECK-NEXT: movapd %xmm0, (%eax)
+; CHECK-NEXT: movapd %xmm0, (%ecx)
; CHECK-NEXT: ret
}
Modified: llvm/branches/Apple/Leela/test/CodeGen/X86/sse3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/test/CodeGen/X86/sse3.ll?rev=84581&r1=84580&r2=84581&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/test/CodeGen/X86/sse3.ll (original)
+++ llvm/branches/Apple/Leela/test/CodeGen/X86/sse3.ll Mon Oct 19 19:54:25 2009
@@ -17,8 +17,8 @@
; X64: t0:
; X64: movddup (%rsi), %xmm0
-; X64: pshuflw $0, %xmm0, %xmm0
; X64: xorl %eax, %eax
+; X64: pshuflw $0, %xmm0, %xmm0
; X64: pinsrw $0, %eax, %xmm0
; X64: movaps %xmm0, (%rdi)
; X64: ret
@@ -167,18 +167,12 @@
store <4 x i16> %6, <4 x i16>* @g2, align 8
ret void
; X64: t10:
-; X64: movq _g1 at GOTPCREL(%rip), %rax
-; X64: movaps (%rax), %xmm0
; X64: pextrw $4, %xmm0, %eax
-; X64: movaps %xmm0, %xmm1
+; X64: pextrw $6, %xmm0, %edx
; X64: movlhps %xmm1, %xmm1
; X64: pshuflw $8, %xmm1, %xmm1
; X64: pinsrw $2, %eax, %xmm1
-; X64: pextrw $6, %xmm0, %eax
-; X64: pinsrw $3, %eax, %xmm1
-; X64: movq _g2 at GOTPCREL(%rip), %rax
-; X64: movq %xmm1, (%rax)
-; X64: ret
+; X64: pinsrw $3, %edx, %xmm1
}
@@ -189,8 +183,8 @@
ret <8 x i16> %tmp7
; X64: t11:
-; X64: movd %xmm1, %eax
; X64: movlhps %xmm0, %xmm0
+; X64: movd %xmm1, %eax
; X64: pshuflw $1, %xmm0, %xmm0
; X64: pinsrw $1, %eax, %xmm0
; X64: ret
@@ -203,8 +197,8 @@
ret <8 x i16> %tmp9
; X64: t12:
-; X64: pextrw $3, %xmm1, %eax
; X64: movlhps %xmm0, %xmm0
+; X64: pextrw $3, %xmm1, %eax
; X64: pshufhw $3, %xmm0, %xmm0
; X64: pinsrw $5, %eax, %xmm0
; X64: ret
@@ -256,18 +250,12 @@
%tmp9 = shufflevector <16 x i8> %tmp8, <16 x i8> %T0, <16 x i32> < i32 0, i32 1, i32 2, i32 17, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef , i32 undef >
ret <16 x i8> %tmp9
; X64: t16:
-; X64: movaps LCPI17_0(%rip), %xmm1
-; X64: movd %xmm1, %eax
; X64: pinsrw $0, %eax, %xmm1
; X64: pextrw $8, %xmm0, %eax
; X64: pinsrw $1, %eax, %xmm1
; X64: pextrw $1, %xmm1, %ecx
; X64: movd %xmm1, %edx
; X64: pinsrw $0, %edx, %xmm1
-; X64: movzbl %cl, %ecx
-; X64: andw $-256, %ax
-; X64: orw %cx, %ax
-; X64: movaps %xmm1, %xmm0
; X64: pinsrw $1, %eax, %xmm0
; X64: ret
}
Modified: llvm/branches/Apple/Leela/test/CodeGen/X86/tailcallstack64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/test/CodeGen/X86/tailcallstack64.ll?rev=84581&r1=84580&r2=84581&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/test/CodeGen/X86/tailcallstack64.ll (original)
+++ llvm/branches/Apple/Leela/test/CodeGen/X86/tailcallstack64.ll Mon Oct 19 19:54:25 2009
@@ -3,19 +3,18 @@
; Check that lowered arguments on the stack do not overwrite each other.
; Add %in1 %p1 to a different temporary register (%eax).
; CHECK: movl %edi, %eax
-; CHECK: addl 32(%rsp), %eax
; Move param %in1 to temp register (%r10d).
; CHECK: movl 40(%rsp), %r10d
-; Move result of addition to stack.
-; CHECK: movl %eax, 40(%rsp)
; Move param %in2 to stack.
; CHECK: movl %r10d, 32(%rsp)
+; Move result of addition to stack.
+; CHECK: movl %eax, 40(%rsp)
; Eventually, do a TAILCALL
; CHECK: TAILCALL
-declare fastcc i32 @tailcallee(i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5, i32 %p6, i32 %a, i32 %b)
+declare fastcc i32 @tailcallee(i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5, i32 %p6, i32 %a, i32 %b) nounwind
-define fastcc i32 @tailcaller(i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5, i32 %p6, i32 %in1, i32 %in2) {
+define fastcc i32 @tailcaller(i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5, i32 %p6, i32 %in1, i32 %in2) nounwind {
entry:
%tmp = add i32 %in1, %p1
%retval = tail call fastcc i32 @tailcallee(i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5, i32 %p6, i32 %in2,i32 %tmp)
Modified: llvm/branches/Apple/Leela/test/CodeGen/X86/widen_arith-3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/test/CodeGen/X86/widen_arith-3.ll?rev=84581&r1=84580&r2=84581&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/test/CodeGen/X86/widen_arith-3.ll (original)
+++ llvm/branches/Apple/Leela/test/CodeGen/X86/widen_arith-3.ll Mon Oct 19 19:54:25 2009
@@ -1,7 +1,7 @@
-; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx -o %t
-; RUN: grep paddw %t | count 1
-; RUN: grep movd %t | count 2
-; RUN: grep pextrw %t | count 1
+; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx | FileCheck %s
+; CHECK: paddw
+; CHECK: pextrw
+; CHECK: movd
; Widen a v3i16 to v8i16 to do a vector add
Modified: llvm/branches/Apple/Leela/tools/llc/llc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/tools/llc/llc.cpp?rev=84581&r1=84580&r2=84581&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/tools/llc/llc.cpp (original)
+++ llvm/branches/Apple/Leela/tools/llc/llc.cpp Mon Oct 19 19:54:25 2009
@@ -298,7 +298,7 @@
return 1;
case ' ': break;
case '0': OLvl = CodeGenOpt::None; break;
- case '1':
+ case '1': OLvl = CodeGenOpt::Less; break;
case '2': OLvl = CodeGenOpt::Default; break;
case '3': OLvl = CodeGenOpt::Aggressive; break;
}
Modified: llvm/branches/Apple/Leela/tools/lli/lli.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/tools/lli/lli.cpp?rev=84581&r1=84580&r2=84581&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/tools/lli/lli.cpp (original)
+++ llvm/branches/Apple/Leela/tools/lli/lli.cpp Mon Oct 19 19:54:25 2009
@@ -148,7 +148,7 @@
return 1;
case ' ': break;
case '0': OLvl = CodeGenOpt::None; break;
- case '1':
+ case '1': OLvl = CodeGenOpt::Less; break;
case '2': OLvl = CodeGenOpt::Default; break;
case '3': OLvl = CodeGenOpt::Aggressive; break;
}
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