[llvm-branch-commits] [llvm-branch] r84594 - in /llvm/branches/Apple/Leela/lib: CodeGen/PrologEpilogInserter.cpp Target/ARM/ARMBaseRegisterInfo.cpp Target/ARM/ARMBaseRegisterInfo.h Target/ARM/Thumb1RegisterInfo.cpp Target/ARM/Thumb1RegisterInfo.h
Bill Wendling
isanbard at gmail.com
Mon Oct 19 21:06:03 PDT 2009
Author: void
Date: Mon Oct 19 23:06:03 2009
New Revision: 84594
URL: http://llvm.org/viewvc/llvm-project?rev=84594&view=rev
Log:
$ svn merge -c 84585 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r84585 into '.':
U lib/CodeGen/PrologEpilogInserter.cpp
U lib/Target/ARM/ARMBaseRegisterInfo.h
U lib/Target/ARM/ARMBaseRegisterInfo.cpp
$ svn merge -c 84587 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r84587 into '.':
U lib/Target/ARM/Thumb1RegisterInfo.cpp
U lib/Target/ARM/Thumb1RegisterInfo.h
Modified:
llvm/branches/Apple/Leela/lib/CodeGen/PrologEpilogInserter.cpp
llvm/branches/Apple/Leela/lib/Target/ARM/ARMBaseRegisterInfo.cpp
llvm/branches/Apple/Leela/lib/Target/ARM/ARMBaseRegisterInfo.h
llvm/branches/Apple/Leela/lib/Target/ARM/Thumb1RegisterInfo.cpp
llvm/branches/Apple/Leela/lib/Target/ARM/Thumb1RegisterInfo.h
Modified: llvm/branches/Apple/Leela/lib/CodeGen/PrologEpilogInserter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/CodeGen/PrologEpilogInserter.cpp?rev=84594&r1=84593&r2=84594&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/CodeGen/PrologEpilogInserter.cpp (original)
+++ llvm/branches/Apple/Leela/lib/CodeGen/PrologEpilogInserter.cpp Mon Oct 19 23:06:03 2009
@@ -787,11 +787,6 @@
if (Reg == 0)
continue;
if (!TargetRegisterInfo::isVirtualRegister(Reg)) {
- // If we have an active scavenged register, we shouldn't be
- // seeing any references to it.
- assert (Reg != CurrentScratchReg
- && "overlapping use of scavenged frame index register!");
-
// If we have a previous scratch reg, check and see if anything
// here kills whatever value is in there.
if (Reg == PrevScratchReg) {
Modified: llvm/branches/Apple/Leela/lib/Target/ARM/ARMBaseRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=84594&r1=84593&r2=84594&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original)
+++ llvm/branches/Apple/Leela/lib/Target/ARM/ARMBaseRegisterInfo.cpp Mon Oct 19 23:06:03 2009
@@ -934,6 +934,10 @@
requiresRegisterScavenging(const MachineFunction &MF) const {
return true;
}
+bool ARMBaseRegisterInfo::
+requiresFrameIndexScavenging(const MachineFunction &MF) const {
+ return true;
+}
// hasReservedCallFrame - Under normal circumstances, when a frame pointer is
// not required, we reserve argument space for call sites in the function
@@ -1010,17 +1014,6 @@
MBB.erase(I);
}
-/// findScratchRegister - Find a 'free' ARM register. If register scavenger
-/// is not being used, R12 is available. Otherwise, try for a call-clobbered
-/// register first and then a spilled callee-saved register if that fails.
-static
-unsigned findScratchRegister(RegScavenger *RS, const TargetRegisterClass *RC,
- ARMFunctionInfo *AFI) {
- unsigned Reg = RS ? RS->FindUnusedReg(RC) : (unsigned) ARM::R12;
- assert(!AFI->isThumb1OnlyFunction());
- return Reg;
-}
-
unsigned
ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
int SPAdj, int *Value,
@@ -1075,14 +1068,7 @@
(MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4) &&
"This code isn't needed if offset already handled!");
- // Insert a set of r12 with the full address: r12 = sp + offset
- // If the offset we have is too large to fit into the instruction, we need
- // to form it with a series of ADDri's. Do this by taking 8-bit chunks
- // out of 'Offset'.
- unsigned ScratchReg = findScratchRegister(RS, ARM::GPRRegisterClass, AFI);
- if (ScratchReg == 0)
- // No register is "free". Scavenge a register.
- ScratchReg = RS->scavengeRegister(ARM::GPRRegisterClass, II, SPAdj);
+ unsigned ScratchReg = 0;
int PIdx = MI.findFirstPredOperandIdx();
ARMCC::CondCodes Pred = (PIdx == -1)
? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
@@ -1091,6 +1077,8 @@
// Must be addrmode4.
MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false);
else {
+ ScratchReg = MF.getRegInfo().createVirtualRegister(ARM::GPRRegisterClass);
+ *Value = Offset;
if (!AFI->isThumbFunction())
emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
Offset, Pred, PredReg, TII);
@@ -1101,7 +1089,7 @@
}
MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
}
- return 0;
+ return ScratchReg;
}
/// Move iterator pass the next bunch of callee save load / store ops for
Modified: llvm/branches/Apple/Leela/lib/Target/ARM/ARMBaseRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/ARM/ARMBaseRegisterInfo.h?rev=84594&r1=84593&r2=84594&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/ARM/ARMBaseRegisterInfo.h (original)
+++ llvm/branches/Apple/Leela/lib/Target/ARM/ARMBaseRegisterInfo.h Mon Oct 19 23:06:03 2009
@@ -122,6 +122,8 @@
virtual bool requiresRegisterScavenging(const MachineFunction &MF) const;
+ virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const;
+
virtual bool hasReservedCallFrame(MachineFunction &MF) const;
virtual void eliminateCallFramePseudoInstr(MachineFunction &MF,
Modified: llvm/branches/Apple/Leela/lib/Target/ARM/Thumb1RegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/ARM/Thumb1RegisterInfo.cpp?rev=84594&r1=84593&r2=84594&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/ARM/Thumb1RegisterInfo.cpp (original)
+++ llvm/branches/Apple/Leela/lib/Target/ARM/Thumb1RegisterInfo.cpp Mon Oct 19 23:06:03 2009
@@ -77,18 +77,6 @@
return TargetRegisterInfo::getPhysicalRegisterRegClass(Reg, VT);
}
-bool
-Thumb1RegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
- return true;
-}
-
-bool
-Thumb1RegisterInfo::requiresFrameIndexScavenging(const MachineFunction &MF)
- const {
- return true;
-}
-
-
bool Thumb1RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
const MachineFrameInfo *FFI = MF.getFrameInfo();
unsigned CFSize = FFI->getMaxCallFrameSize();
Modified: llvm/branches/Apple/Leela/lib/Target/ARM/Thumb1RegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/ARM/Thumb1RegisterInfo.h?rev=84594&r1=84593&r2=84594&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/ARM/Thumb1RegisterInfo.h (original)
+++ llvm/branches/Apple/Leela/lib/Target/ARM/Thumb1RegisterInfo.h Mon Oct 19 23:06:03 2009
@@ -40,9 +40,6 @@
const TargetRegisterClass *
getPhysicalRegisterRegClass(unsigned Reg, EVT VT = MVT::Other) const;
- bool requiresRegisterScavenging(const MachineFunction &MF) const;
- bool requiresFrameIndexScavenging(const MachineFunction &MF) const;
-
bool hasReservedCallFrame(MachineFunction &MF) const;
void eliminateCallFramePseudoInstr(MachineFunction &MF,
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