[llvm-branch-commits] [llvm-branch] r76116 - in /llvm/branches/Apple/Bender-SWB: lib/Target/X86/X86InstrInfo.cpp test/CodeGen/X86/2009-07-16-LoadFoldingBug.ll

[Bill Wendling]

Author: void
Date: Thu Jul 16 17:16:20 2009
New Revision: 76116

URL: http://llvm.org/viewvc/llvm-project?rev=76116&view=rev
Log:
--- Merging r76094 into '.':
A    test/CodeGen/X86/2009-07-16-LoadFoldingBug.ll
U    lib/Target/X86/X86InstrInfo.cpp

With recent MC changes, RIP base register is explicitly modeled. Make sure we
add it when x86 V_SET0 / V_SETALLONES (by transforming it into a constpool load)
into the use instruction.

Added:
    llvm/branches/Apple/Bender-SWB/test/CodeGen/X86/2009-07-16-LoadFoldingBug.ll
      - copied unchanged from r76094, llvm/trunk/test/CodeGen/X86/2009-07-16-LoadFoldingBug.ll
Modified:
    llvm/branches/Apple/Bender-SWB/lib/Target/X86/X86InstrInfo.cpp

Modified: llvm/branches/Apple/Bender-SWB/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Bender-SWB/lib/Target/X86/X86InstrInfo.cpp?rev=76116&r1=76115&r2=76116&view=diff

==============================================================================
--- llvm/branches/Apple/Bender-SWB/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/branches/Apple/Bender-SWB/lib/Target/X86/X86InstrInfo.cpp Thu Jul 16 17:16:20 2009
@@ -2250,13 +2250,15 @@
 
     // x86-32 PIC requires a PIC base register for constant pools.
     unsigned PICBase = 0;
-    if (TM.getRelocationModel() == Reloc::PIC_ &&
-        !TM.getSubtarget<X86Subtarget>().is64Bit())
-      // FIXME: PICBase = TM.getInstrInfo()->getGlobalBaseReg(&MF);
-      // This doesn't work for several reasons.
-      // 1. GlobalBaseReg may have been spilled.
-      // 2. It may not be live at MI.
-      return false;
+    if (TM.getRelocationModel() == Reloc::PIC_)
+      if (TM.getSubtarget<X86Subtarget>().is64Bit())
+        PICBase = X86::RIP;
+      else 
+        // FIXME: PICBase = TM.getInstrInfo()->getGlobalBaseReg(&MF);
+        // This doesn't work for several reasons.
+        // 1. GlobalBaseReg may have been spilled.
+        // 2. It may not be live at MI.
+        return false;
 
     // Create a v4i32 constant-pool entry.
     MachineConstantPool &MCP = *MF.getConstantPool();