[llvm-branch-commits] [llvm-branch] r75032 - /llvm/branches/Apple/Bender/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

[Bill Wendling]

Author: void
Date: Wed Jul  8 14:45:30 2009
New Revision: 75032

URL: http://llvm.org/viewvc/llvm-project?rev=75032&view=rev
Log:
In the current AMD backend (AMDILISelLowering.cpp), they currently set extract
subvector to be custom lowered but LLVM 2115 doesn't currently allow custom
lowering of that node, e.g., in select_uchar8_uchar8

  0x100879198: v2i8 = extract_subvector 0x100878fa8, 0x100879290

This gets transformed to

 0x10087f328: v2i8,ch = load 0x10030de58, 0x10087ef48, 0x100878408

which they don't expect.

Modified:
    llvm/branches/Apple/Bender/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

Modified: llvm/branches/Apple/Bender/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Bender/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=75032&r1=75031&r2=75032&view=diff

==============================================================================
--- llvm/branches/Apple/Bender/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/branches/Apple/Bender/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Wed Jul  8 14:45:30 2009
@@ -5039,8 +5039,18 @@
   // We know that operand #0 is the Vec vector.  For now we assume the index
   // is a constant and that the extracted result is a supported hardware type.
   SDValue Vec = Op.getOperand(0);
+  MVT TVT = Vec.getValueType();
   SDValue Idx = LegalizeOp(Op.getOperand(1));
 
+  if (TLI.getOperationAction(ISD::EXTRACT_SUBVECTOR, TVT) ==
+      TargetLowering::Custom) {
+    Vec = LegalizeOp(Vec);
+    Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
+    SDValue Tmp3 = TLI.LowerOperation(Op, DAG);
+    if (Tmp3.getNode())
+      return Tmp3;
+  }
+
   unsigned NumElems = Vec.getValueType().getVectorNumElements();
 
   if (NumElems == Op.getValueType().getVectorNumElements()) {