[Lldb-commits] [lldb] [llvm] Revert "[AArch64] Fix definition of system register move instructions" (PR #201137)
via lldb-commits
lldb-commits at lists.llvm.org
Tue Jun 2 07:53:25 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-lldb
Author: Lukacma
<details>
<summary>Changes</summary>
Reverts llvm/llvm-project#<!-- -->185709
---
Patch is 217.22 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/201137.diff
34 Files Affected:
- (modified) lldb/test/API/commands/register/aarch64_dynamic_regset/main.c (+1-1)
- (modified) lldb/test/API/commands/register/aarch64_sve_registers/rw_access_static_config/main.c (+1-1)
- (modified) llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp (+2-7)
- (modified) llvm/lib/Target/AArch64/AArch64InstrFormats.td (+4-6)
- (modified) llvm/lib/Target/AArch64/AArch64InstrInfo.td (+10-12)
- (modified) llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td (+2-2)
- (modified) llvm/lib/Target/AArch64/AArch64SystemOperands.td (+1047-1047)
- (modified) llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp (+5-10)
- (modified) llvm/test/CodeGen/AArch64/aarch64-sme-za-call-lowering.ll (+6-6)
- (modified) llvm/test/CodeGen/AArch64/aarch64-sysreg128.ll (+5-5)
- (removed) llvm/test/CodeGen/AArch64/arm64-invalid-sys-reg.ll (-26)
- (added) llvm/test/CodeGen/AArch64/arm64-named-reg-notareg.ll (+13)
- (modified) llvm/test/CodeGen/AArch64/expand-sme-pseudos.mir (+4-4)
- (modified) llvm/test/CodeGen/AArch64/machine-sme-abi-find-insert-pt.mir (+13-13)
- (modified) llvm/test/CodeGen/AArch64/machine-sme-abi-skip-debug-inst.mir (+5-4)
- (modified) llvm/test/CodeGen/AArch64/sme-abi-eh-liveins.mir (+5-5)
- (modified) llvm/test/CodeGen/AArch64/sme-lazy-sve-nzcv-live.mir (+3-3)
- (modified) llvm/test/CodeGen/AArch64/special-reg.ll (+11-24)
- (modified) llvm/test/MC/AArch64/arm64-system-encoding.s (+4-18)
- (modified) llvm/test/MC/AArch64/armv9-mrrs-diagnostics.s (-23)
- (modified) llvm/test/MC/AArch64/armv9-mrrs.s (-26)
- (modified) llvm/test/MC/AArch64/armv9-msrr-diagnostics.s (-23)
- (modified) llvm/test/MC/AArch64/armv9-msrr.s (-26)
- (modified) llvm/test/MC/AArch64/basic-a64-instructions.s (+4)
- (modified) llvm/test/MC/Disassembler/AArch64/armv8.2a-uao.txt (+4-4)
- (modified) llvm/test/MC/Disassembler/AArch64/armv8.4a-dit.txt (+3-2)
- (modified) llvm/test/MC/Disassembler/AArch64/armv8.5a-dataproc.txt (+2-2)
- (modified) llvm/test/MC/Disassembler/AArch64/armv8.5a-mte.txt (+5-4)
- (modified) llvm/test/MC/Disassembler/AArch64/armv8.5a-sb.txt (+2-1)
- (modified) llvm/test/MC/Disassembler/AArch64/armv8.5a-ssbs.txt (+4-4)
- (modified) llvm/test/MC/Disassembler/AArch64/armv8.7a-wfxt.txt (+3-3)
- (modified) llvm/test/MC/Disassembler/AArch64/armv8.7a-xs.txt (+17-19)
- (modified) llvm/test/MC/Disassembler/AArch64/armv8.8a-nmi.txt (+17-17)
- (modified) llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt (+4)
``````````diff
diff --git a/lldb/test/API/commands/register/aarch64_dynamic_regset/main.c b/lldb/test/API/commands/register/aarch64_dynamic_regset/main.c
index cef79caaebc34..93100f01502f8 100644
--- a/lldb/test/API/commands/register/aarch64_dynamic_regset/main.c
+++ b/lldb/test/API/commands/register/aarch64_dynamic_regset/main.c
@@ -75,7 +75,7 @@ void set_sve_registers() {
int main(int argc, char *argv[]) {
if (argc > 1) {
// Enable streaming mode SVE and the ZA array storage.
- asm volatile("smstart");
+ asm volatile("msr s0_3_c4_c7_3, xzr" /*smstart*/);
}
// If we have SVE or SME, set the SVE registers.
diff --git a/lldb/test/API/commands/register/aarch64_sve_registers/rw_access_static_config/main.c b/lldb/test/API/commands/register/aarch64_sve_registers/rw_access_static_config/main.c
index abff9734577ad..1e654ad26b1ce 100644
--- a/lldb/test/API/commands/register/aarch64_sve_registers/rw_access_static_config/main.c
+++ b/lldb/test/API/commands/register/aarch64_sve_registers/rw_access_static_config/main.c
@@ -9,7 +9,7 @@
#define PR_SME_SET_VL 63
#endif
-#define SMSTART_SM() asm volatile("smstart SM")
+#define SMSTART_SM() asm volatile("msr s0_3_c4_c3_3, xzr" /*smstart sm*/)
void write_sve_regs() {
// We assume the smefa64 feature is present, which allows ffr access
diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
index f25f45a058aa8..3fad1ef357762 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -4268,14 +4268,9 @@ static int getIntOperandFromRegisterString(StringRef RegString) {
"Unexpected non-integer value in special register string.");
(void)AllIntFields;
- if (Ops[0] < 2 || Ops[1] > 7 || Ops[2] > 15 || Ops[3] > 15 || Ops[4] > 7)
- return -1;
-
// Need to combine the integer fields of the string into a single value
- // based on the bit encoding of MRS/MSR instruction. We also mask Ops[0], as
- // top bit as it is implicitly assumed to be 1 for MRS/MSR instruction and is
- // not part of the encoding.
- return ((Ops[0] & 0x1) << 14) | (Ops[1] << 11) | (Ops[2] << 7) |
+ // based on the bit encoding of MRS/MSR instruction.
+ return (Ops[0] << 14) | (Ops[1] << 11) | (Ops[2] << 7) |
(Ops[3] << 3) | (Ops[4]);
}
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index 67474aea6c537..c252f4933dc18 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -2024,9 +2024,8 @@ def TIndexhint_op : Operand<i32> {
class MRSI : RtSystemI<1, (outs GPR64:$Rt), (ins mrs_sysreg_op:$systemreg),
"mrs", "\t$Rt, $systemreg"> {
- bits<15> systemreg;
- let Inst{20}= 0b1;
- let Inst{19-5} = systemreg;
+ bits<16> systemreg;
+ let Inst{20-5} = systemreg;
let DecoderNamespace = "Fallback";
// The MRS is set as a NZCV setting instruction. Not all MRS instructions
// require doing this. The alternative was to explicitly model each one, but
@@ -2040,9 +2039,8 @@ class MRSI : RtSystemI<1, (outs GPR64:$Rt), (ins mrs_sysreg_op:$systemreg),
// would do it, but feels like overkill at this point.
class MSRI : RtSystemI<0, (outs), (ins msr_sysreg_op:$systemreg, GPR64:$Rt),
"msr", "\t$systemreg, $Rt"> {
- bits<15> systemreg;
- let Inst{20} = 0b1;
- let Inst{19-5} = systemreg;
+ bits<16> systemreg;
+ let Inst{20-5} = systemreg;
let DecoderNamespace = "Fallback";
}
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 79dea283a1d23..82d4fcedc5a5e 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -2505,35 +2505,35 @@ def HWASAN_CHECK_MEMACCESS_SHORTGRANULES_FIXEDSHADOW : Pseudo<
}
// The virtual cycle counter register is CNTVCT_EL0.
-def : Pat<(readcyclecounter), (MRS 0x5f02)>;
+def : Pat<(readcyclecounter), (MRS 0xdf02)>;
// FPCR and FPSR registers.
let Uses = [FPCR] in
def MRS_FPCR : Pseudo<(outs GPR64:$dst), (ins),
[(set GPR64:$dst, (int_aarch64_get_fpcr))]>,
- PseudoInstExpansion<(MRS GPR64:$dst, 0x5a20)>,
+ PseudoInstExpansion<(MRS GPR64:$dst, 0xda20)>,
Sched<[WriteSys]>;
let Defs = [FPCR] in
def MSR_FPCR : Pseudo<(outs), (ins GPR64:$val),
[(int_aarch64_set_fpcr i64:$val)]>,
- PseudoInstExpansion<(MSR 0x5a20, GPR64:$val)>,
+ PseudoInstExpansion<(MSR 0xda20, GPR64:$val)>,
Sched<[WriteSys]>;
let Uses = [FPSR] in
def MRS_FPSR : Pseudo<(outs GPR64:$dst), (ins),
[(set GPR64:$dst, (int_aarch64_get_fpsr))]>,
- PseudoInstExpansion<(MRS GPR64:$dst, 0x5a21)>,
+ PseudoInstExpansion<(MRS GPR64:$dst, 0xda21)>,
Sched<[WriteSys]>;
let Defs = [FPSR] in
def MSR_FPSR : Pseudo<(outs), (ins GPR64:$val),
[(int_aarch64_set_fpsr i64:$val)]>,
- PseudoInstExpansion<(MSR 0x5a21, GPR64:$val)>,
+ PseudoInstExpansion<(MSR 0xda21, GPR64:$val)>,
Sched<[WriteSys]>;
let Defs = [FPMR] in
def MSR_FPMR : Pseudo<(outs), (ins GPR64:$val),
[(int_aarch64_set_fpmr i64:$val)]>,
- PseudoInstExpansion<(MSR 0x5a22, GPR64:$val)>,
+ PseudoInstExpansion<(MSR 0xda22, GPR64:$val)>,
Sched<[WriteSys]>;
// Generic system instructions
@@ -11732,18 +11732,16 @@ def MRRS : RtSystemI128<1,
(outs MrrsMssrPairClassOperand:$Rt), (ins mrs_sysreg_op:$systemreg),
"mrrs", "\t$Rt, $systemreg">
{
- bits<15> systemreg;
- let Inst{20}= 0b1;
- let Inst{19-5} = systemreg;
+ bits<16> systemreg;
+ let Inst{20-5} = systemreg;
}
def MSRR : RtSystemI128<0,
(outs), (ins msr_sysreg_op:$systemreg, MrrsMssrPairClassOperand:$Rt),
"msrr", "\t$systemreg, $Rt">
{
- bits<15> systemreg;
- let Inst{20} = 0b1;
- let Inst{19-5} = systemreg;
+ bits<16> systemreg;
+ let Inst{20-5} = systemreg;
}
//===----------------------------===//
diff --git a/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
index 3a1a8ada697ab..022fed6473486 100644
--- a/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
@@ -281,9 +281,9 @@ def RestoreZAPseudo :
// Read and write TPIDR2_EL0
def : Pat<(int_aarch64_sme_set_tpidr2 i64:$val),
- (MSR 0x5e85, GPR64:$val)>;
+ (MSR 0xde85, GPR64:$val)>;
def : Pat<(i64 (int_aarch64_sme_get_tpidr2)),
- (MRS 0x5e85)>;
+ (MRS 0xde85)>;
} // End let Predicates = [HasSMEandIsNonStreamingSafe]
diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
index 5824bd9009257..bcd1786a0e9ea 100644
--- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
+++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
@@ -1067,11 +1067,11 @@ let Requires = ["AArch64::FeatureTLBIW"] in {
// MRS/MSR (system register read/write) instruction options.
//===----------------------------------------------------------------------===//
-class SysReg<string name, bit op0, bits<3> op1, bits<4> crn, bits<4> crm,
+class SysReg<string name, bits<2> op0, bits<3> op1, bits<4> crn, bits<4> crm,
bits<3> op2> {
string Name = name;
- bits<15> Encoding;
- let Encoding{14} = op0;
+ bits<16> Encoding;
+ let Encoding{15-14} = op0;
let Encoding{13-11} = op1;
let Encoding{10-7} = crn;
let Encoding{6-3} = crm;
@@ -1101,21 +1101,21 @@ def lookupSysRegByName : SearchIndex {
let Key = ["Name"];
}
-class RWSysReg<string name, bit op0, bits<3> op1, bits<4> crn, bits<4> crm,
+class RWSysReg<string name, bits<2> op0, bits<3> op1, bits<4> crn, bits<4> crm,
bits<3> op2>
: SysReg<name, op0, op1, crn, crm, op2> {
let Readable = 1;
let Writeable = 1;
}
-class ROSysReg<string name, bit op0, bits<3> op1, bits<4> crn, bits<4> crm,
+class ROSysReg<string name, bits<2> op0, bits<3> op1, bits<4> crn, bits<4> crm,
bits<3> op2>
: SysReg<name, op0, op1, crn, crm, op2> {
let Readable = 1;
let Writeable = 0;
}
-class WOSysReg<string name, bit op0, bits<3> op1, bits<4> crn, bits<4> crm,
+class WOSysReg<string name, bits<2> op0, bits<3> op1, bits<4> crn, bits<4> crm,
bits<3> op2>
: SysReg<name, op0, op1, crn, crm, op2> {
let Readable = 0;
@@ -1127,186 +1127,186 @@ class WOSysReg<string name, bit op0, bits<3> op1, bits<4> crn, bits<4> crm,
//===----------------------
// Op0 Op1 CRn CRm Op2
-def : ROSysReg<"MDCCSR_EL0", 0b0, 0b011, 0b0000, 0b0001, 0b000>;
-def : ROSysReg<"DBGDTRRX_EL0", 0b0, 0b011, 0b0000, 0b0101, 0b000>;
-def : ROSysReg<"MDRAR_EL1", 0b0, 0b000, 0b0001, 0b0000, 0b000>;
-def : ROSysReg<"OSLSR_EL1", 0b0, 0b000, 0b0001, 0b0001, 0b100>;
-def : ROSysReg<"DBGAUTHSTATUS_EL1", 0b0, 0b000, 0b0111, 0b1110, 0b110>;
-def : ROSysReg<"PMCEID0_EL0", 0b1, 0b011, 0b1001, 0b1100, 0b110>;
-def : ROSysReg<"PMCEID1_EL0", 0b1, 0b011, 0b1001, 0b1100, 0b111>;
-def : ROSysReg<"PMMIR_EL1", 0b1, 0b000, 0b1001, 0b1110, 0b110>;
-def : ROSysReg<"MIDR_EL1", 0b1, 0b000, 0b0000, 0b0000, 0b000>;
-def : ROSysReg<"CCSIDR_EL1", 0b1, 0b001, 0b0000, 0b0000, 0b000>;
+def : ROSysReg<"MDCCSR_EL0", 0b10, 0b011, 0b0000, 0b0001, 0b000>;
+def : ROSysReg<"DBGDTRRX_EL0", 0b10, 0b011, 0b0000, 0b0101, 0b000>;
+def : ROSysReg<"MDRAR_EL1", 0b10, 0b000, 0b0001, 0b0000, 0b000>;
+def : ROSysReg<"OSLSR_EL1", 0b10, 0b000, 0b0001, 0b0001, 0b100>;
+def : ROSysReg<"DBGAUTHSTATUS_EL1", 0b10, 0b000, 0b0111, 0b1110, 0b110>;
+def : ROSysReg<"PMCEID0_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b110>;
+def : ROSysReg<"PMCEID1_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b111>;
+def : ROSysReg<"PMMIR_EL1", 0b11, 0b000, 0b1001, 0b1110, 0b110>;
+def : ROSysReg<"MIDR_EL1", 0b11, 0b000, 0b0000, 0b0000, 0b000>;
+def : ROSysReg<"CCSIDR_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b000>;
//v8.3 CCIDX - extending the CCsIDr number of sets
-def : ROSysReg<"CCSIDR2_EL1", 0b1, 0b001, 0b0000, 0b0000, 0b010> {
+def : ROSysReg<"CCSIDR2_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b010> {
let Requires = [{ {AArch64::FeatureCCIDX} }];
}
-def : ROSysReg<"CLIDR_EL1", 0b1, 0b001, 0b0000, 0b0000, 0b001>;
-def : ROSysReg<"CTR_EL0", 0b1, 0b011, 0b0000, 0b0000, 0b001>;
-def : ROSysReg<"MPIDR_EL1", 0b1, 0b000, 0b0000, 0b0000, 0b101>;
-def : ROSysReg<"REVIDR_EL1", 0b1, 0b000, 0b0000, 0b0000, 0b110>;
-def : ROSysReg<"AIDR_EL1", 0b1, 0b001, 0b0000, 0b0000, 0b111>;
-def : ROSysReg<"DCZID_EL0", 0b1, 0b011, 0b0000, 0b0000, 0b111>;
-def : ROSysReg<"ID_PFR0_EL1", 0b1, 0b000, 0b0000, 0b0001, 0b000>;
-def : ROSysReg<"ID_PFR1_EL1", 0b1, 0b000, 0b0000, 0b0001, 0b001>;
-def : ROSysReg<"ID_PFR2_EL1", 0b1, 0b000, 0b0000, 0b0011, 0b100> {
+def : ROSysReg<"CLIDR_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b001>;
+def : ROSysReg<"CTR_EL0", 0b11, 0b011, 0b0000, 0b0000, 0b001>;
+def : ROSysReg<"MPIDR_EL1", 0b11, 0b000, 0b0000, 0b0000, 0b101>;
+def : ROSysReg<"REVIDR_EL1", 0b11, 0b000, 0b0000, 0b0000, 0b110>;
+def : ROSysReg<"AIDR_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b111>;
+def : ROSysReg<"DCZID_EL0", 0b11, 0b011, 0b0000, 0b0000, 0b111>;
+def : ROSysReg<"ID_PFR0_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b000>;
+def : ROSysReg<"ID_PFR1_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b001>;
+def : ROSysReg<"ID_PFR2_EL1", 0b11, 0b000, 0b0000, 0b0011, 0b100> {
let Requires = [{ {AArch64::FeatureSpecRestrict} }];
}
-def : ROSysReg<"ID_DFR0_EL1", 0b1, 0b000, 0b0000, 0b0001, 0b010>;
-def : ROSysReg<"ID_DFR1_EL1", 0b1, 0b000, 0b0000, 0b0011, 0b101>;
-def : ROSysReg<"ID_AFR0_EL1", 0b1, 0b000, 0b0000, 0b0001, 0b011>;
-def : ROSysReg<"ID_MMFR0_EL1", 0b1, 0b000, 0b0000, 0b0001, 0b100>;
-def : ROSysReg<"ID_MMFR1_EL1", 0b1, 0b000, 0b0000, 0b0001, 0b101>;
-def : ROSysReg<"ID_MMFR2_EL1", 0b1, 0b000, 0b0000, 0b0001, 0b110>;
-def : ROSysReg<"ID_MMFR3_EL1", 0b1, 0b000, 0b0000, 0b0001, 0b111>;
-def : ROSysReg<"ID_ISAR0_EL1", 0b1, 0b000, 0b0000, 0b0010, 0b000>;
-def : ROSysReg<"ID_ISAR1_EL1", 0b1, 0b000, 0b0000, 0b0010, 0b001>;
-def : ROSysReg<"ID_ISAR2_EL1", 0b1, 0b000, 0b0000, 0b0010, 0b010>;
-def : ROSysReg<"ID_ISAR3_EL1", 0b1, 0b000, 0b0000, 0b0010, 0b011>;
-def : ROSysReg<"ID_ISAR4_EL1", 0b1, 0b000, 0b0000, 0b0010, 0b100>;
-def : ROSysReg<"ID_ISAR5_EL1", 0b1, 0b000, 0b0000, 0b0010, 0b101>;
-def : ROSysReg<"ID_ISAR6_EL1", 0b1, 0b000, 0b0000, 0b0010, 0b111> {
+def : ROSysReg<"ID_DFR0_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b010>;
+def : ROSysReg<"ID_DFR1_EL1", 0b11, 0b000, 0b0000, 0b0011, 0b101>;
+def : ROSysReg<"ID_AFR0_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b011>;
+def : ROSysReg<"ID_MMFR0_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b100>;
+def : ROSysReg<"ID_MMFR1_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b101>;
+def : ROSysReg<"ID_MMFR2_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b110>;
+def : ROSysReg<"ID_MMFR3_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b111>;
+def : ROSysReg<"ID_ISAR0_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b000>;
+def : ROSysReg<"ID_ISAR1_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b001>;
+def : ROSysReg<"ID_ISAR2_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b010>;
+def : ROSysReg<"ID_ISAR3_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b011>;
+def : ROSysReg<"ID_ISAR4_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b100>;
+def : ROSysReg<"ID_ISAR5_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b101>;
+def : ROSysReg<"ID_ISAR6_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b111> {
let Requires = [{ {AArch64::HasV8_2aOps} }];
}
-def : ROSysReg<"ID_AA64PFR0_EL1", 0b1, 0b000, 0b0000, 0b0100, 0b000>;
-def : ROSysReg<"ID_AA64PFR1_EL1", 0b1, 0b000, 0b0000, 0b0100, 0b001>;
-def : ROSysReg<"ID_AA64PFR2_EL1", 0b1, 0b000, 0b0000, 0b0100, 0b010>;
-def : ROSysReg<"ID_AA64DFR0_EL1", 0b1, 0b000, 0b0000, 0b0101, 0b000>;
-def : ROSysReg<"ID_AA64DFR1_EL1", 0b1, 0b000, 0b0000, 0b0101, 0b001>;
-def : ROSysReg<"ID_AA64DFR2_EL1", 0b1, 0b000, 0b0000, 0b0101, 0b010>;
-def : ROSysReg<"ID_AA64AFR0_EL1", 0b1, 0b000, 0b0000, 0b0101, 0b100>;
-def : ROSysReg<"ID_AA64AFR1_EL1", 0b1, 0b000, 0b0000, 0b0101, 0b101>;
-def : ROSysReg<"ID_AA64ISAR0_EL1", 0b1, 0b000, 0b0000, 0b0110, 0b000>;
-def : ROSysReg<"ID_AA64ISAR1_EL1", 0b1, 0b000, 0b0000, 0b0110, 0b001>;
-def : ROSysReg<"ID_AA64ISAR2_EL1", 0b1, 0b000, 0b0000, 0b0110, 0b010>;
-def : ROSysReg<"ID_AA64ISAR3_EL1", 0b1, 0b000, 0b0000, 0b0110, 0b011>;
-def : ROSysReg<"ID_AA64MMFR0_EL1", 0b1, 0b000, 0b0000, 0b0111, 0b000>;
-def : ROSysReg<"ID_AA64MMFR1_EL1", 0b1, 0b000, 0b0000, 0b0111, 0b001>;
-def : ROSysReg<"ID_AA64MMFR2_EL1", 0b1, 0b000, 0b0000, 0b0111, 0b010>;
-def : ROSysReg<"ID_AA64MMFR3_EL1", 0b1, 0b000, 0b0000, 0b0111, 0b011>;
-def : ROSysReg<"ID_AA64MMFR4_EL1", 0b1, 0b000, 0b0000, 0b0111, 0b100>;
-def : ROSysReg<"MVFR0_EL1", 0b1, 0b000, 0b0000, 0b0011, 0b000>;
-def : ROSysReg<"MVFR1_EL1", 0b1, 0b000, 0b0000, 0b0011, 0b001>;
-def : ROSysReg<"MVFR2_EL1", 0b1, 0b000, 0b0000, 0b0011, 0b010>;
-def : ROSysReg<"RVBAR_EL1", 0b1, 0b000, 0b1100, 0b0000, 0b001>;
-def : ROSysReg<"RVBAR_EL2", 0b1, 0b100, 0b1100, 0b0000, 0b001>;
-def : ROSysReg<"RVBAR_EL3", 0b1, 0b110, 0b1100, 0b0000, 0b001>;
-def : ROSysReg<"ISR_EL1", 0b1, 0b000, 0b1100, 0b0001, 0b000>;
-def : ROSysReg<"CNTPCT_EL0", 0b1, 0b011, 0b1110, 0b0000, 0b001>;
-def : ROSysReg<"CNTVCT_EL0", 0b1, 0b011, 0b1110, 0b0000, 0b010>;
-def : ROSysReg<"ID_MMFR4_EL1", 0b1, 0b000, 0b0000, 0b0010, 0b110>;
-def : ROSysReg<"ID_MMFR5_EL1", 0b1, 0b000, 0b0000, 0b0011, 0b110>;
+def : ROSysReg<"ID_AA64PFR0_EL1", 0b11, 0b000, 0b0000, 0b0100, 0b000>;
+def : ROSysReg<"ID_AA64PFR1_EL1", 0b11, 0b000, 0b0000, 0b0100, 0b001>;
+def : ROSysReg<"ID_AA64PFR2_EL1", 0b11, 0b000, 0b0000, 0b0100, 0b010>;
+def : ROSysReg<"ID_AA64DFR0_EL1", 0b11, 0b000, 0b0000, 0b0101, 0b000>;
+def : ROSysReg<"ID_AA64DFR1_EL1", 0b11, 0b000, 0b0000, 0b0101, 0b001>;
+def : ROSysReg<"ID_AA64DFR2_EL1", 0b11, 0b000, 0b0000, 0b0101, 0b010>;
+def : ROSysReg<"ID_AA64AFR0_EL1", 0b11, 0b000, 0b0000, 0b0101, 0b100>;
+def : ROSysReg<"ID_AA64AFR1_EL1", 0b11, 0b000, 0b0000, 0b0101, 0b101>;
+def : ROSysReg<"ID_AA64ISAR0_EL1", 0b11, 0b000, 0b0000, 0b0110, 0b000>;
+def : ROSysReg<"ID_AA64ISAR1_EL1", 0b11, 0b000, 0b0000, 0b0110, 0b001>;
+def : ROSysReg<"ID_AA64ISAR2_EL1", 0b11, 0b000, 0b0000, 0b0110, 0b010>;
+def : ROSysReg<"ID_AA64ISAR3_EL1", 0b11, 0b000, 0b0000, 0b0110, 0b011>;
+def : ROSysReg<"ID_AA64MMFR0_EL1", 0b11, 0b000, 0b0000, 0b0111, 0b000>;
+def : ROSysReg<"ID_AA64MMFR1_EL1", 0b11, 0b000, 0b0000, 0b0111, 0b001>;
+def : ROSysReg<"ID_AA64MMFR2_EL1", 0b11, 0b000, 0b0000, 0b0111, 0b010>;
+def : ROSysReg<"ID_AA64MMFR3_EL1", 0b11, 0b000, 0b0000, 0b0111, 0b011>;
+def : ROSysReg<"ID_AA64MMFR4_EL1", 0b11, 0b000, 0b0000, 0b0111, 0b100>;
+def : ROSysReg<"MVFR0_EL1", 0b11, 0b000, 0b0000, 0b0011, 0b000>;
+def : ROSysReg<"MVFR1_EL1", 0b11, 0b000, 0b0000, 0b0011, 0b001>;
+def : ROSysReg<"MVFR2_EL1", 0b11, 0b000, 0b0000, 0b0011, 0b010>;
+def : ROSysReg<"RVBAR_EL1", 0b11, 0b000, 0b1100, 0b0000, 0b001>;
+def : ROSysReg<"RVBAR_EL2", 0b11, 0b100, 0b1100, 0b0000, 0b001>;
+def : ROSysReg<"RVBAR_EL3", 0b11, 0b110, 0b1100, 0b0000, 0b001>;
+def : ROSysReg<"ISR_EL1", 0b11, 0b000, 0b1100, 0b0001, 0b000>;
+def : ROSysReg<"CNTPCT_EL0", 0b11, 0b011, 0b1110, 0b0000, 0b001>;
+def : ROSysReg<"CNTVCT_EL0", 0b11, 0b011, 0b1110, 0b0000, 0b010>;
+def : ROSysReg<"ID_MMFR4_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b110>;
+def : ROSysReg<"ID_MMFR5_EL1", 0b11, 0b000, 0b0000, 0b0011, 0b110>;
// Trace registers
// Op0 Op1 CRn CRm Op2
-def : ROSysReg<"TRCSTATR", 0b0, 0b001, 0b0000, 0b0011, 0b000>;
-def : ROSysReg<"TRCIDR8", 0b0, 0b001, 0b0000, 0b0000, 0b110>;
-def : ROSysReg<"TRCIDR9", 0b0, 0b001, 0b0000, 0b0001, 0b110>;
-def : ROSysReg<"TRCIDR10", 0b0, 0b001, 0b0000, 0b0010, 0b110>;
-def : ROSysReg<"TRCIDR11", 0b0, 0b001, 0b0000, 0b0011, 0b110>;
-def : ROSysReg<"TRCIDR12", 0b0, 0b001, 0b0000, 0b0100, 0b110>;
-def : ROSysReg<"TRCIDR13", 0b0, 0b001, 0b0000, 0b0101, 0b110>;
-def : ROSysReg<"TRCIDR0", 0b0, 0b001, 0b0000, 0b1000, 0b111>;
-def : ROSysReg<"TRCIDR1", 0b0, 0b001, 0b0000, 0b1001, 0b111>;
-def : ROSysReg<"TRCIDR2", 0b0, 0b001, 0b0000, 0b1010, 0b111>;
-def : ROSysReg<"TRCIDR3", 0b0, 0b001, 0b0000, 0b1011, 0b111>;
-def : ROSysReg<"TRCIDR4", 0b0, 0b001, 0b0000, 0b1100, 0b111>;
-def : ROSysReg<"TRCIDR5", 0b0, 0b001, 0b0000, 0b1101, 0b111>;
-def : ROSysReg<"TRCIDR6", 0b0, 0b001, 0b0000, 0b1110, 0b111>;
-def : ROSysReg<"TRCIDR7", 0b0, 0b001, 0b0000, 0b1111, 0b111>;
-def : ROSysReg<"TRCOSLSR", 0b0, 0b001, 0b0001, 0b0001, 0b100>;
-def : ROSysReg<"TRCPDSR", 0b0, 0b001, 0b0001, 0b0101, 0b100>;
-def : ROSysReg<"TRCDEVAFF0", 0b0, 0b001, 0b0111, 0b1010, 0b110>;
-def : ROSysReg<"TRCDEVAFF1", 0b0, 0b001, 0b0111, 0b1011, 0b110>;
-def : ROSysReg<"TRCLSR", 0b0, 0b001, 0b0111, 0b1101, 0b110>;
-def : ROSysReg<"TRCAUTHSTATUS", 0b0, 0b001, 0b0111, 0b1110, 0b110>;
-def : ROSysReg<"TRCDEVARCH", 0b0, 0b001, 0b0111, 0b1111, 0b110>;
-def : ROSysReg<"TRCDEVID", 0b0, 0b001, 0b0111, 0b0010, 0b111>;
-def : ROSysReg<"TRCDEVTYPE", 0b0, 0b001, 0b0111, 0b0011, 0b111>;
-def : ROSysReg<"TRCPIDR4", 0b0, 0b001, 0b0111, 0b0100, 0b111>;
-def : ROSysReg<"TRCPIDR5", 0b0, 0b001, 0b0111, 0b0101, 0b111>;
-def : ROSysReg<"TRCPIDR6", 0b0, 0b001, 0b0111, 0b0110, 0b111>;
-def : ROSysReg<"TRCPIDR7", 0b0, 0b001, 0b01...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/201137
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