[Lldb-commits] [PATCH] D154927: [lldb][AArch64] Add SME's streaming vector control register

[David Spickett via Phabricator via lldb-commits]

DavidSpickett created this revision.
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Software can tell if it is in streaming SVE mode by checking
the Streaming Vector Control Register (SVCR).

"E3.1.9 SVCR, Streaming Vector Control Register" in
"Arm® Architecture Reference Manual Supplement, The Scalable Matrix
Extension (SME), for Armv9-A"

This is especially useful for debug because the names of the
SVE registers are the same betweeen non-streaming and streaming mode.

The Linux Kernel chose to not put this register behind ptrace,
and it can be read from EL0. However, this would mean running code
in process to read it. That can be done but we already know all
the information just from ptrace.

So this is a pseudo register that matches the architectural
content, and it is read only for now until all bits are implemented.
The name is just "svcr", which aligns with GDB's proposed naming.

It is in a new dynamic register set named for the SME exention.
There will also be a streaming vector length pseduo register here
in future.

The register contains two bits:
0 : Whether streaming SVE mode is enabled.
1 : Whether the array storage is enabled.

This patch only adds bit 0, bit 1 will be added in a later patch
after the array storage (ZA) is supported. The register is read
only and may be made writeable in a later patch.

An existing test has been updated to check the expected SVCR value.
There's not much point adding a dedicated test given that the content
is just whatever m_sme_state is. If lldb gets it wrong, svcr will be
wrong too.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D154927

Files:
  lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
  lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
  lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
  lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h
  lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/TestSVERegisters.py

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