[Lldb-commits] [PATCH] D124760: [lldb] Fix ppc64 detection in lldb
serge via Phabricator via lldb-commits
lldb-commits at lists.llvm.org
Tue May 3 02:40:19 PDT 2022
serge-sans-paille updated this revision to Diff 426620.
serge-sans-paille added a comment.
Fix nits
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D124760/new/
https://reviews.llvm.org/D124760
Files:
lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
lldb/source/Utility/ArchSpec.cpp
lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py
lldb/test/API/functionalities/postmortem/elf-core/linux-ppc64.core
lldb/test/API/functionalities/postmortem/elf-core/linux-ppc64.out
Index: lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py
===================================================================
--- lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py
+++ lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py
@@ -24,12 +24,14 @@
_i386_pid = 32306
_x86_64_pid = 32259
_s390x_pid = 1045
+ _ppc64_pid = 28146
_ppc64le_pid = 28147
_aarch64_regions = 4
_i386_regions = 4
_x86_64_regions = 5
_s390x_regions = 2
+ _ppc64_regions = 2
_ppc64le_regions = 2
@skipIfLLVMTargetMissing("AArch64")
@@ -49,6 +51,12 @@
self.do_test("linux-ppc64le", self._ppc64le_pid, self._ppc64le_regions,
"linux-ppc64le.ou")
+ @skipIfLLVMTargetMissing("PowerPC")
+ def test_ppc64(self):
+ """Test that lldb can read the process information from an ppc64 linux core file."""
+ self.do_test("linux-ppc64", self._ppc64_pid, self._ppc64_regions,
+ "linux-ppc64.ou")
+
@skipIfLLVMTargetMissing("X86")
def test_x86_64(self):
"""Test that lldb can read the process information from an x86_64 linux core file."""
Index: lldb/source/Utility/ArchSpec.cpp
===================================================================
--- lldb/source/Utility/ArchSpec.cpp
+++ lldb/source/Utility/ArchSpec.cpp
@@ -358,10 +358,10 @@
0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel MCU // FIXME: is this correct?
{ArchSpec::eCore_ppc_generic, llvm::ELF::EM_PPC, LLDB_INVALID_CPUTYPE,
0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC
- {ArchSpec::eCore_ppc64le_generic, llvm::ELF::EM_PPC64, LLDB_INVALID_CPUTYPE,
- 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64le
- {ArchSpec::eCore_ppc64_generic, llvm::ELF::EM_PPC64, LLDB_INVALID_CPUTYPE,
- 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64
+ {ArchSpec::eCore_ppc64le_generic, llvm::ELF::EM_PPC64,
+ ArchSpec::eCore_ppc64le_generic, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64le
+ {ArchSpec::eCore_ppc64_generic, llvm::ELF::EM_PPC64,
+ ArchSpec::eCore_ppc64_generic, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64
{ArchSpec::eCore_arm_generic, llvm::ELF::EM_ARM, LLDB_INVALID_CPUTYPE,
0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM
{ArchSpec::eCore_arm_aarch64, llvm::ELF::EM_AARCH64, LLDB_INVALID_CPUTYPE,
@@ -400,8 +400,8 @@
LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // HEXAGON
{ArchSpec::eCore_arc, llvm::ELF::EM_ARC_COMPACT2, LLDB_INVALID_CPUTYPE,
0xFFFFFFFFu, 0xFFFFFFFFu}, // ARC
- {ArchSpec::eCore_avr, llvm::ELF::EM_AVR, LLDB_INVALID_CPUTYPE,
- 0xFFFFFFFFu, 0xFFFFFFFFu}, // AVR
+ {ArchSpec::eCore_avr, llvm::ELF::EM_AVR, LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu,
+ 0xFFFFFFFFu}, // AVR
{ArchSpec::eCore_riscv32, llvm::ELF::EM_RISCV,
ArchSpec::eRISCVSubType_riscv32, 0xFFFFFFFFu, 0xFFFFFFFFu}, // riscv32
{ArchSpec::eCore_riscv64, llvm::ELF::EM_RISCV,
Index: lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
===================================================================
--- lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
+++ lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
@@ -310,9 +310,19 @@
}
}
+static uint32_t ppc64VariantFromElfFlags(const elf::ELFHeader &header) {
+ uint32_t endian = header.e_ident[EI_DATA];
+ if (endian == ELFDATA2LSB)
+ return ArchSpec::eCore_ppc64le_generic;
+ else
+ return ArchSpec::eCore_ppc64_generic;
+}
+
static uint32_t subTypeFromElfHeader(const elf::ELFHeader &header) {
if (header.e_machine == llvm::ELF::EM_MIPS)
return mipsVariantFromElfFlags(header);
+ else if (header.e_machine == llvm::ELF::EM_PPC64)
+ return ppc64VariantFromElfFlags(header);
else if (header.e_machine == llvm::ELF::EM_RISCV)
return riscvVariantFromElfFlags(header);
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