[Lldb-commits] [PATCH] D79699: Add ptrace register access for AArch64 SVE registers

[Pavel Labath via Phabricator via lldb-commits]

labath added a comment.

In D79699#2215216 <https://reviews.llvm.org/D79699#2215216>, @omjavaid wrote:

> @labath Any further action needed on this change? I have updated test main.c for doing asm write to SVE regs and then reading them back during testing. Also i have removed NativeProcessLinux_arm64 dependence on LinuxPTraceDefines_arm64sve.h.  We are using sys root's ptrace.h as SVE marcros are back ported in most versions of ptrace.h.

Almost. I have two more questions/requests inline.



================
Comment at: lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/TestSVERegisters.py:100-106
+        has_sve = False
+        for registerSet in currentFrame.GetRegisters():
+            if 'Scalable Vector Extension Registers' in registerSet.GetName():
+                has_sve = True
+
+        if not has_sve:
+            self.skipTest('SVE registers must be supported.')
----------------
Are you sure this will work if the system does not support SVE? I would expect the test application to die from SIGILL (or something) long before we reach this part.

Even if it does work, it will mean that the test will be skipped (instead of failing) if the lldb-server stops reporting the sve registers (or even if it just slightly changes the register set name). That's why I was originally suggesting to check for SVE support from within the inferior process.

Is there a simple way to do that? I'm assuming there must be, otherwise the application could not detect whether it can use sve...


================
Comment at: lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/TestSVERegisters.py:134
+        for i in range(16):
+            self.expect("register read " + 'p%i' % (i), substrs=[p_regs_value])
+
----------------
So, the program sets all p registers to the same value (0xffff..) right? Would it be possible to introduce some variance there (like you did for the z registers), to ensure that the registers are actually read from the right place?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D79699/new/

https://reviews.llvm.org/D79699