[clang] [llvm] [RISCV][MC] Add experimental Smeihv, Sseihv, Smip, and Ssip support (PR #215095)

[Zeyi Xu via cfe-commits]

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@@ -272,11 +272,15 @@
 // CHECK-NEXT:     zvzip                0.1       'Zvzip' (Vector Reordering Structured Data)
 // CHECK-NEXT:     smcsps               0.19      'Smcsps' (Conditional Stack Pointer Swap at Machine Level)
 // CHECK-NEXT:     smehv                0.19      'Smehv' (Synchronous Exception Hardware Vectoring at Machine Level)
+// CHECK-NEXT:     smeihv               0.19      'Smeihv' (External Interrupt Hardware Vectoring at Machine Level)
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zeyi2 wrote:

The descriptions come from the table [here](https://github.com/riscv/riscv-fast-interrupt/blob/6164eca8c8c9138e519ea3b8510655b2b5bb76d0/src/aclic.adoc?plain=1#L188-L205)

https://github.com/llvm/llvm-project/pull/215095