[clang] [llvm] [RISCV][MC] Add experimental Smeihv, Sseihv, Smip, and Ssip support (PR #215095)

[Zeyi Xu via cfe-commits]

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@@ -1115,6 +1115,28 @@ def FeatureStdExtSsehv
                                  "Synchronous Exception Hardware Vectoring at Supervisor Level",
                                  [FeatureStdExtSsijt]>;
 
+def FeatureStdExtSmeihv
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zeyi2 wrote:

[`Smeihv` and `Sseihv`](https://github.com/riscv/riscv-fast-interrupt/blob/6164eca8c8c9138e519ea3b8510655b2b5bb76d0/src/aclic.adoc?plain=1#L686-L765) only add a new `xtvec.MODE=10` behavior and define no new instructions or CSRs, so IMO MC only needs to register them as experimental features.

https://github.com/llvm/llvm-project/pull/215095