[clang] [llvm] [X86] AVX10_V2_AUX Implementation (PR #206888)
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Tue Jun 30 23:16:51 PDT 2026
https://github.com/ganeshgit updated https://github.com/llvm/llvm-project/pull/206888
>From 09d35e0917a8efa42fc626606a2b2e262b9f97f5 Mon Sep 17 00:00:00 2001
From: Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian at amd.com>
Date: Wed, 1 Jul 2026 10:01:13 +0530
Subject: [PATCH] AVX10_V2_AUX Implementation
- AVX10_V2_AUX extends AVX10.2 with FP8/FP4/FP6 format conversions optimized
for AI/ML inference workloads, enabling efficient low-precision arithmetic
- Narrowing conversions from single-precision to FP8: VCVTPS2BF8, VCVTPS2HF8,
VCVTPS2BF8S, VCVTPS2HF8S with optional saturation, biasing
(VCVTBIASPS2BF8/HF8), and round-to-odd (VCVTROPS2HF8) variants
- Expanding conversions from FP8 to single-precision: VCVTBF82PS, VCVTHF82PS
that widen 8-bit FP formats with masking support
- FP4/FP6 conversions: VCVTBF82BF4S, VCVTHF82BF4S for truncating,
VCVTBF82BF6S, VCVTHF82HF6S for same-size, and expanding VCVTBF42HF8,
VCVTBF62BF8, VCVTHF62HF8
- Support includes instruction definitions, intrinsics, and Clang headers
- Tests covering AT&T and Intel syntax assembly for both 32-bit and 64-bit
modes, plus disassembler tests verifying round-trip encoding and decoding
---
clang/include/clang/Basic/BuiltinsX86.td | 247 +++
clang/lib/Basic/Targets/X86.cpp | 6 +
clang/lib/Basic/Targets/X86.h | 1 +
clang/lib/Headers/CMakeLists.txt | 1 +
clang/lib/Headers/avx10_2_v2auxintrin.h | 1067 +++++++++
clang/lib/Headers/cpuid.h | 3 +
clang/lib/Headers/immintrin.h | 4 +
.../test/CodeGen/X86/avx10_2_v2aux-builtins.c | 1056 +++++++++
clang/test/CodeGen/attr-target-x86.c | 4 +-
llvm/include/llvm/IR/IntrinsicsX86.td | 197 ++
.../llvm/TargetParser/X86TargetParser.def | 1 +
llvm/lib/Target/X86/X86.td | 3 +
llvm/lib/Target/X86/X86InstrAVX10_V2_AUX.td | 588 +++++
llvm/lib/Target/X86/X86InstrFragmentsSIMD.td | 57 +
llvm/lib/Target/X86/X86InstrInfo.td | 3 +
llvm/lib/Target/X86/X86InstrPredicates.td | 1 +
llvm/lib/Target/X86/X86IntrinsicsInfo.h | 72 +
llvm/lib/TargetParser/X86TargetParser.cpp | 1 +
.../CodeGen/X86/avx10_2_v2aux-intrinsics.ll | 1931 +++++++++++++++++
.../MC/Disassembler/X86/avx10_v2_aux-32.txt | 460 ++++
.../MC/Disassembler/X86/avx10_v2_aux-64.txt | 460 ++++
llvm/test/MC/X86/avx10_v2_aux-att-32.s | 463 ++++
llvm/test/MC/X86/avx10_v2_aux-att-64.s | 687 ++++++
llvm/test/MC/X86/avx10_v2_aux-intel-32.s | 331 +++
llvm/test/MC/X86/avx10_v2_aux-intel-64.s | 687 ++++++
llvm/test/TableGen/x86-fold-tables.inc | 224 ++
26 files changed, 8553 insertions(+), 2 deletions(-)
create mode 100644 clang/lib/Headers/avx10_2_v2auxintrin.h
create mode 100644 clang/test/CodeGen/X86/avx10_2_v2aux-builtins.c
create mode 100644 llvm/lib/Target/X86/X86InstrAVX10_V2_AUX.td
create mode 100644 llvm/test/CodeGen/X86/avx10_2_v2aux-intrinsics.ll
create mode 100644 llvm/test/MC/Disassembler/X86/avx10_v2_aux-32.txt
create mode 100644 llvm/test/MC/Disassembler/X86/avx10_v2_aux-64.txt
create mode 100644 llvm/test/MC/X86/avx10_v2_aux-att-32.s
create mode 100644 llvm/test/MC/X86/avx10_v2_aux-att-64.s
create mode 100644 llvm/test/MC/X86/avx10_v2_aux-intel-32.s
create mode 100644 llvm/test/MC/X86/avx10_v2_aux-intel-64.s
diff --git a/clang/include/clang/Basic/BuiltinsX86.td b/clang/include/clang/Basic/BuiltinsX86.td
index b0f95d98b8471..82fd8d80cc82d 100644
--- a/clang/include/clang/Basic/BuiltinsX86.td
+++ b/clang/include/clang/Basic/BuiltinsX86.td
@@ -5045,3 +5045,250 @@ let Features = "avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<256>
let Features = "avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in {
def vgetmantbf16512_mask : X86Builtin<"_Vector<32, __bf16>(_Vector<32, __bf16>, _Constant int, _Vector<32, __bf16>, unsigned int)">;
}
+
+// AVX10 V2 AUX - Convert instructions
+
+// Group A: PS(f32) -> i8 truncating conversions (quarter-size: output always v16i8)
+
+// VCVTPS2BF8
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<128>] in {
+ def vcvtps2bf8_128_mask : X86Builtin<"_Vector<16, char>(_Vector<4, float>, _Vector<16, char>, unsigned char)">;
+}
+
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<256>] in {
+ def vcvtps2bf8_256_mask : X86Builtin<"_Vector<16, char>(_Vector<8, float>, _Vector<16, char>, unsigned char)">;
+}
+
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<512>] in {
+ def vcvtps2bf8_512_mask : X86Builtin<"_Vector<16, char>(_Vector<16, float>, _Vector<16, char>, unsigned short)">;
+}
+
+// VCVTPS2BF8S
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<128>] in {
+ def vcvtps2bf8s_128_mask : X86Builtin<"_Vector<16, char>(_Vector<4, float>, _Vector<16, char>, unsigned char)">;
+}
+
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<256>] in {
+ def vcvtps2bf8s_256_mask : X86Builtin<"_Vector<16, char>(_Vector<8, float>, _Vector<16, char>, unsigned char)">;
+}
+
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<512>] in {
+ def vcvtps2bf8s_512_mask : X86Builtin<"_Vector<16, char>(_Vector<16, float>, _Vector<16, char>, unsigned short)">;
+}
+
+// VCVTPS2HF8
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<128>] in {
+ def vcvtps2hf8_128_mask : X86Builtin<"_Vector<16, char>(_Vector<4, float>, _Vector<16, char>, unsigned char)">;
+}
+
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<256>] in {
+ def vcvtps2hf8_256_mask : X86Builtin<"_Vector<16, char>(_Vector<8, float>, _Vector<16, char>, unsigned char)">;
+}
+
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<512>] in {
+ def vcvtps2hf8_512_mask : X86Builtin<"_Vector<16, char>(_Vector<16, float>, _Vector<16, char>, unsigned short)">;
+}
+
+// VCVTPS2HF8S
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<128>] in {
+ def vcvtps2hf8s_128_mask : X86Builtin<"_Vector<16, char>(_Vector<4, float>, _Vector<16, char>, unsigned char)">;
+}
+
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<256>] in {
+ def vcvtps2hf8s_256_mask : X86Builtin<"_Vector<16, char>(_Vector<8, float>, _Vector<16, char>, unsigned char)">;
+}
+
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<512>] in {
+ def vcvtps2hf8s_512_mask : X86Builtin<"_Vector<16, char>(_Vector<16, float>, _Vector<16, char>, unsigned short)">;
+}
+
+// VCVTROPS2HF8
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<128>] in {
+ def vcvtrops2hf8_128_mask : X86Builtin<"_Vector<16, char>(_Vector<4, float>, _Vector<16, char>, unsigned char)">;
+}
+
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<256>] in {
+ def vcvtrops2hf8_256_mask : X86Builtin<"_Vector<16, char>(_Vector<8, float>, _Vector<16, char>, unsigned char)">;
+}
+
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<512>] in {
+ def vcvtrops2hf8_512_mask : X86Builtin<"_Vector<16, char>(_Vector<16, float>, _Vector<16, char>, unsigned short)">;
+}
+
+// VCVTROPS2HF8S
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<128>] in {
+ def vcvtrops2hf8s_128_mask : X86Builtin<"_Vector<16, char>(_Vector<4, float>, _Vector<16, char>, unsigned char)">;
+}
+
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<256>] in {
+ def vcvtrops2hf8s_256_mask : X86Builtin<"_Vector<16, char>(_Vector<8, float>, _Vector<16, char>, unsigned char)">;
+}
+
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<512>] in {
+ def vcvtrops2hf8s_512_mask : X86Builtin<"_Vector<16, char>(_Vector<16, float>, _Vector<16, char>, unsigned short)">;
+}
+
+// Group B: Bias PS -> i8 conversions (3-operand: bias + f32 source -> i8 dest)
+
+// VCVTBIASPS2BF8
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<128>] in {
+ def vcvtbiasps2bf8_128_mask : X86Builtin<"_Vector<16, char>(_Vector<16, char>, _Vector<4, float>, _Vector<16, char>, unsigned char)">;
+}
+
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<256>] in {
+ def vcvtbiasps2bf8_256_mask : X86Builtin<"_Vector<16, char>(_Vector<32, char>, _Vector<8, float>, _Vector<16, char>, unsigned char)">;
+}
+
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<512>] in {
+ def vcvtbiasps2bf8_512_mask : X86Builtin<"_Vector<16, char>(_Vector<64, char>, _Vector<16, float>, _Vector<16, char>, unsigned short)">;
+}
+
+// VCVTBIASPS2BF8S
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<128>] in {
+ def vcvtbiasps2bf8s_128_mask : X86Builtin<"_Vector<16, char>(_Vector<16, char>, _Vector<4, float>, _Vector<16, char>, unsigned char)">;
+}
+
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<256>] in {
+ def vcvtbiasps2bf8s_256_mask : X86Builtin<"_Vector<16, char>(_Vector<32, char>, _Vector<8, float>, _Vector<16, char>, unsigned char)">;
+}
+
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<512>] in {
+ def vcvtbiasps2bf8s_512_mask : X86Builtin<"_Vector<16, char>(_Vector<64, char>, _Vector<16, float>, _Vector<16, char>, unsigned short)">;
+}
+
+// VCVTBIASPS2HF8
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<128>] in {
+ def vcvtbiasps2hf8_128_mask : X86Builtin<"_Vector<16, char>(_Vector<16, char>, _Vector<4, float>, _Vector<16, char>, unsigned char)">;
+}
+
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<256>] in {
+ def vcvtbiasps2hf8_256_mask : X86Builtin<"_Vector<16, char>(_Vector<32, char>, _Vector<8, float>, _Vector<16, char>, unsigned char)">;
+}
+
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<512>] in {
+ def vcvtbiasps2hf8_512_mask : X86Builtin<"_Vector<16, char>(_Vector<64, char>, _Vector<16, float>, _Vector<16, char>, unsigned short)">;
+}
+
+// VCVTBIASPS2HF8S
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<128>] in {
+ def vcvtbiasps2hf8s_128_mask : X86Builtin<"_Vector<16, char>(_Vector<16, char>, _Vector<4, float>, _Vector<16, char>, unsigned char)">;
+}
+
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<256>] in {
+ def vcvtbiasps2hf8s_256_mask : X86Builtin<"_Vector<16, char>(_Vector<32, char>, _Vector<8, float>, _Vector<16, char>, unsigned char)">;
+}
+
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<512>] in {
+ def vcvtbiasps2hf8s_512_mask : X86Builtin<"_Vector<16, char>(_Vector<64, char>, _Vector<16, float>, _Vector<16, char>, unsigned short)">;
+}
+
+// Group C: 8bit -> PS expanding conversions
+
+// VCVTBF82PS
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<128>] in {
+ def vcvtbf8_2ps128_mask : X86Builtin<"_Vector<4, float>(_Vector<16, char>, _Vector<4, float>, unsigned char)">;
+}
+
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<256>] in {
+ def vcvtbf8_2ps256_mask : X86Builtin<"_Vector<8, float>(_Vector<16, char>, _Vector<8, float>, unsigned char)">;
+}
+
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<512>] in {
+ def vcvtbf8_2ps512_mask : X86Builtin<"_Vector<16, float>(_Vector<16, char>, _Vector<16, float>, unsigned short)">;
+}
+
+// VCVTHF82PS
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<128>] in {
+ def vcvthf8_2ps128_mask : X86Builtin<"_Vector<4, float>(_Vector<16, char>, _Vector<4, float>, unsigned char)">;
+}
+
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<256>] in {
+ def vcvthf8_2ps256_mask : X86Builtin<"_Vector<8, float>(_Vector<16, char>, _Vector<8, float>, unsigned char)">;
+}
+
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<512>] in {
+ def vcvthf8_2ps512_mask : X86Builtin<"_Vector<16, float>(_Vector<16, char>, _Vector<16, float>, unsigned short)">;
+}
+
+// Group E: Same-size reg-only conversions (no masking)
+
+// VCVTBF82BF6S
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<128>] in {
+ def vcvtbf82bf6s128 : X86Builtin<"_Vector<16, char>(_Vector<16, char>)">;
+}
+
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<256>] in {
+ def vcvtbf82bf6s256 : X86Builtin<"_Vector<32, char>(_Vector<32, char>)">;
+}
+
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<512>] in {
+ def vcvtbf82bf6s512 : X86Builtin<"_Vector<64, char>(_Vector<64, char>)">;
+}
+
+// VCVTHF82HF6S
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<128>] in {
+ def vcvthf82hf6s128 : X86Builtin<"_Vector<16, char>(_Vector<16, char>)">;
+}
+
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<256>] in {
+ def vcvthf82hf6s256 : X86Builtin<"_Vector<32, char>(_Vector<32, char>)">;
+}
+
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<512>] in {
+ def vcvthf82hf6s512 : X86Builtin<"_Vector<64, char>(_Vector<64, char>)">;
+}
+
+// Group F: Expanding/same-size conversions (no masking in intrinsic; use selectb for masking)
+
+// VCVTBF42HF8
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<128>] in {
+ def vcvtbf42hf8128 : X86Builtin<"_Vector<16, char>(_Vector<16, char>)">;
+}
+
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<256>] in {
+ def vcvtbf42hf8256 : X86Builtin<"_Vector<32, char>(_Vector<16, char>)">;
+}
+
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<512>] in {
+ def vcvtbf42hf8512 : X86Builtin<"_Vector<64, char>(_Vector<32, char>)">;
+}
+
+// VCVTBF62HF8
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<128>] in {
+ def vcvtbf62hf8128 : X86Builtin<"_Vector<16, char>(_Vector<16, char>)">;
+}
+
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<256>] in {
+ def vcvtbf62hf8256 : X86Builtin<"_Vector<32, char>(_Vector<32, char>)">;
+}
+
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<512>] in {
+ def vcvtbf62hf8512 : X86Builtin<"_Vector<64, char>(_Vector<64, char>)">;
+}
+
+// VCVTHF62HF8
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<128>] in {
+ def vcvthf62hf8128 : X86Builtin<"_Vector<16, char>(_Vector<16, char>)">;
+}
+
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<256>] in {
+ def vcvthf62hf8256 : X86Builtin<"_Vector<32, char>(_Vector<32, char>)">;
+}
+
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<512>] in {
+ def vcvthf62hf8512 : X86Builtin<"_Vector<64, char>(_Vector<64, char>)">;
+}
+
+// Group H: VUNPACKB - Byte unpack with immediate (no masking in intrinsic)
+
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<128>] in {
+ def vunpackb128 : X86Builtin<"_Vector<16, char>(_Vector<16, char>, _Constant unsigned char)">;
+}
+
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<256>] in {
+ def vunpackb256 : X86Builtin<"_Vector<32, char>(_Vector<32, char>, _Constant unsigned char)">;
+}
+
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<512>] in {
+ def vunpackb512 : X86Builtin<"_Vector<64, char>(_Vector<64, char>, _Constant unsigned char)">;
+}
diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index 2943604f8c8ff..9482e179dee5c 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -281,6 +281,8 @@ bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
} else if (Feature == "+avx10.2") {
HasAVX10_2 = true;
HasFullBFloat16 = true;
+ } else if (Feature == "+avx10-v2-aux") {
+ HasAVX10_V2_AUX = true;
} else if (Feature == "+avx512cd") {
HasAVX512CD = true;
} else if (Feature == "+avx512vpopcntdq") {
@@ -836,6 +838,8 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
Builder.defineMacro("__AVX10_2__");
Builder.defineMacro("__AVX10_2_512__");
}
+ if (HasAVX10_V2_AUX)
+ Builder.defineMacro("__AVX10_V2_AUX__");
if (HasAVX512CD)
Builder.defineMacro("__AVX512CD__");
if (HasAVX512VPOPCNTDQ)
@@ -1087,6 +1091,7 @@ bool X86TargetInfo::isValidFeatureName(StringRef Name) const {
.Case("avx", true)
.Case("avx10.1", true)
.Case("avx10.2", true)
+ .Case("avx10-v2-aux", true)
.Case("avx2", true)
.Case("avx512f", true)
.Case("avx512cd", true)
@@ -1208,6 +1213,7 @@ bool X86TargetInfo::hasFeature(StringRef Feature) const {
.Case("avx", SSELevel >= AVX)
.Case("avx10.1", HasAVX10_1)
.Case("avx10.2", HasAVX10_2)
+ .Case("avx10-v2-aux", HasAVX10_V2_AUX)
.Case("avx2", SSELevel >= AVX2)
.Case("avx512f", SSELevel >= AVX512F)
.Case("avx512cd", HasAVX512CD)
diff --git a/clang/lib/Basic/Targets/X86.h b/clang/lib/Basic/Targets/X86.h
index f9c39b31f5e08..02f7e8c5807ca 100644
--- a/clang/lib/Basic/Targets/X86.h
+++ b/clang/lib/Basic/Targets/X86.h
@@ -98,6 +98,7 @@ class LLVM_LIBRARY_VISIBILITY X86TargetInfo : public TargetInfo {
bool HasF16C = false;
bool HasAVX10_1 = false;
bool HasAVX10_2 = false;
+ bool HasAVX10_V2_AUX = false;
bool HasAVX512CD = false;
bool HasAVX512VPOPCNTDQ = false;
bool HasAVX512VNNI = false;
diff --git a/clang/lib/Headers/CMakeLists.txt b/clang/lib/Headers/CMakeLists.txt
index 439f2725168ba..b4891961a4598 100644
--- a/clang/lib/Headers/CMakeLists.txt
+++ b/clang/lib/Headers/CMakeLists.txt
@@ -183,6 +183,7 @@ set(x86_files
avx10_2_512niintrin.h
avx10_2_512satcvtdsintrin.h
avx10_2_512satcvtintrin.h
+ avx10_2_v2auxintrin.h
avx10_2bf16intrin.h
avx10_2convertintrin.h
avx10_2copyintrin.h
diff --git a/clang/lib/Headers/avx10_2_v2auxintrin.h b/clang/lib/Headers/avx10_2_v2auxintrin.h
new file mode 100644
index 0000000000000..5e54085c104c5
--- /dev/null
+++ b/clang/lib/Headers/avx10_2_v2auxintrin.h
@@ -0,0 +1,1067 @@
+/*===------------ avx10_2_v2auxintrin.h - AVX10_2_V2AUX -------------------===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ *
+ *===-----------------------------------------------------------------------===
+ */
+#ifndef __IMMINTRIN_H
+#error \
+ "Never use <avx10_2_v2auxintrin.h> directly; include <immintrin.h> instead."
+#endif // __IMMINTRIN_H
+
+#ifdef __SSE2__
+
+#ifndef __AVX10_2_V2AUXINTRIN_H
+#define __AVX10_2_V2AUXINTRIN_H
+
+/* Define the default attributes for the functions in this file. */
+#define __DEFAULT_FN_ATTRS128 \
+ __attribute__((__always_inline__, __nodebug__, __target__("avx10-v2-aux"), \
+ __min_vector_width__(128)))
+#define __DEFAULT_FN_ATTRS256 \
+ __attribute__((__always_inline__, __nodebug__, __target__("avx10-v2-aux"), \
+ __min_vector_width__(256)))
+#define __DEFAULT_FN_ATTRS512 \
+ __attribute__((__always_inline__, __nodebug__, __target__("avx10-v2-aux"), \
+ __min_vector_width__(512)))
+
+// clang-format off
+
+//===----------------------------------------------------------------------===//
+// Group A: VCVTPS2BF8 / VCVTPS2BF8S / VCVTPS2HF8 / VCVTPS2HF8S /
+// VCVTROPS2HF8 / VCVTROPS2HF8S
+// Convert packed single-precision to FP8. Output is always __m128i.
+//===----------------------------------------------------------------------===//
+
+// VCVTPS2BF8 - 128-bit
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS128
+_mm_cvtps_bf8(__m128 __A) {
+ return (__m128i)__builtin_ia32_vcvtps2bf8_128_mask(
+ (__v4sf)__A, (__v16qi)_mm_undefined_si128(), (__mmask8)-1);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS128
+_mm_mask_cvtps_bf8(__m128i __W, __mmask8 __U, __m128 __A) {
+ return (__m128i)__builtin_ia32_vcvtps2bf8_128_mask(
+ (__v4sf)__A, (__v16qi)(__m128i)__W, (__mmask8)__U);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS128
+_mm_maskz_cvtps_bf8(__mmask8 __U, __m128 __A) {
+ return (__m128i)__builtin_ia32_vcvtps2bf8_128_mask(
+ (__v4sf)__A, (__v16qi)(__m128i)_mm_setzero_si128(), (__mmask8)__U);
+}
+
+// VCVTPS2BF8 - 256-bit
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS256
+_mm256_cvtps_bf8(__m256 __A) {
+ return (__m128i)__builtin_ia32_vcvtps2bf8_256_mask(
+ (__v8sf)__A, (__v16qi)_mm_undefined_si128(), (__mmask8)-1);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS256
+_mm256_mask_cvtps_bf8(__m128i __W, __mmask8 __U, __m256 __A) {
+ return (__m128i)__builtin_ia32_vcvtps2bf8_256_mask(
+ (__v8sf)__A, (__v16qi)(__m128i)__W, (__mmask8)__U);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS256
+_mm256_maskz_cvtps_bf8(__mmask8 __U, __m256 __A) {
+ return (__m128i)__builtin_ia32_vcvtps2bf8_256_mask(
+ (__v8sf)__A, (__v16qi)(__m128i)_mm_setzero_si128(), (__mmask8)__U);
+}
+
+// VCVTPS2BF8 - 512-bit
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS512
+_mm512_cvtps_bf8(__m512 __A) {
+ return (__m128i)__builtin_ia32_vcvtps2bf8_512_mask(
+ (__v16sf)__A, (__v16qi)_mm_undefined_si128(), (__mmask16)-1);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS512
+_mm512_mask_cvtps_bf8(__m128i __W, __mmask16 __U, __m512 __A) {
+ return (__m128i)__builtin_ia32_vcvtps2bf8_512_mask(
+ (__v16sf)__A, (__v16qi)(__m128i)__W, (__mmask16)__U);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS512
+_mm512_maskz_cvtps_bf8(__mmask16 __U, __m512 __A) {
+ return (__m128i)__builtin_ia32_vcvtps2bf8_512_mask(
+ (__v16sf)__A, (__v16qi)(__m128i)_mm_setzero_si128(), (__mmask16)__U);
+}
+
+// VCVTPS2BF8S - 128-bit
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS128
+_mm_cvts_ps_bf8(__m128 __A) {
+ return (__m128i)__builtin_ia32_vcvtps2bf8s_128_mask(
+ (__v4sf)__A, (__v16qi)_mm_undefined_si128(), (__mmask8)-1);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS128
+_mm_mask_cvts_ps_bf8(__m128i __W, __mmask8 __U, __m128 __A) {
+ return (__m128i)__builtin_ia32_vcvtps2bf8s_128_mask(
+ (__v4sf)__A, (__v16qi)(__m128i)__W, (__mmask8)__U);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS128
+_mm_maskz_cvts_ps_bf8(__mmask8 __U, __m128 __A) {
+ return (__m128i)__builtin_ia32_vcvtps2bf8s_128_mask(
+ (__v4sf)__A, (__v16qi)(__m128i)_mm_setzero_si128(), (__mmask8)__U);
+}
+
+// VCVTPS2BF8S - 256-bit
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS256
+_mm256_cvts_ps_bf8(__m256 __A) {
+ return (__m128i)__builtin_ia32_vcvtps2bf8s_256_mask(
+ (__v8sf)__A, (__v16qi)_mm_undefined_si128(), (__mmask8)-1);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS256
+_mm256_mask_cvts_ps_bf8(__m128i __W, __mmask8 __U, __m256 __A) {
+ return (__m128i)__builtin_ia32_vcvtps2bf8s_256_mask(
+ (__v8sf)__A, (__v16qi)(__m128i)__W, (__mmask8)__U);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS256
+_mm256_maskz_cvts_ps_bf8(__mmask8 __U, __m256 __A) {
+ return (__m128i)__builtin_ia32_vcvtps2bf8s_256_mask(
+ (__v8sf)__A, (__v16qi)(__m128i)_mm_setzero_si128(), (__mmask8)__U);
+}
+
+// VCVTPS2BF8S - 512-bit
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS512
+_mm512_cvts_ps_bf8(__m512 __A) {
+ return (__m128i)__builtin_ia32_vcvtps2bf8s_512_mask(
+ (__v16sf)__A, (__v16qi)_mm_undefined_si128(), (__mmask16)-1);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS512
+_mm512_mask_cvts_ps_bf8(__m128i __W, __mmask16 __U, __m512 __A) {
+ return (__m128i)__builtin_ia32_vcvtps2bf8s_512_mask(
+ (__v16sf)__A, (__v16qi)(__m128i)__W, (__mmask16)__U);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS512
+_mm512_maskz_cvts_ps_bf8(__mmask16 __U, __m512 __A) {
+ return (__m128i)__builtin_ia32_vcvtps2bf8s_512_mask(
+ (__v16sf)__A, (__v16qi)(__m128i)_mm_setzero_si128(), (__mmask16)__U);
+}
+
+// VCVTPS2HF8 - 128-bit
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS128
+_mm_cvtps_hf8(__m128 __A) {
+ return (__m128i)__builtin_ia32_vcvtps2hf8_128_mask(
+ (__v4sf)__A, (__v16qi)_mm_undefined_si128(), (__mmask8)-1);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS128
+_mm_mask_cvtps_hf8(__m128i __W, __mmask8 __U, __m128 __A) {
+ return (__m128i)__builtin_ia32_vcvtps2hf8_128_mask(
+ (__v4sf)__A, (__v16qi)(__m128i)__W, (__mmask8)__U);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS128
+_mm_maskz_cvtps_hf8(__mmask8 __U, __m128 __A) {
+ return (__m128i)__builtin_ia32_vcvtps2hf8_128_mask(
+ (__v4sf)__A, (__v16qi)(__m128i)_mm_setzero_si128(), (__mmask8)__U);
+}
+
+// VCVTPS2HF8 - 256-bit
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS256
+_mm256_cvtps_hf8(__m256 __A) {
+ return (__m128i)__builtin_ia32_vcvtps2hf8_256_mask(
+ (__v8sf)__A, (__v16qi)_mm_undefined_si128(), (__mmask8)-1);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS256
+_mm256_mask_cvtps_hf8(__m128i __W, __mmask8 __U, __m256 __A) {
+ return (__m128i)__builtin_ia32_vcvtps2hf8_256_mask(
+ (__v8sf)__A, (__v16qi)(__m128i)__W, (__mmask8)__U);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS256
+_mm256_maskz_cvtps_hf8(__mmask8 __U, __m256 __A) {
+ return (__m128i)__builtin_ia32_vcvtps2hf8_256_mask(
+ (__v8sf)__A, (__v16qi)(__m128i)_mm_setzero_si128(), (__mmask8)__U);
+}
+
+// VCVTPS2HF8 - 512-bit
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS512
+_mm512_cvtps_hf8(__m512 __A) {
+ return (__m128i)__builtin_ia32_vcvtps2hf8_512_mask(
+ (__v16sf)__A, (__v16qi)_mm_undefined_si128(), (__mmask16)-1);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS512
+_mm512_mask_cvtps_hf8(__m128i __W, __mmask16 __U, __m512 __A) {
+ return (__m128i)__builtin_ia32_vcvtps2hf8_512_mask(
+ (__v16sf)__A, (__v16qi)(__m128i)__W, (__mmask16)__U);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS512
+_mm512_maskz_cvtps_hf8(__mmask16 __U, __m512 __A) {
+ return (__m128i)__builtin_ia32_vcvtps2hf8_512_mask(
+ (__v16sf)__A, (__v16qi)(__m128i)_mm_setzero_si128(), (__mmask16)__U);
+}
+
+// VCVTPS2HF8S - 128-bit
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS128
+_mm_cvts_ps_hf8(__m128 __A) {
+ return (__m128i)__builtin_ia32_vcvtps2hf8s_128_mask(
+ (__v4sf)__A, (__v16qi)_mm_undefined_si128(), (__mmask8)-1);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS128
+_mm_mask_cvts_ps_hf8(__m128i __W, __mmask8 __U, __m128 __A) {
+ return (__m128i)__builtin_ia32_vcvtps2hf8s_128_mask(
+ (__v4sf)__A, (__v16qi)(__m128i)__W, (__mmask8)__U);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS128
+_mm_maskz_cvts_ps_hf8(__mmask8 __U, __m128 __A) {
+ return (__m128i)__builtin_ia32_vcvtps2hf8s_128_mask(
+ (__v4sf)__A, (__v16qi)(__m128i)_mm_setzero_si128(), (__mmask8)__U);
+}
+
+// VCVTPS2HF8S - 256-bit
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS256
+_mm256_cvts_ps_hf8(__m256 __A) {
+ return (__m128i)__builtin_ia32_vcvtps2hf8s_256_mask(
+ (__v8sf)__A, (__v16qi)_mm_undefined_si128(), (__mmask8)-1);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS256
+_mm256_mask_cvts_ps_hf8(__m128i __W, __mmask8 __U, __m256 __A) {
+ return (__m128i)__builtin_ia32_vcvtps2hf8s_256_mask(
+ (__v8sf)__A, (__v16qi)(__m128i)__W, (__mmask8)__U);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS256
+_mm256_maskz_cvts_ps_hf8(__mmask8 __U, __m256 __A) {
+ return (__m128i)__builtin_ia32_vcvtps2hf8s_256_mask(
+ (__v8sf)__A, (__v16qi)(__m128i)_mm_setzero_si128(), (__mmask8)__U);
+}
+
+// VCVTPS2HF8S - 512-bit
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS512
+_mm512_cvts_ps_hf8(__m512 __A) {
+ return (__m128i)__builtin_ia32_vcvtps2hf8s_512_mask(
+ (__v16sf)__A, (__v16qi)_mm_undefined_si128(), (__mmask16)-1);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS512
+_mm512_mask_cvts_ps_hf8(__m128i __W, __mmask16 __U, __m512 __A) {
+ return (__m128i)__builtin_ia32_vcvtps2hf8s_512_mask(
+ (__v16sf)__A, (__v16qi)(__m128i)__W, (__mmask16)__U);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS512
+_mm512_maskz_cvts_ps_hf8(__mmask16 __U, __m512 __A) {
+ return (__m128i)__builtin_ia32_vcvtps2hf8s_512_mask(
+ (__v16sf)__A, (__v16qi)(__m128i)_mm_setzero_si128(), (__mmask16)__U);
+}
+
+// VCVTROPS2HF8 - 128-bit
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS128
+_mm_cvtrops_hf8(__m128 __A) {
+ return (__m128i)__builtin_ia32_vcvtrops2hf8_128_mask(
+ (__v4sf)__A, (__v16qi)_mm_undefined_si128(), (__mmask8)-1);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS128
+_mm_mask_cvtrops_hf8(__m128i __W, __mmask8 __U, __m128 __A) {
+ return (__m128i)__builtin_ia32_vcvtrops2hf8_128_mask(
+ (__v4sf)__A, (__v16qi)(__m128i)__W, (__mmask8)__U);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS128
+_mm_maskz_cvtrops_hf8(__mmask8 __U, __m128 __A) {
+ return (__m128i)__builtin_ia32_vcvtrops2hf8_128_mask(
+ (__v4sf)__A, (__v16qi)(__m128i)_mm_setzero_si128(), (__mmask8)__U);
+}
+
+// VCVTROPS2HF8 - 256-bit
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS256
+_mm256_cvtrops_hf8(__m256 __A) {
+ return (__m128i)__builtin_ia32_vcvtrops2hf8_256_mask(
+ (__v8sf)__A, (__v16qi)_mm_undefined_si128(), (__mmask8)-1);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS256
+_mm256_mask_cvtrops_hf8(__m128i __W, __mmask8 __U, __m256 __A) {
+ return (__m128i)__builtin_ia32_vcvtrops2hf8_256_mask(
+ (__v8sf)__A, (__v16qi)(__m128i)__W, (__mmask8)__U);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS256
+_mm256_maskz_cvtrops_hf8(__mmask8 __U, __m256 __A) {
+ return (__m128i)__builtin_ia32_vcvtrops2hf8_256_mask(
+ (__v8sf)__A, (__v16qi)(__m128i)_mm_setzero_si128(), (__mmask8)__U);
+}
+
+// VCVTROPS2HF8 - 512-bit
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS512
+_mm512_cvtrops_hf8(__m512 __A) {
+ return (__m128i)__builtin_ia32_vcvtrops2hf8_512_mask(
+ (__v16sf)__A, (__v16qi)_mm_undefined_si128(), (__mmask16)-1);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS512
+_mm512_mask_cvtrops_hf8(__m128i __W, __mmask16 __U, __m512 __A) {
+ return (__m128i)__builtin_ia32_vcvtrops2hf8_512_mask(
+ (__v16sf)__A, (__v16qi)(__m128i)__W, (__mmask16)__U);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS512
+_mm512_maskz_cvtrops_hf8(__mmask16 __U, __m512 __A) {
+ return (__m128i)__builtin_ia32_vcvtrops2hf8_512_mask(
+ (__v16sf)__A, (__v16qi)(__m128i)_mm_setzero_si128(), (__mmask16)__U);
+}
+
+// VCVTROPS2HF8S - 128-bit
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS128
+_mm_cvts_rops_hf8(__m128 __A) {
+ return (__m128i)__builtin_ia32_vcvtrops2hf8s_128_mask(
+ (__v4sf)__A, (__v16qi)_mm_undefined_si128(), (__mmask8)-1);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS128
+_mm_mask_cvts_rops_hf8(__m128i __W, __mmask8 __U, __m128 __A) {
+ return (__m128i)__builtin_ia32_vcvtrops2hf8s_128_mask(
+ (__v4sf)__A, (__v16qi)(__m128i)__W, (__mmask8)__U);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS128
+_mm_maskz_cvts_rops_hf8(__mmask8 __U, __m128 __A) {
+ return (__m128i)__builtin_ia32_vcvtrops2hf8s_128_mask(
+ (__v4sf)__A, (__v16qi)(__m128i)_mm_setzero_si128(), (__mmask8)__U);
+}
+
+// VCVTROPS2HF8S - 256-bit
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS256
+_mm256_cvts_rops_hf8(__m256 __A) {
+ return (__m128i)__builtin_ia32_vcvtrops2hf8s_256_mask(
+ (__v8sf)__A, (__v16qi)_mm_undefined_si128(), (__mmask8)-1);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS256
+_mm256_mask_cvts_rops_hf8(__m128i __W, __mmask8 __U, __m256 __A) {
+ return (__m128i)__builtin_ia32_vcvtrops2hf8s_256_mask(
+ (__v8sf)__A, (__v16qi)(__m128i)__W, (__mmask8)__U);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS256
+_mm256_maskz_cvts_rops_hf8(__mmask8 __U, __m256 __A) {
+ return (__m128i)__builtin_ia32_vcvtrops2hf8s_256_mask(
+ (__v8sf)__A, (__v16qi)(__m128i)_mm_setzero_si128(), (__mmask8)__U);
+}
+
+// VCVTROPS2HF8S - 512-bit
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS512
+_mm512_cvts_rops_hf8(__m512 __A) {
+ return (__m128i)__builtin_ia32_vcvtrops2hf8s_512_mask(
+ (__v16sf)__A, (__v16qi)_mm_undefined_si128(), (__mmask16)-1);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS512
+_mm512_mask_cvts_rops_hf8(__m128i __W, __mmask16 __U, __m512 __A) {
+ return (__m128i)__builtin_ia32_vcvtrops2hf8s_512_mask(
+ (__v16sf)__A, (__v16qi)(__m128i)__W, (__mmask16)__U);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS512
+_mm512_maskz_cvts_rops_hf8(__mmask16 __U, __m512 __A) {
+ return (__m128i)__builtin_ia32_vcvtrops2hf8s_512_mask(
+ (__v16sf)__A, (__v16qi)(__m128i)_mm_setzero_si128(), (__mmask16)__U);
+}
+
+//===----------------------------------------------------------------------===//
+// Group B: VCVTBIASPS2BF8 / VCVTBIASPS2BF8S / VCVTBIASPS2HF8 /
+// VCVTBIASPS2HF8S
+// Convert packed single-precision with bias to FP8. Output is always __m128i.
+//===----------------------------------------------------------------------===//
+
+// VCVTBIASPS2BF8 - 128-bit
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS128
+_mm_cvtbiasps_bf8(__m128i __A, __m128 __B) {
+ return (__m128i)__builtin_ia32_vcvtbiasps2bf8_128_mask(
+ (__v16qi)__A, (__v4sf)__B, (__v16qi)_mm_undefined_si128(), (__mmask8)-1);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS128
+_mm_mask_cvtbiasps_bf8(__m128i __W, __mmask8 __U, __m128i __A, __m128 __B) {
+ return (__m128i)__builtin_ia32_vcvtbiasps2bf8_128_mask(
+ (__v16qi)__A, (__v4sf)__B, (__v16qi)(__m128i)__W, (__mmask8)__U);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS128
+_mm_maskz_cvtbiasps_bf8(__mmask8 __U, __m128i __A, __m128 __B) {
+ return (__m128i)__builtin_ia32_vcvtbiasps2bf8_128_mask(
+ (__v16qi)__A, (__v4sf)__B, (__v16qi)(__m128i)_mm_setzero_si128(),
+ (__mmask8)__U);
+}
+
+// VCVTBIASPS2BF8 - 256-bit
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS256
+_mm256_cvtbiasps_bf8(__m256i __A, __m256 __B) {
+ return (__m128i)__builtin_ia32_vcvtbiasps2bf8_256_mask(
+ (__v32qi)__A, (__v8sf)__B, (__v16qi)_mm_undefined_si128(), (__mmask8)-1);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS256
+_mm256_mask_cvtbiasps_bf8(__m128i __W, __mmask8 __U, __m256i __A, __m256 __B) {
+ return (__m128i)__builtin_ia32_vcvtbiasps2bf8_256_mask(
+ (__v32qi)__A, (__v8sf)__B, (__v16qi)(__m128i)__W, (__mmask8)__U);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS256
+_mm256_maskz_cvtbiasps_bf8(__mmask8 __U, __m256i __A, __m256 __B) {
+ return (__m128i)__builtin_ia32_vcvtbiasps2bf8_256_mask(
+ (__v32qi)__A, (__v8sf)__B, (__v16qi)(__m128i)_mm_setzero_si128(),
+ (__mmask8)__U);
+}
+
+// VCVTBIASPS2BF8 - 512-bit
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS512
+_mm512_cvtbiasps_bf8(__m512i __A, __m512 __B) {
+ return (__m128i)__builtin_ia32_vcvtbiasps2bf8_512_mask(
+ (__v64qi)__A, (__v16sf)__B, (__v16qi)_mm_undefined_si128(),
+ (__mmask16)-1);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS512
+_mm512_mask_cvtbiasps_bf8(__m128i __W, __mmask16 __U, __m512i __A,
+ __m512 __B) {
+ return (__m128i)__builtin_ia32_vcvtbiasps2bf8_512_mask(
+ (__v64qi)__A, (__v16sf)__B, (__v16qi)(__m128i)__W, (__mmask16)__U);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS512
+_mm512_maskz_cvtbiasps_bf8(__mmask16 __U, __m512i __A, __m512 __B) {
+ return (__m128i)__builtin_ia32_vcvtbiasps2bf8_512_mask(
+ (__v64qi)__A, (__v16sf)__B, (__v16qi)(__m128i)_mm_setzero_si128(),
+ (__mmask16)__U);
+}
+
+// VCVTBIASPS2BF8S - 128-bit
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS128
+_mm_cvts_biasps_bf8(__m128i __A, __m128 __B) {
+ return (__m128i)__builtin_ia32_vcvtbiasps2bf8s_128_mask(
+ (__v16qi)__A, (__v4sf)__B, (__v16qi)_mm_undefined_si128(), (__mmask8)-1);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS128
+_mm_mask_cvts_biasps_bf8(__m128i __W, __mmask8 __U, __m128i __A, __m128 __B) {
+ return (__m128i)__builtin_ia32_vcvtbiasps2bf8s_128_mask(
+ (__v16qi)__A, (__v4sf)__B, (__v16qi)(__m128i)__W, (__mmask8)__U);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS128
+_mm_maskz_cvts_biasps_bf8(__mmask8 __U, __m128i __A, __m128 __B) {
+ return (__m128i)__builtin_ia32_vcvtbiasps2bf8s_128_mask(
+ (__v16qi)__A, (__v4sf)__B, (__v16qi)(__m128i)_mm_setzero_si128(),
+ (__mmask8)__U);
+}
+
+// VCVTBIASPS2BF8S - 256-bit
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS256
+_mm256_cvts_biasps_bf8(__m256i __A, __m256 __B) {
+ return (__m128i)__builtin_ia32_vcvtbiasps2bf8s_256_mask(
+ (__v32qi)__A, (__v8sf)__B, (__v16qi)_mm_undefined_si128(), (__mmask8)-1);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_mask_cvts_biasps_bf8(
+ __m128i __W, __mmask8 __U, __m256i __A, __m256 __B) {
+ return (__m128i)__builtin_ia32_vcvtbiasps2bf8s_256_mask(
+ (__v32qi)__A, (__v8sf)__B, (__v16qi)(__m128i)__W, (__mmask8)__U);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS256
+_mm256_maskz_cvts_biasps_bf8(__mmask8 __U, __m256i __A, __m256 __B) {
+ return (__m128i)__builtin_ia32_vcvtbiasps2bf8s_256_mask(
+ (__v32qi)__A, (__v8sf)__B, (__v16qi)(__m128i)_mm_setzero_si128(),
+ (__mmask8)__U);
+}
+
+// VCVTBIASPS2BF8S - 512-bit
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS512
+_mm512_cvts_biasps_bf8(__m512i __A, __m512 __B) {
+ return (__m128i)__builtin_ia32_vcvtbiasps2bf8s_512_mask(
+ (__v64qi)__A, (__v16sf)__B, (__v16qi)_mm_undefined_si128(),
+ (__mmask16)-1);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS512
+_mm512_mask_cvts_biasps_bf8(__m128i __W, __mmask16 __U, __m512i __A,
+ __m512 __B) {
+ return (__m128i)__builtin_ia32_vcvtbiasps2bf8s_512_mask(
+ (__v64qi)__A, (__v16sf)__B, (__v16qi)(__m128i)__W, (__mmask16)__U);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS512
+_mm512_maskz_cvts_biasps_bf8(__mmask16 __U, __m512i __A, __m512 __B) {
+ return (__m128i)__builtin_ia32_vcvtbiasps2bf8s_512_mask(
+ (__v64qi)__A, (__v16sf)__B, (__v16qi)(__m128i)_mm_setzero_si128(),
+ (__mmask16)__U);
+}
+
+// VCVTBIASPS2HF8 - 128-bit
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS128
+_mm_cvtbiasps_hf8(__m128i __A, __m128 __B) {
+ return (__m128i)__builtin_ia32_vcvtbiasps2hf8_128_mask(
+ (__v16qi)__A, (__v4sf)__B, (__v16qi)_mm_undefined_si128(), (__mmask8)-1);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS128
+_mm_mask_cvtbiasps_hf8(__m128i __W, __mmask8 __U, __m128i __A, __m128 __B) {
+ return (__m128i)__builtin_ia32_vcvtbiasps2hf8_128_mask(
+ (__v16qi)__A, (__v4sf)__B, (__v16qi)(__m128i)__W, (__mmask8)__U);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS128
+_mm_maskz_cvtbiasps_hf8(__mmask8 __U, __m128i __A, __m128 __B) {
+ return (__m128i)__builtin_ia32_vcvtbiasps2hf8_128_mask(
+ (__v16qi)__A, (__v4sf)__B, (__v16qi)(__m128i)_mm_setzero_si128(),
+ (__mmask8)__U);
+}
+
+// VCVTBIASPS2HF8 - 256-bit
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS256
+_mm256_cvtbiasps_hf8(__m256i __A, __m256 __B) {
+ return (__m128i)__builtin_ia32_vcvtbiasps2hf8_256_mask(
+ (__v32qi)__A, (__v8sf)__B, (__v16qi)_mm_undefined_si128(), (__mmask8)-1);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS256
+_mm256_mask_cvtbiasps_hf8(__m128i __W, __mmask8 __U, __m256i __A, __m256 __B) {
+ return (__m128i)__builtin_ia32_vcvtbiasps2hf8_256_mask(
+ (__v32qi)__A, (__v8sf)__B, (__v16qi)(__m128i)__W, (__mmask8)__U);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS256
+_mm256_maskz_cvtbiasps_hf8(__mmask8 __U, __m256i __A, __m256 __B) {
+ return (__m128i)__builtin_ia32_vcvtbiasps2hf8_256_mask(
+ (__v32qi)__A, (__v8sf)__B, (__v16qi)(__m128i)_mm_setzero_si128(),
+ (__mmask8)__U);
+}
+
+// VCVTBIASPS2HF8 - 512-bit
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS512
+_mm512_cvtbiasps_hf8(__m512i __A, __m512 __B) {
+ return (__m128i)__builtin_ia32_vcvtbiasps2hf8_512_mask(
+ (__v64qi)__A, (__v16sf)__B, (__v16qi)_mm_undefined_si128(),
+ (__mmask16)-1);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS512
+_mm512_mask_cvtbiasps_hf8(__m128i __W, __mmask16 __U, __m512i __A,
+ __m512 __B) {
+ return (__m128i)__builtin_ia32_vcvtbiasps2hf8_512_mask(
+ (__v64qi)__A, (__v16sf)__B, (__v16qi)(__m128i)__W, (__mmask16)__U);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS512
+_mm512_maskz_cvtbiasps_hf8(__mmask16 __U, __m512i __A, __m512 __B) {
+ return (__m128i)__builtin_ia32_vcvtbiasps2hf8_512_mask(
+ (__v64qi)__A, (__v16sf)__B, (__v16qi)(__m128i)_mm_setzero_si128(),
+ (__mmask16)__U);
+}
+
+// VCVTBIASPS2HF8S - 128-bit
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS128
+_mm_cvts_biasps_hf8(__m128i __A, __m128 __B) {
+ return (__m128i)__builtin_ia32_vcvtbiasps2hf8s_128_mask(
+ (__v16qi)__A, (__v4sf)__B, (__v16qi)_mm_undefined_si128(), (__mmask8)-1);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS128
+_mm_mask_cvts_biasps_hf8(__m128i __W, __mmask8 __U, __m128i __A, __m128 __B) {
+ return (__m128i)__builtin_ia32_vcvtbiasps2hf8s_128_mask(
+ (__v16qi)__A, (__v4sf)__B, (__v16qi)(__m128i)__W, (__mmask8)__U);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS128
+_mm_maskz_cvts_biasps_hf8(__mmask8 __U, __m128i __A, __m128 __B) {
+ return (__m128i)__builtin_ia32_vcvtbiasps2hf8s_128_mask(
+ (__v16qi)__A, (__v4sf)__B, (__v16qi)(__m128i)_mm_setzero_si128(),
+ (__mmask8)__U);
+}
+
+// VCVTBIASPS2HF8S - 256-bit
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS256
+_mm256_cvts_biasps_hf8(__m256i __A, __m256 __B) {
+ return (__m128i)__builtin_ia32_vcvtbiasps2hf8s_256_mask(
+ (__v32qi)__A, (__v8sf)__B, (__v16qi)_mm_undefined_si128(), (__mmask8)-1);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_mask_cvts_biasps_hf8(
+ __m128i __W, __mmask8 __U, __m256i __A, __m256 __B) {
+ return (__m128i)__builtin_ia32_vcvtbiasps2hf8s_256_mask(
+ (__v32qi)__A, (__v8sf)__B, (__v16qi)(__m128i)__W, (__mmask8)__U);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS256
+_mm256_maskz_cvts_biasps_hf8(__mmask8 __U, __m256i __A, __m256 __B) {
+ return (__m128i)__builtin_ia32_vcvtbiasps2hf8s_256_mask(
+ (__v32qi)__A, (__v8sf)__B, (__v16qi)(__m128i)_mm_setzero_si128(),
+ (__mmask8)__U);
+}
+
+// VCVTBIASPS2HF8S - 512-bit
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS512
+_mm512_cvts_biasps_hf8(__m512i __A, __m512 __B) {
+ return (__m128i)__builtin_ia32_vcvtbiasps2hf8s_512_mask(
+ (__v64qi)__A, (__v16sf)__B, (__v16qi)_mm_undefined_si128(),
+ (__mmask16)-1);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS512
+_mm512_mask_cvts_biasps_hf8(__m128i __W, __mmask16 __U, __m512i __A,
+ __m512 __B) {
+ return (__m128i)__builtin_ia32_vcvtbiasps2hf8s_512_mask(
+ (__v64qi)__A, (__v16sf)__B, (__v16qi)(__m128i)__W, (__mmask16)__U);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS512
+_mm512_maskz_cvts_biasps_hf8(__mmask16 __U, __m512i __A, __m512 __B) {
+ return (__m128i)__builtin_ia32_vcvtbiasps2hf8s_512_mask(
+ (__v64qi)__A, (__v16sf)__B, (__v16qi)(__m128i)_mm_setzero_si128(),
+ (__mmask16)__U);
+}
+
+//===----------------------------------------------------------------------===//
+// Group C: VCVTBF82PS / VCVTHF82PS
+// Convert packed FP8 to single-precision. Input is __m128i, output varies.
+//===----------------------------------------------------------------------===//
+
+// VCVTBF82PS - 128-bit
+
+static __inline__ __m128 __DEFAULT_FN_ATTRS128
+_mm_cvtbf8_ps(__m128i __A) {
+ return (__m128)__builtin_ia32_vcvtbf8_2ps128_mask(
+ (__v16qi)__A, (__v4sf)_mm_undefined_ps(), (__mmask8)-1);
+}
+
+static __inline__ __m128 __DEFAULT_FN_ATTRS128
+_mm_mask_cvtbf8_ps(__m128 __W, __mmask8 __U, __m128i __A) {
+ return (__m128)__builtin_ia32_vcvtbf8_2ps128_mask(
+ (__v16qi)__A, (__v4sf)__W, (__mmask8)__U);
+}
+
+static __inline__ __m128 __DEFAULT_FN_ATTRS128
+_mm_maskz_cvtbf8_ps(__mmask8 __U, __m128i __A) {
+ return (__m128)__builtin_ia32_vcvtbf8_2ps128_mask(
+ (__v16qi)__A, (__v4sf)_mm_setzero_ps(), (__mmask8)__U);
+}
+
+// VCVTBF82PS - 256-bit
+
+static __inline__ __m256 __DEFAULT_FN_ATTRS256
+_mm256_cvtbf8_ps(__m128i __A) {
+ return (__m256)__builtin_ia32_vcvtbf8_2ps256_mask(
+ (__v16qi)__A, (__v8sf)_mm256_undefined_ps(), (__mmask8)-1);
+}
+
+static __inline__ __m256 __DEFAULT_FN_ATTRS256
+_mm256_mask_cvtbf8_ps(__m256 __W, __mmask8 __U, __m128i __A) {
+ return (__m256)__builtin_ia32_vcvtbf8_2ps256_mask(
+ (__v16qi)__A, (__v8sf)__W, (__mmask8)__U);
+}
+
+static __inline__ __m256 __DEFAULT_FN_ATTRS256
+_mm256_maskz_cvtbf8_ps(__mmask8 __U, __m128i __A) {
+ return (__m256)__builtin_ia32_vcvtbf8_2ps256_mask(
+ (__v16qi)__A, (__v8sf)_mm256_setzero_ps(), (__mmask8)__U);
+}
+
+// VCVTBF82PS - 512-bit
+
+static __inline__ __m512 __DEFAULT_FN_ATTRS512
+_mm512_cvtbf8_ps(__m128i __A) {
+ return (__m512)__builtin_ia32_vcvtbf8_2ps512_mask(
+ (__v16qi)__A, (__v16sf)_mm512_undefined_ps(), (__mmask16)-1);
+}
+
+static __inline__ __m512 __DEFAULT_FN_ATTRS512
+_mm512_mask_cvtbf8_ps(__m512 __W, __mmask16 __U, __m128i __A) {
+ return (__m512)__builtin_ia32_vcvtbf8_2ps512_mask(
+ (__v16qi)__A, (__v16sf)__W, (__mmask16)__U);
+}
+
+static __inline__ __m512 __DEFAULT_FN_ATTRS512
+_mm512_maskz_cvtbf8_ps(__mmask16 __U, __m128i __A) {
+ return (__m512)__builtin_ia32_vcvtbf8_2ps512_mask(
+ (__v16qi)__A, (__v16sf)_mm512_setzero_ps(), (__mmask16)__U);
+}
+
+// VCVTHF82PS - 128-bit
+
+static __inline__ __m128 __DEFAULT_FN_ATTRS128
+_mm_cvthf8_ps(__m128i __A) {
+ return (__m128)__builtin_ia32_vcvthf8_2ps128_mask(
+ (__v16qi)__A, (__v4sf)_mm_undefined_ps(), (__mmask8)-1);
+}
+
+static __inline__ __m128 __DEFAULT_FN_ATTRS128
+_mm_mask_cvthf8_ps(__m128 __W, __mmask8 __U, __m128i __A) {
+ return (__m128)__builtin_ia32_vcvthf8_2ps128_mask(
+ (__v16qi)__A, (__v4sf)__W, (__mmask8)__U);
+}
+
+static __inline__ __m128 __DEFAULT_FN_ATTRS128
+_mm_maskz_cvthf8_ps(__mmask8 __U, __m128i __A) {
+ return (__m128)__builtin_ia32_vcvthf8_2ps128_mask(
+ (__v16qi)__A, (__v4sf)_mm_setzero_ps(), (__mmask8)__U);
+}
+
+// VCVTHF82PS - 256-bit
+
+static __inline__ __m256 __DEFAULT_FN_ATTRS256
+_mm256_cvthf8_ps(__m128i __A) {
+ return (__m256)__builtin_ia32_vcvthf8_2ps256_mask(
+ (__v16qi)__A, (__v8sf)_mm256_undefined_ps(), (__mmask8)-1);
+}
+
+static __inline__ __m256 __DEFAULT_FN_ATTRS256
+_mm256_mask_cvthf8_ps(__m256 __W, __mmask8 __U, __m128i __A) {
+ return (__m256)__builtin_ia32_vcvthf8_2ps256_mask(
+ (__v16qi)__A, (__v8sf)__W, (__mmask8)__U);
+}
+
+static __inline__ __m256 __DEFAULT_FN_ATTRS256
+_mm256_maskz_cvthf8_ps(__mmask8 __U, __m128i __A) {
+ return (__m256)__builtin_ia32_vcvthf8_2ps256_mask(
+ (__v16qi)__A, (__v8sf)_mm256_setzero_ps(), (__mmask8)__U);
+}
+
+// VCVTHF82PS - 512-bit
+
+static __inline__ __m512 __DEFAULT_FN_ATTRS512
+_mm512_cvthf8_ps(__m128i __A) {
+ return (__m512)__builtin_ia32_vcvthf8_2ps512_mask(
+ (__v16qi)__A, (__v16sf)_mm512_undefined_ps(), (__mmask16)-1);
+}
+
+static __inline__ __m512 __DEFAULT_FN_ATTRS512
+_mm512_mask_cvthf8_ps(__m512 __W, __mmask16 __U, __m128i __A) {
+ return (__m512)__builtin_ia32_vcvthf8_2ps512_mask(
+ (__v16qi)__A, (__v16sf)__W, (__mmask16)__U);
+}
+
+static __inline__ __m512 __DEFAULT_FN_ATTRS512
+_mm512_maskz_cvthf8_ps(__mmask16 __U, __m128i __A) {
+ return (__m512)__builtin_ia32_vcvthf8_2ps512_mask(
+ (__v16qi)__A, (__v16sf)_mm512_setzero_ps(), (__mmask16)__U);
+}
+
+//===----------------------------------------------------------------------===//
+// Group E: VCVTBF82BF6S / VCVTHF82HF6S
+// Same-size reg-only conversions (no masking support)
+//===----------------------------------------------------------------------===//
+
+// VCVTBF82BF6S
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS128
+_mm_cvtbf8_bf6s(__m128i __A) {
+ return (__m128i)__builtin_ia32_vcvtbf82bf6s128((__v16qi)__A);
+}
+
+static __inline__ __m256i __DEFAULT_FN_ATTRS256
+_mm256_cvtbf8_bf6s(__m256i __A) {
+ return (__m256i)__builtin_ia32_vcvtbf82bf6s256((__v32qi)__A);
+}
+
+static __inline__ __m512i __DEFAULT_FN_ATTRS512
+_mm512_cvtbf8_bf6s(__m512i __A) {
+ return (__m512i)__builtin_ia32_vcvtbf82bf6s512((__v64qi)__A);
+}
+
+// VCVTHF82HF6S
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS128
+_mm_cvthf8_hf6s(__m128i __A) {
+ return (__m128i)__builtin_ia32_vcvthf82hf6s128((__v16qi)__A);
+}
+
+static __inline__ __m256i __DEFAULT_FN_ATTRS256
+_mm256_cvthf8_hf6s(__m256i __A) {
+ return (__m256i)__builtin_ia32_vcvthf82hf6s256((__v32qi)__A);
+}
+
+static __inline__ __m512i __DEFAULT_FN_ATTRS512
+_mm512_cvthf8_hf6s(__m512i __A) {
+ return (__m512i)__builtin_ia32_vcvthf82hf6s512((__v64qi)__A);
+}
+
+//===----------------------------------------------------------------------===//
+// Group F: VCVTBF42HF8 / VCVTBF62HF8 / VCVTHF62HF8
+// Expanding/same-size conversions with masking support
+//===----------------------------------------------------------------------===//
+
+// VCVTBF42HF8 - 128-bit
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS128
+_mm_cvtbf4_hf8(__m128i __A) {
+ return (__m128i)__builtin_ia32_vcvtbf42hf8128((__v16qi)__A);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS128
+_mm_mask_cvtbf4_hf8(__m128i __W, __mmask16 __U, __m128i __A) {
+ return (__m128i)__builtin_ia32_selectb_128(
+ __U, (__v16qi)_mm_cvtbf4_hf8(__A), (__v16qi)__W);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS128
+_mm_maskz_cvtbf4_hf8(__mmask16 __U, __m128i __A) {
+ return (__m128i)__builtin_ia32_selectb_128(
+ __U, (__v16qi)_mm_cvtbf4_hf8(__A), (__v16qi)_mm_setzero_si128());
+}
+
+// VCVTBF42HF8 - 256-bit
+
+static __inline__ __m256i __DEFAULT_FN_ATTRS256
+_mm256_cvtbf4_hf8(__m128i __A) {
+ return (__m256i)__builtin_ia32_vcvtbf42hf8256((__v16qi)__A);
+}
+
+static __inline__ __m256i __DEFAULT_FN_ATTRS256
+_mm256_mask_cvtbf4_hf8(__m256i __W, __mmask32 __U, __m128i __A) {
+ return (__m256i)__builtin_ia32_selectb_256(
+ __U, (__v32qi)_mm256_cvtbf4_hf8(__A), (__v32qi)__W);
+}
+
+static __inline__ __m256i __DEFAULT_FN_ATTRS256
+_mm256_maskz_cvtbf4_hf8(__mmask32 __U, __m128i __A) {
+ return (__m256i)__builtin_ia32_selectb_256(
+ __U, (__v32qi)_mm256_cvtbf4_hf8(__A), (__v32qi)_mm256_setzero_si256());
+}
+
+// VCVTBF42HF8 - 512-bit
+
+static __inline__ __m512i __DEFAULT_FN_ATTRS512
+_mm512_cvtbf4_hf8(__m256i __A) {
+ return (__m512i)__builtin_ia32_vcvtbf42hf8512((__v32qi)__A);
+}
+
+static __inline__ __m512i __DEFAULT_FN_ATTRS512
+_mm512_mask_cvtbf4_hf8(__m512i __W, __mmask64 __U, __m256i __A) {
+ return (__m512i)__builtin_ia32_selectb_512(
+ __U, (__v64qi)_mm512_cvtbf4_hf8(__A), (__v64qi)__W);
+}
+
+static __inline__ __m512i __DEFAULT_FN_ATTRS512
+_mm512_maskz_cvtbf4_hf8(__mmask64 __U, __m256i __A) {
+ return (__m512i)__builtin_ia32_selectb_512(
+ __U, (__v64qi)_mm512_cvtbf4_hf8(__A), (__v64qi)_mm512_setzero_si512());
+}
+
+// VCVTBF62HF8 - 128-bit
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS128
+_mm_cvtbf6_hf8(__m128i __A) {
+ return (__m128i)__builtin_ia32_vcvtbf62hf8128((__v16qi)__A);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS128
+_mm_mask_cvtbf6_hf8(__m128i __W, __mmask16 __U, __m128i __A) {
+ return (__m128i)__builtin_ia32_selectb_128(
+ __U, (__v16qi)_mm_cvtbf6_hf8(__A), (__v16qi)__W);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS128
+_mm_maskz_cvtbf6_hf8(__mmask16 __U, __m128i __A) {
+ return (__m128i)__builtin_ia32_selectb_128(
+ __U, (__v16qi)_mm_cvtbf6_hf8(__A), (__v16qi)_mm_setzero_si128());
+}
+
+// VCVTBF62HF8 - 256-bit
+
+static __inline__ __m256i __DEFAULT_FN_ATTRS256
+_mm256_cvtbf6_hf8(__m256i __A) {
+ return (__m256i)__builtin_ia32_vcvtbf62hf8256((__v32qi)__A);
+}
+
+static __inline__ __m256i __DEFAULT_FN_ATTRS256
+_mm256_mask_cvtbf6_hf8(__m256i __W, __mmask32 __U, __m256i __A) {
+ return (__m256i)__builtin_ia32_selectb_256(
+ __U, (__v32qi)_mm256_cvtbf6_hf8(__A), (__v32qi)__W);
+}
+
+static __inline__ __m256i __DEFAULT_FN_ATTRS256
+_mm256_maskz_cvtbf6_hf8(__mmask32 __U, __m256i __A) {
+ return (__m256i)__builtin_ia32_selectb_256(
+ __U, (__v32qi)_mm256_cvtbf6_hf8(__A), (__v32qi)_mm256_setzero_si256());
+}
+
+// VCVTBF62HF8 - 512-bit
+
+static __inline__ __m512i __DEFAULT_FN_ATTRS512
+_mm512_cvtbf6_hf8(__m512i __A) {
+ return (__m512i)__builtin_ia32_vcvtbf62hf8512((__v64qi)__A);
+}
+
+static __inline__ __m512i __DEFAULT_FN_ATTRS512
+_mm512_mask_cvtbf6_hf8(__m512i __W, __mmask64 __U, __m512i __A) {
+ return (__m512i)__builtin_ia32_selectb_512(
+ __U, (__v64qi)_mm512_cvtbf6_hf8(__A), (__v64qi)__W);
+}
+
+static __inline__ __m512i __DEFAULT_FN_ATTRS512
+_mm512_maskz_cvtbf6_hf8(__mmask64 __U, __m512i __A) {
+ return (__m512i)__builtin_ia32_selectb_512(
+ __U, (__v64qi)_mm512_cvtbf6_hf8(__A), (__v64qi)_mm512_setzero_si512());
+}
+
+// VCVTHF62HF8 - 128-bit
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS128
+_mm_cvthf6_hf8(__m128i __A) {
+ return (__m128i)__builtin_ia32_vcvthf62hf8128((__v16qi)__A);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS128
+_mm_mask_cvthf6_hf8(__m128i __W, __mmask16 __U, __m128i __A) {
+ return (__m128i)__builtin_ia32_selectb_128(
+ __U, (__v16qi)_mm_cvthf6_hf8(__A), (__v16qi)__W);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS128
+_mm_maskz_cvthf6_hf8(__mmask16 __U, __m128i __A) {
+ return (__m128i)__builtin_ia32_selectb_128(
+ __U, (__v16qi)_mm_cvthf6_hf8(__A), (__v16qi)_mm_setzero_si128());
+}
+
+// VCVTHF62HF8 - 256-bit
+
+static __inline__ __m256i __DEFAULT_FN_ATTRS256
+_mm256_cvthf6_hf8(__m256i __A) {
+ return (__m256i)__builtin_ia32_vcvthf62hf8256((__v32qi)__A);
+}
+
+static __inline__ __m256i __DEFAULT_FN_ATTRS256
+_mm256_mask_cvthf6_hf8(__m256i __W, __mmask32 __U, __m256i __A) {
+ return (__m256i)__builtin_ia32_selectb_256(
+ __U, (__v32qi)_mm256_cvthf6_hf8(__A), (__v32qi)__W);
+}
+
+static __inline__ __m256i __DEFAULT_FN_ATTRS256
+_mm256_maskz_cvthf6_hf8(__mmask32 __U, __m256i __A) {
+ return (__m256i)__builtin_ia32_selectb_256(
+ __U, (__v32qi)_mm256_cvthf6_hf8(__A), (__v32qi)_mm256_setzero_si256());
+}
+
+// VCVTHF62HF8 - 512-bit
+
+static __inline__ __m512i __DEFAULT_FN_ATTRS512
+_mm512_cvthf6_hf8(__m512i __A) {
+ return (__m512i)__builtin_ia32_vcvthf62hf8512((__v64qi)__A);
+}
+
+static __inline__ __m512i __DEFAULT_FN_ATTRS512
+_mm512_mask_cvthf6_hf8(__m512i __W, __mmask64 __U, __m512i __A) {
+ return (__m512i)__builtin_ia32_selectb_512(
+ __U, (__v64qi)_mm512_cvthf6_hf8(__A), (__v64qi)__W);
+}
+
+static __inline__ __m512i __DEFAULT_FN_ATTRS512
+_mm512_maskz_cvthf6_hf8(__mmask64 __U, __m512i __A) {
+ return (__m512i)__builtin_ia32_selectb_512(
+ __U, (__v64qi)_mm512_cvthf6_hf8(__A), (__v64qi)_mm512_setzero_si512());
+}
+
+//===----------------------------------------------------------------------===//
+// Group H: VUNPACKB
+// Byte unpack with immediate
+//===----------------------------------------------------------------------===//
+
+// VUNPACKB - 128-bit
+
+#define _mm_unpackb_epi8(A, imm) \
+ ((__m128i)__builtin_ia32_vunpackb128((__v16qi)(__m128i)(A), (int)(imm)))
+
+#define _mm_mask_unpackb_epi8(W, U, A, imm) \
+ ((__m128i)__builtin_ia32_selectb_128( \
+ (__mmask16)(U), \
+ (__v16qi)_mm_unpackb_epi8((A), (imm)), \
+ (__v16qi)(__m128i)(W)))
+
+#define _mm_maskz_unpackb_epi8(U, A, imm) \
+ ((__m128i)__builtin_ia32_selectb_128( \
+ (__mmask16)(U), \
+ (__v16qi)_mm_unpackb_epi8((A), (imm)), \
+ (__v16qi)_mm_setzero_si128()))
+
+// VUNPACKB - 256-bit
+
+#define _mm256_unpackb_epi8(A, imm) \
+ ((__m256i)__builtin_ia32_vunpackb256((__v32qi)(__m256i)(A), (int)(imm)))
+
+#define _mm256_mask_unpackb_epi8(W, U, A, imm) \
+ ((__m256i)__builtin_ia32_selectb_256( \
+ (__mmask32)(U), \
+ (__v32qi)_mm256_unpackb_epi8((A), (imm)), \
+ (__v32qi)(__m256i)(W)))
+
+#define _mm256_maskz_unpackb_epi8(U, A, imm) \
+ ((__m256i)__builtin_ia32_selectb_256( \
+ (__mmask32)(U), \
+ (__v32qi)_mm256_unpackb_epi8((A), (imm)), \
+ (__v32qi)_mm256_setzero_si256()))
+
+// VUNPACKB - 512-bit
+
+#define _mm512_unpackb_epi8(A, imm) \
+ ((__m512i)__builtin_ia32_vunpackb512((__v64qi)(__m512i)(A), (int)(imm)))
+
+#define _mm512_mask_unpackb_epi8(W, U, A, imm) \
+ ((__m512i)__builtin_ia32_selectb_512( \
+ (__mmask64)(U), \
+ (__v64qi)_mm512_unpackb_epi8((A), (imm)), \
+ (__v64qi)(__m512i)(W)))
+
+#define _mm512_maskz_unpackb_epi8(U, A, imm) \
+ ((__m512i)__builtin_ia32_selectb_512( \
+ (__mmask64)(U), \
+ (__v64qi)_mm512_unpackb_epi8((A), (imm)), \
+ (__v64qi)_mm512_setzero_si512()))
+
+// clang-format on
+
+#undef __DEFAULT_FN_ATTRS128
+#undef __DEFAULT_FN_ATTRS256
+#undef __DEFAULT_FN_ATTRS512
+
+#endif // __AVX10_2_V2AUXINTRIN_H
+#endif // __SSE2__
diff --git a/clang/lib/Headers/cpuid.h b/clang/lib/Headers/cpuid.h
index 156425c7561bb..a8c6adbc3e2dc 100644
--- a/clang/lib/Headers/cpuid.h
+++ b/clang/lib/Headers/cpuid.h
@@ -222,6 +222,9 @@
#define bit_AVX10 0x00080000
#define bit_APXF 0x00200000
+/* Features in %ecx for leaf 24 sub-leaf 1 */
+#define bit_AVX10_V2_AUX 0x00000008
+
/* Features in %eax for leaf 13 sub-leaf 1 */
#define bit_XSAVEOPT 0x00000001
#define bit_XSAVEC 0x00000002
diff --git a/clang/lib/Headers/immintrin.h b/clang/lib/Headers/immintrin.h
index 19064a4ff5cea..bd474d6507935 100644
--- a/clang/lib/Headers/immintrin.h
+++ b/clang/lib/Headers/immintrin.h
@@ -500,6 +500,10 @@ _storebe_i64(void * __P, long long __D) {
#include <avx10_2_512satcvtdsintrin.h>
#include <avx10_2_512satcvtintrin.h>
+#ifdef __AVX10_V2_AUX__
+#include <avx10_2_v2auxintrin.h>
+#endif
+
#include <sm4evexintrin.h>
#include <enqcmdintrin.h>
diff --git a/clang/test/CodeGen/X86/avx10_2_v2aux-builtins.c b/clang/test/CodeGen/X86/avx10_2_v2aux-builtins.c
new file mode 100644
index 0000000000000..c4d076b27b21e
--- /dev/null
+++ b/clang/test/CodeGen/X86/avx10_2_v2aux-builtins.c
@@ -0,0 +1,1056 @@
+// RUN: %clang_cc1 %s -flax-vector-conversions=none -ffreestanding -triple=x86_64 -target-feature +avx10-v2-aux \
+// RUN: -emit-llvm -o - -Wno-invalid-feature-combination -Wall -Werror | FileCheck %s
+// RUN: %clang_cc1 %s -flax-vector-conversions=none -ffreestanding -triple=i386 -target-feature +avx10-v2-aux \
+// RUN: -emit-llvm -o - -Wno-invalid-feature-combination -Wall -Werror | FileCheck %s
+
+#include <immintrin.h>
+
+//
+// Group A: VCVTPS2BF8 / VCVTPS2BF8S / VCVTPS2HF8 / VCVTPS2HF8S /
+// VCVTROPS2HF8 / VCVTROPS2HF8S
+//
+
+// VCVTPS2BF8 - 128-bit
+
+__m128i test_mm_cvtps_bf8(__m128 __A) {
+ // CHECK-LABEL: @test_mm_cvtps_bf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtps2bf8.128(
+ return _mm_cvtps_bf8(__A);
+}
+
+__m128i test_mm_mask_cvtps_bf8(__m128i __W, __mmask8 __U, __m128 __A) {
+ // CHECK-LABEL: @test_mm_mask_cvtps_bf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtps2bf8.128(
+ return _mm_mask_cvtps_bf8(__W, __U, __A);
+}
+
+__m128i test_mm_maskz_cvtps_bf8(__mmask8 __U, __m128 __A) {
+ // CHECK-LABEL: @test_mm_maskz_cvtps_bf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtps2bf8.128(
+ return _mm_maskz_cvtps_bf8(__U, __A);
+}
+
+// VCVTPS2BF8 - 256-bit
+
+__m128i test_mm256_cvtps_bf8(__m256 __A) {
+ // CHECK-LABEL: @test_mm256_cvtps_bf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtps2bf8.256(
+ return _mm256_cvtps_bf8(__A);
+}
+
+__m128i test_mm256_mask_cvtps_bf8(__m128i __W, __mmask8 __U, __m256 __A) {
+ // CHECK-LABEL: @test_mm256_mask_cvtps_bf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtps2bf8.256(
+ return _mm256_mask_cvtps_bf8(__W, __U, __A);
+}
+
+__m128i test_mm256_maskz_cvtps_bf8(__mmask8 __U, __m256 __A) {
+ // CHECK-LABEL: @test_mm256_maskz_cvtps_bf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtps2bf8.256(
+ return _mm256_maskz_cvtps_bf8(__U, __A);
+}
+
+// VCVTPS2BF8 - 512-bit
+
+__m128i test_mm512_cvtps_bf8(__m512 __A) {
+ // CHECK-LABEL: @test_mm512_cvtps_bf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtps2bf8.512(
+ return _mm512_cvtps_bf8(__A);
+}
+
+__m128i test_mm512_mask_cvtps_bf8(__m128i __W, __mmask16 __U, __m512 __A) {
+ // CHECK-LABEL: @test_mm512_mask_cvtps_bf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtps2bf8.512(
+ return _mm512_mask_cvtps_bf8(__W, __U, __A);
+}
+
+__m128i test_mm512_maskz_cvtps_bf8(__mmask16 __U, __m512 __A) {
+ // CHECK-LABEL: @test_mm512_maskz_cvtps_bf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtps2bf8.512(
+ return _mm512_maskz_cvtps_bf8(__U, __A);
+}
+
+// VCVTPS2BF8S - 128-bit
+
+__m128i test_mm_cvts_ps_bf8(__m128 __A) {
+ // CHECK-LABEL: @test_mm_cvts_ps_bf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtps2bf8s.128(
+ return _mm_cvts_ps_bf8(__A);
+}
+
+__m128i test_mm_mask_cvts_ps_bf8(__m128i __W, __mmask8 __U, __m128 __A) {
+ // CHECK-LABEL: @test_mm_mask_cvts_ps_bf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtps2bf8s.128(
+ return _mm_mask_cvts_ps_bf8(__W, __U, __A);
+}
+
+__m128i test_mm_maskz_cvts_ps_bf8(__mmask8 __U, __m128 __A) {
+ // CHECK-LABEL: @test_mm_maskz_cvts_ps_bf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtps2bf8s.128(
+ return _mm_maskz_cvts_ps_bf8(__U, __A);
+}
+
+// VCVTPS2BF8S - 256-bit
+
+__m128i test_mm256_cvts_ps_bf8(__m256 __A) {
+ // CHECK-LABEL: @test_mm256_cvts_ps_bf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtps2bf8s.256(
+ return _mm256_cvts_ps_bf8(__A);
+}
+
+__m128i test_mm256_mask_cvts_ps_bf8(__m128i __W, __mmask8 __U, __m256 __A) {
+ // CHECK-LABEL: @test_mm256_mask_cvts_ps_bf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtps2bf8s.256(
+ return _mm256_mask_cvts_ps_bf8(__W, __U, __A);
+}
+
+__m128i test_mm256_maskz_cvts_ps_bf8(__mmask8 __U, __m256 __A) {
+ // CHECK-LABEL: @test_mm256_maskz_cvts_ps_bf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtps2bf8s.256(
+ return _mm256_maskz_cvts_ps_bf8(__U, __A);
+}
+
+// VCVTPS2BF8S - 512-bit
+
+__m128i test_mm512_cvts_ps_bf8(__m512 __A) {
+ // CHECK-LABEL: @test_mm512_cvts_ps_bf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtps2bf8s.512(
+ return _mm512_cvts_ps_bf8(__A);
+}
+
+__m128i test_mm512_mask_cvts_ps_bf8(__m128i __W, __mmask16 __U, __m512 __A) {
+ // CHECK-LABEL: @test_mm512_mask_cvts_ps_bf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtps2bf8s.512(
+ return _mm512_mask_cvts_ps_bf8(__W, __U, __A);
+}
+
+__m128i test_mm512_maskz_cvts_ps_bf8(__mmask16 __U, __m512 __A) {
+ // CHECK-LABEL: @test_mm512_maskz_cvts_ps_bf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtps2bf8s.512(
+ return _mm512_maskz_cvts_ps_bf8(__U, __A);
+}
+
+// VCVTPS2HF8 - 128-bit
+
+__m128i test_mm_cvtps_hf8(__m128 __A) {
+ // CHECK-LABEL: @test_mm_cvtps_hf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtps2hf8.128(
+ return _mm_cvtps_hf8(__A);
+}
+
+__m128i test_mm_mask_cvtps_hf8(__m128i __W, __mmask8 __U, __m128 __A) {
+ // CHECK-LABEL: @test_mm_mask_cvtps_hf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtps2hf8.128(
+ return _mm_mask_cvtps_hf8(__W, __U, __A);
+}
+
+__m128i test_mm_maskz_cvtps_hf8(__mmask8 __U, __m128 __A) {
+ // CHECK-LABEL: @test_mm_maskz_cvtps_hf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtps2hf8.128(
+ return _mm_maskz_cvtps_hf8(__U, __A);
+}
+
+// VCVTPS2HF8 - 256-bit
+
+__m128i test_mm256_cvtps_hf8(__m256 __A) {
+ // CHECK-LABEL: @test_mm256_cvtps_hf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtps2hf8.256(
+ return _mm256_cvtps_hf8(__A);
+}
+
+__m128i test_mm256_mask_cvtps_hf8(__m128i __W, __mmask8 __U, __m256 __A) {
+ // CHECK-LABEL: @test_mm256_mask_cvtps_hf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtps2hf8.256(
+ return _mm256_mask_cvtps_hf8(__W, __U, __A);
+}
+
+__m128i test_mm256_maskz_cvtps_hf8(__mmask8 __U, __m256 __A) {
+ // CHECK-LABEL: @test_mm256_maskz_cvtps_hf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtps2hf8.256(
+ return _mm256_maskz_cvtps_hf8(__U, __A);
+}
+
+// VCVTPS2HF8 - 512-bit
+
+__m128i test_mm512_cvtps_hf8(__m512 __A) {
+ // CHECK-LABEL: @test_mm512_cvtps_hf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtps2hf8.512(
+ return _mm512_cvtps_hf8(__A);
+}
+
+__m128i test_mm512_mask_cvtps_hf8(__m128i __W, __mmask16 __U, __m512 __A) {
+ // CHECK-LABEL: @test_mm512_mask_cvtps_hf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtps2hf8.512(
+ return _mm512_mask_cvtps_hf8(__W, __U, __A);
+}
+
+__m128i test_mm512_maskz_cvtps_hf8(__mmask16 __U, __m512 __A) {
+ // CHECK-LABEL: @test_mm512_maskz_cvtps_hf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtps2hf8.512(
+ return _mm512_maskz_cvtps_hf8(__U, __A);
+}
+
+// VCVTPS2HF8S - 128-bit
+
+__m128i test_mm_cvts_ps_hf8(__m128 __A) {
+ // CHECK-LABEL: @test_mm_cvts_ps_hf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtps2hf8s.128(
+ return _mm_cvts_ps_hf8(__A);
+}
+
+__m128i test_mm_mask_cvts_ps_hf8(__m128i __W, __mmask8 __U, __m128 __A) {
+ // CHECK-LABEL: @test_mm_mask_cvts_ps_hf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtps2hf8s.128(
+ return _mm_mask_cvts_ps_hf8(__W, __U, __A);
+}
+
+__m128i test_mm_maskz_cvts_ps_hf8(__mmask8 __U, __m128 __A) {
+ // CHECK-LABEL: @test_mm_maskz_cvts_ps_hf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtps2hf8s.128(
+ return _mm_maskz_cvts_ps_hf8(__U, __A);
+}
+
+// VCVTPS2HF8S - 256-bit
+
+__m128i test_mm256_cvts_ps_hf8(__m256 __A) {
+ // CHECK-LABEL: @test_mm256_cvts_ps_hf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtps2hf8s.256(
+ return _mm256_cvts_ps_hf8(__A);
+}
+
+__m128i test_mm256_mask_cvts_ps_hf8(__m128i __W, __mmask8 __U, __m256 __A) {
+ // CHECK-LABEL: @test_mm256_mask_cvts_ps_hf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtps2hf8s.256(
+ return _mm256_mask_cvts_ps_hf8(__W, __U, __A);
+}
+
+__m128i test_mm256_maskz_cvts_ps_hf8(__mmask8 __U, __m256 __A) {
+ // CHECK-LABEL: @test_mm256_maskz_cvts_ps_hf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtps2hf8s.256(
+ return _mm256_maskz_cvts_ps_hf8(__U, __A);
+}
+
+// VCVTPS2HF8S - 512-bit
+
+__m128i test_mm512_cvts_ps_hf8(__m512 __A) {
+ // CHECK-LABEL: @test_mm512_cvts_ps_hf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtps2hf8s.512(
+ return _mm512_cvts_ps_hf8(__A);
+}
+
+__m128i test_mm512_mask_cvts_ps_hf8(__m128i __W, __mmask16 __U, __m512 __A) {
+ // CHECK-LABEL: @test_mm512_mask_cvts_ps_hf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtps2hf8s.512(
+ return _mm512_mask_cvts_ps_hf8(__W, __U, __A);
+}
+
+__m128i test_mm512_maskz_cvts_ps_hf8(__mmask16 __U, __m512 __A) {
+ // CHECK-LABEL: @test_mm512_maskz_cvts_ps_hf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtps2hf8s.512(
+ return _mm512_maskz_cvts_ps_hf8(__U, __A);
+}
+
+// VCVTROPS2HF8 - 128-bit
+
+__m128i test_mm_cvtrops_hf8(__m128 __A) {
+ // CHECK-LABEL: @test_mm_cvtrops_hf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtrops2hf8.128(
+ return _mm_cvtrops_hf8(__A);
+}
+
+__m128i test_mm_mask_cvtrops_hf8(__m128i __W, __mmask8 __U, __m128 __A) {
+ // CHECK-LABEL: @test_mm_mask_cvtrops_hf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtrops2hf8.128(
+ return _mm_mask_cvtrops_hf8(__W, __U, __A);
+}
+
+__m128i test_mm_maskz_cvtrops_hf8(__mmask8 __U, __m128 __A) {
+ // CHECK-LABEL: @test_mm_maskz_cvtrops_hf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtrops2hf8.128(
+ return _mm_maskz_cvtrops_hf8(__U, __A);
+}
+
+// VCVTROPS2HF8 - 256-bit
+
+__m128i test_mm256_cvtrops_hf8(__m256 __A) {
+ // CHECK-LABEL: @test_mm256_cvtrops_hf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtrops2hf8.256(
+ return _mm256_cvtrops_hf8(__A);
+}
+
+__m128i test_mm256_mask_cvtrops_hf8(__m128i __W, __mmask8 __U, __m256 __A) {
+ // CHECK-LABEL: @test_mm256_mask_cvtrops_hf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtrops2hf8.256(
+ return _mm256_mask_cvtrops_hf8(__W, __U, __A);
+}
+
+__m128i test_mm256_maskz_cvtrops_hf8(__mmask8 __U, __m256 __A) {
+ // CHECK-LABEL: @test_mm256_maskz_cvtrops_hf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtrops2hf8.256(
+ return _mm256_maskz_cvtrops_hf8(__U, __A);
+}
+
+// VCVTROPS2HF8 - 512-bit
+
+__m128i test_mm512_cvtrops_hf8(__m512 __A) {
+ // CHECK-LABEL: @test_mm512_cvtrops_hf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtrops2hf8.512(
+ return _mm512_cvtrops_hf8(__A);
+}
+
+__m128i test_mm512_mask_cvtrops_hf8(__m128i __W, __mmask16 __U, __m512 __A) {
+ // CHECK-LABEL: @test_mm512_mask_cvtrops_hf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtrops2hf8.512(
+ return _mm512_mask_cvtrops_hf8(__W, __U, __A);
+}
+
+__m128i test_mm512_maskz_cvtrops_hf8(__mmask16 __U, __m512 __A) {
+ // CHECK-LABEL: @test_mm512_maskz_cvtrops_hf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtrops2hf8.512(
+ return _mm512_maskz_cvtrops_hf8(__U, __A);
+}
+
+// VCVTROPS2HF8S - 128-bit
+
+__m128i test_mm_cvts_rops_hf8(__m128 __A) {
+ // CHECK-LABEL: @test_mm_cvts_rops_hf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtrops2hf8s.128(
+ return _mm_cvts_rops_hf8(__A);
+}
+
+__m128i test_mm_mask_cvts_rops_hf8(__m128i __W, __mmask8 __U, __m128 __A) {
+ // CHECK-LABEL: @test_mm_mask_cvts_rops_hf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtrops2hf8s.128(
+ return _mm_mask_cvts_rops_hf8(__W, __U, __A);
+}
+
+__m128i test_mm_maskz_cvts_rops_hf8(__mmask8 __U, __m128 __A) {
+ // CHECK-LABEL: @test_mm_maskz_cvts_rops_hf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtrops2hf8s.128(
+ return _mm_maskz_cvts_rops_hf8(__U, __A);
+}
+
+// VCVTROPS2HF8S - 256-bit
+
+__m128i test_mm256_cvts_rops_hf8(__m256 __A) {
+ // CHECK-LABEL: @test_mm256_cvts_rops_hf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtrops2hf8s.256(
+ return _mm256_cvts_rops_hf8(__A);
+}
+
+__m128i test_mm256_mask_cvts_rops_hf8(__m128i __W, __mmask8 __U, __m256 __A) {
+ // CHECK-LABEL: @test_mm256_mask_cvts_rops_hf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtrops2hf8s.256(
+ return _mm256_mask_cvts_rops_hf8(__W, __U, __A);
+}
+
+__m128i test_mm256_maskz_cvts_rops_hf8(__mmask8 __U, __m256 __A) {
+ // CHECK-LABEL: @test_mm256_maskz_cvts_rops_hf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtrops2hf8s.256(
+ return _mm256_maskz_cvts_rops_hf8(__U, __A);
+}
+
+// VCVTROPS2HF8S - 512-bit
+
+__m128i test_mm512_cvts_rops_hf8(__m512 __A) {
+ // CHECK-LABEL: @test_mm512_cvts_rops_hf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtrops2hf8s.512(
+ return _mm512_cvts_rops_hf8(__A);
+}
+
+__m128i test_mm512_mask_cvts_rops_hf8(__m128i __W, __mmask16 __U, __m512 __A) {
+ // CHECK-LABEL: @test_mm512_mask_cvts_rops_hf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtrops2hf8s.512(
+ return _mm512_mask_cvts_rops_hf8(__W, __U, __A);
+}
+
+__m128i test_mm512_maskz_cvts_rops_hf8(__mmask16 __U, __m512 __A) {
+ // CHECK-LABEL: @test_mm512_maskz_cvts_rops_hf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtrops2hf8s.512(
+ return _mm512_maskz_cvts_rops_hf8(__U, __A);
+}
+
+//
+// Group B: VCVTBIASPS2BF8 / VCVTBIASPS2BF8S / VCVTBIASPS2HF8 /
+// VCVTBIASPS2HF8S
+//
+
+// VCVTBIASPS2BF8 - 128-bit
+
+__m128i test_mm_cvtbiasps_bf8(__m128i __A, __m128 __B) {
+ // CHECK-LABEL: @test_mm_cvtbiasps_bf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2bf8.128(
+ return _mm_cvtbiasps_bf8(__A, __B);
+}
+
+__m128i test_mm_mask_cvtbiasps_bf8(__m128i __W, __mmask8 __U, __m128i __A, __m128 __B) {
+ // CHECK-LABEL: @test_mm_mask_cvtbiasps_bf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2bf8.128(
+ return _mm_mask_cvtbiasps_bf8(__W, __U, __A, __B);
+}
+
+__m128i test_mm_maskz_cvtbiasps_bf8(__mmask8 __U, __m128i __A, __m128 __B) {
+ // CHECK-LABEL: @test_mm_maskz_cvtbiasps_bf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2bf8.128(
+ return _mm_maskz_cvtbiasps_bf8(__U, __A, __B);
+}
+
+// VCVTBIASPS2BF8 - 256-bit
+
+__m128i test_mm256_cvtbiasps_bf8(__m256i __A, __m256 __B) {
+ // CHECK-LABEL: @test_mm256_cvtbiasps_bf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2bf8.256(
+ return _mm256_cvtbiasps_bf8(__A, __B);
+}
+
+__m128i test_mm256_mask_cvtbiasps_bf8(__m128i __W, __mmask8 __U, __m256i __A, __m256 __B) {
+ // CHECK-LABEL: @test_mm256_mask_cvtbiasps_bf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2bf8.256(
+ return _mm256_mask_cvtbiasps_bf8(__W, __U, __A, __B);
+}
+
+__m128i test_mm256_maskz_cvtbiasps_bf8(__mmask8 __U, __m256i __A, __m256 __B) {
+ // CHECK-LABEL: @test_mm256_maskz_cvtbiasps_bf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2bf8.256(
+ return _mm256_maskz_cvtbiasps_bf8(__U, __A, __B);
+}
+
+// VCVTBIASPS2BF8 - 512-bit
+
+__m128i test_mm512_cvtbiasps_bf8(__m512i __A, __m512 __B) {
+ // CHECK-LABEL: @test_mm512_cvtbiasps_bf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2bf8.512(
+ return _mm512_cvtbiasps_bf8(__A, __B);
+}
+
+__m128i test_mm512_mask_cvtbiasps_bf8(__m128i __W, __mmask16 __U, __m512i __A, __m512 __B) {
+ // CHECK-LABEL: @test_mm512_mask_cvtbiasps_bf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2bf8.512(
+ return _mm512_mask_cvtbiasps_bf8(__W, __U, __A, __B);
+}
+
+__m128i test_mm512_maskz_cvtbiasps_bf8(__mmask16 __U, __m512i __A, __m512 __B) {
+ // CHECK-LABEL: @test_mm512_maskz_cvtbiasps_bf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2bf8.512(
+ return _mm512_maskz_cvtbiasps_bf8(__U, __A, __B);
+}
+
+// VCVTBIASPS2BF8S - 128-bit
+
+__m128i test_mm_cvts_biasps_bf8(__m128i __A, __m128 __B) {
+ // CHECK-LABEL: @test_mm_cvts_biasps_bf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2bf8s.128(
+ return _mm_cvts_biasps_bf8(__A, __B);
+}
+
+__m128i test_mm_mask_cvts_biasps_bf8(__m128i __W, __mmask8 __U, __m128i __A, __m128 __B) {
+ // CHECK-LABEL: @test_mm_mask_cvts_biasps_bf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2bf8s.128(
+ return _mm_mask_cvts_biasps_bf8(__W, __U, __A, __B);
+}
+
+__m128i test_mm_maskz_cvts_biasps_bf8(__mmask8 __U, __m128i __A, __m128 __B) {
+ // CHECK-LABEL: @test_mm_maskz_cvts_biasps_bf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2bf8s.128(
+ return _mm_maskz_cvts_biasps_bf8(__U, __A, __B);
+}
+
+// VCVTBIASPS2BF8S - 256-bit
+
+__m128i test_mm256_cvts_biasps_bf8(__m256i __A, __m256 __B) {
+ // CHECK-LABEL: @test_mm256_cvts_biasps_bf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2bf8s.256(
+ return _mm256_cvts_biasps_bf8(__A, __B);
+}
+
+__m128i test_mm256_mask_cvts_biasps_bf8(__m128i __W, __mmask8 __U, __m256i __A, __m256 __B) {
+ // CHECK-LABEL: @test_mm256_mask_cvts_biasps_bf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2bf8s.256(
+ return _mm256_mask_cvts_biasps_bf8(__W, __U, __A, __B);
+}
+
+__m128i test_mm256_maskz_cvts_biasps_bf8(__mmask8 __U, __m256i __A, __m256 __B) {
+ // CHECK-LABEL: @test_mm256_maskz_cvts_biasps_bf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2bf8s.256(
+ return _mm256_maskz_cvts_biasps_bf8(__U, __A, __B);
+}
+
+// VCVTBIASPS2BF8S - 512-bit
+
+__m128i test_mm512_cvts_biasps_bf8(__m512i __A, __m512 __B) {
+ // CHECK-LABEL: @test_mm512_cvts_biasps_bf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2bf8s.512(
+ return _mm512_cvts_biasps_bf8(__A, __B);
+}
+
+__m128i test_mm512_mask_cvts_biasps_bf8(__m128i __W, __mmask16 __U, __m512i __A, __m512 __B) {
+ // CHECK-LABEL: @test_mm512_mask_cvts_biasps_bf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2bf8s.512(
+ return _mm512_mask_cvts_biasps_bf8(__W, __U, __A, __B);
+}
+
+__m128i test_mm512_maskz_cvts_biasps_bf8(__mmask16 __U, __m512i __A, __m512 __B) {
+ // CHECK-LABEL: @test_mm512_maskz_cvts_biasps_bf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2bf8s.512(
+ return _mm512_maskz_cvts_biasps_bf8(__U, __A, __B);
+}
+
+// VCVTBIASPS2HF8 - 128-bit
+
+__m128i test_mm_cvtbiasps_hf8(__m128i __A, __m128 __B) {
+ // CHECK-LABEL: @test_mm_cvtbiasps_hf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2hf8.128(
+ return _mm_cvtbiasps_hf8(__A, __B);
+}
+
+__m128i test_mm_mask_cvtbiasps_hf8(__m128i __W, __mmask8 __U, __m128i __A, __m128 __B) {
+ // CHECK-LABEL: @test_mm_mask_cvtbiasps_hf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2hf8.128(
+ return _mm_mask_cvtbiasps_hf8(__W, __U, __A, __B);
+}
+
+__m128i test_mm_maskz_cvtbiasps_hf8(__mmask8 __U, __m128i __A, __m128 __B) {
+ // CHECK-LABEL: @test_mm_maskz_cvtbiasps_hf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2hf8.128(
+ return _mm_maskz_cvtbiasps_hf8(__U, __A, __B);
+}
+
+// VCVTBIASPS2HF8 - 256-bit
+
+__m128i test_mm256_cvtbiasps_hf8(__m256i __A, __m256 __B) {
+ // CHECK-LABEL: @test_mm256_cvtbiasps_hf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2hf8.256(
+ return _mm256_cvtbiasps_hf8(__A, __B);
+}
+
+__m128i test_mm256_mask_cvtbiasps_hf8(__m128i __W, __mmask8 __U, __m256i __A, __m256 __B) {
+ // CHECK-LABEL: @test_mm256_mask_cvtbiasps_hf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2hf8.256(
+ return _mm256_mask_cvtbiasps_hf8(__W, __U, __A, __B);
+}
+
+__m128i test_mm256_maskz_cvtbiasps_hf8(__mmask8 __U, __m256i __A, __m256 __B) {
+ // CHECK-LABEL: @test_mm256_maskz_cvtbiasps_hf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2hf8.256(
+ return _mm256_maskz_cvtbiasps_hf8(__U, __A, __B);
+}
+
+// VCVTBIASPS2HF8 - 512-bit
+
+__m128i test_mm512_cvtbiasps_hf8(__m512i __A, __m512 __B) {
+ // CHECK-LABEL: @test_mm512_cvtbiasps_hf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2hf8.512(
+ return _mm512_cvtbiasps_hf8(__A, __B);
+}
+
+__m128i test_mm512_mask_cvtbiasps_hf8(__m128i __W, __mmask16 __U, __m512i __A, __m512 __B) {
+ // CHECK-LABEL: @test_mm512_mask_cvtbiasps_hf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2hf8.512(
+ return _mm512_mask_cvtbiasps_hf8(__W, __U, __A, __B);
+}
+
+__m128i test_mm512_maskz_cvtbiasps_hf8(__mmask16 __U, __m512i __A, __m512 __B) {
+ // CHECK-LABEL: @test_mm512_maskz_cvtbiasps_hf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2hf8.512(
+ return _mm512_maskz_cvtbiasps_hf8(__U, __A, __B);
+}
+
+// VCVTBIASPS2HF8S - 128-bit
+
+__m128i test_mm_cvts_biasps_hf8(__m128i __A, __m128 __B) {
+ // CHECK-LABEL: @test_mm_cvts_biasps_hf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2hf8s.128(
+ return _mm_cvts_biasps_hf8(__A, __B);
+}
+
+__m128i test_mm_mask_cvts_biasps_hf8(__m128i __W, __mmask8 __U, __m128i __A, __m128 __B) {
+ // CHECK-LABEL: @test_mm_mask_cvts_biasps_hf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2hf8s.128(
+ return _mm_mask_cvts_biasps_hf8(__W, __U, __A, __B);
+}
+
+__m128i test_mm_maskz_cvts_biasps_hf8(__mmask8 __U, __m128i __A, __m128 __B) {
+ // CHECK-LABEL: @test_mm_maskz_cvts_biasps_hf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2hf8s.128(
+ return _mm_maskz_cvts_biasps_hf8(__U, __A, __B);
+}
+
+// VCVTBIASPS2HF8S - 256-bit
+
+__m128i test_mm256_cvts_biasps_hf8(__m256i __A, __m256 __B) {
+ // CHECK-LABEL: @test_mm256_cvts_biasps_hf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2hf8s.256(
+ return _mm256_cvts_biasps_hf8(__A, __B);
+}
+
+__m128i test_mm256_mask_cvts_biasps_hf8(__m128i __W, __mmask8 __U, __m256i __A, __m256 __B) {
+ // CHECK-LABEL: @test_mm256_mask_cvts_biasps_hf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2hf8s.256(
+ return _mm256_mask_cvts_biasps_hf8(__W, __U, __A, __B);
+}
+
+__m128i test_mm256_maskz_cvts_biasps_hf8(__mmask8 __U, __m256i __A, __m256 __B) {
+ // CHECK-LABEL: @test_mm256_maskz_cvts_biasps_hf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2hf8s.256(
+ return _mm256_maskz_cvts_biasps_hf8(__U, __A, __B);
+}
+
+// VCVTBIASPS2HF8S - 512-bit
+
+__m128i test_mm512_cvts_biasps_hf8(__m512i __A, __m512 __B) {
+ // CHECK-LABEL: @test_mm512_cvts_biasps_hf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2hf8s.512(
+ return _mm512_cvts_biasps_hf8(__A, __B);
+}
+
+__m128i test_mm512_mask_cvts_biasps_hf8(__m128i __W, __mmask16 __U, __m512i __A, __m512 __B) {
+ // CHECK-LABEL: @test_mm512_mask_cvts_biasps_hf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2hf8s.512(
+ return _mm512_mask_cvts_biasps_hf8(__W, __U, __A, __B);
+}
+
+__m128i test_mm512_maskz_cvts_biasps_hf8(__mmask16 __U, __m512i __A, __m512 __B) {
+ // CHECK-LABEL: @test_mm512_maskz_cvts_biasps_hf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2hf8s.512(
+ return _mm512_maskz_cvts_biasps_hf8(__U, __A, __B);
+}
+
+//
+// Group C: VCVTBF82PS / VCVTHF82PS
+//
+
+// VCVTBF82PS - 128-bit
+
+__m128 test_mm_cvtbf8_ps(__m128i __A) {
+ // CHECK-LABEL: @test_mm_cvtbf8_ps(
+ // CHECK: call <4 x float> @llvm.x86.avx10.mask.vcvtbf82ps.128(
+ return _mm_cvtbf8_ps(__A);
+}
+
+__m128 test_mm_mask_cvtbf8_ps(__m128 __W, __mmask8 __U, __m128i __A) {
+ // CHECK-LABEL: @test_mm_mask_cvtbf8_ps(
+ // CHECK: call <4 x float> @llvm.x86.avx10.mask.vcvtbf82ps.128(
+ return _mm_mask_cvtbf8_ps(__W, __U, __A);
+}
+
+__m128 test_mm_maskz_cvtbf8_ps(__mmask8 __U, __m128i __A) {
+ // CHECK-LABEL: @test_mm_maskz_cvtbf8_ps(
+ // CHECK: call <4 x float> @llvm.x86.avx10.mask.vcvtbf82ps.128(
+ return _mm_maskz_cvtbf8_ps(__U, __A);
+}
+
+// VCVTBF82PS - 256-bit
+
+__m256 test_mm256_cvtbf8_ps(__m128i __A) {
+ // CHECK-LABEL: @test_mm256_cvtbf8_ps(
+ // CHECK: call <8 x float> @llvm.x86.avx10.mask.vcvtbf82ps.256(
+ return _mm256_cvtbf8_ps(__A);
+}
+
+__m256 test_mm256_mask_cvtbf8_ps(__m256 __W, __mmask8 __U, __m128i __A) {
+ // CHECK-LABEL: @test_mm256_mask_cvtbf8_ps(
+ // CHECK: call <8 x float> @llvm.x86.avx10.mask.vcvtbf82ps.256(
+ return _mm256_mask_cvtbf8_ps(__W, __U, __A);
+}
+
+__m256 test_mm256_maskz_cvtbf8_ps(__mmask8 __U, __m128i __A) {
+ // CHECK-LABEL: @test_mm256_maskz_cvtbf8_ps(
+ // CHECK: call <8 x float> @llvm.x86.avx10.mask.vcvtbf82ps.256(
+ return _mm256_maskz_cvtbf8_ps(__U, __A);
+}
+
+// VCVTBF82PS - 512-bit
+
+__m512 test_mm512_cvtbf8_ps(__m128i __A) {
+ // CHECK-LABEL: @test_mm512_cvtbf8_ps(
+ // CHECK: call <16 x float> @llvm.x86.avx10.mask.vcvtbf82ps.512(
+ return _mm512_cvtbf8_ps(__A);
+}
+
+__m512 test_mm512_mask_cvtbf8_ps(__m512 __W, __mmask16 __U, __m128i __A) {
+ // CHECK-LABEL: @test_mm512_mask_cvtbf8_ps(
+ // CHECK: call <16 x float> @llvm.x86.avx10.mask.vcvtbf82ps.512(
+ return _mm512_mask_cvtbf8_ps(__W, __U, __A);
+}
+
+__m512 test_mm512_maskz_cvtbf8_ps(__mmask16 __U, __m128i __A) {
+ // CHECK-LABEL: @test_mm512_maskz_cvtbf8_ps(
+ // CHECK: call <16 x float> @llvm.x86.avx10.mask.vcvtbf82ps.512(
+ return _mm512_maskz_cvtbf8_ps(__U, __A);
+}
+
+// VCVTHF82PS - 128-bit
+
+__m128 test_mm_cvthf8_ps(__m128i __A) {
+ // CHECK-LABEL: @test_mm_cvthf8_ps(
+ // CHECK: call <4 x float> @llvm.x86.avx10.mask.vcvthf82ps.128(
+ return _mm_cvthf8_ps(__A);
+}
+
+__m128 test_mm_mask_cvthf8_ps(__m128 __W, __mmask8 __U, __m128i __A) {
+ // CHECK-LABEL: @test_mm_mask_cvthf8_ps(
+ // CHECK: call <4 x float> @llvm.x86.avx10.mask.vcvthf82ps.128(
+ return _mm_mask_cvthf8_ps(__W, __U, __A);
+}
+
+__m128 test_mm_maskz_cvthf8_ps(__mmask8 __U, __m128i __A) {
+ // CHECK-LABEL: @test_mm_maskz_cvthf8_ps(
+ // CHECK: call <4 x float> @llvm.x86.avx10.mask.vcvthf82ps.128(
+ return _mm_maskz_cvthf8_ps(__U, __A);
+}
+
+// VCVTHF82PS - 256-bit
+
+__m256 test_mm256_cvthf8_ps(__m128i __A) {
+ // CHECK-LABEL: @test_mm256_cvthf8_ps(
+ // CHECK: call <8 x float> @llvm.x86.avx10.mask.vcvthf82ps.256(
+ return _mm256_cvthf8_ps(__A);
+}
+
+__m256 test_mm256_mask_cvthf8_ps(__m256 __W, __mmask8 __U, __m128i __A) {
+ // CHECK-LABEL: @test_mm256_mask_cvthf8_ps(
+ // CHECK: call <8 x float> @llvm.x86.avx10.mask.vcvthf82ps.256(
+ return _mm256_mask_cvthf8_ps(__W, __U, __A);
+}
+
+__m256 test_mm256_maskz_cvthf8_ps(__mmask8 __U, __m128i __A) {
+ // CHECK-LABEL: @test_mm256_maskz_cvthf8_ps(
+ // CHECK: call <8 x float> @llvm.x86.avx10.mask.vcvthf82ps.256(
+ return _mm256_maskz_cvthf8_ps(__U, __A);
+}
+
+// VCVTHF82PS - 512-bit
+
+__m512 test_mm512_cvthf8_ps(__m128i __A) {
+ // CHECK-LABEL: @test_mm512_cvthf8_ps(
+ // CHECK: call <16 x float> @llvm.x86.avx10.mask.vcvthf82ps.512(
+ return _mm512_cvthf8_ps(__A);
+}
+
+__m512 test_mm512_mask_cvthf8_ps(__m512 __W, __mmask16 __U, __m128i __A) {
+ // CHECK-LABEL: @test_mm512_mask_cvthf8_ps(
+ // CHECK: call <16 x float> @llvm.x86.avx10.mask.vcvthf82ps.512(
+ return _mm512_mask_cvthf8_ps(__W, __U, __A);
+}
+
+__m512 test_mm512_maskz_cvthf8_ps(__mmask16 __U, __m128i __A) {
+ // CHECK-LABEL: @test_mm512_maskz_cvthf8_ps(
+ // CHECK: call <16 x float> @llvm.x86.avx10.mask.vcvthf82ps.512(
+ return _mm512_maskz_cvthf8_ps(__U, __A);
+}
+
+//
+// Group E: VCVTBF82BF6S / VCVTHF82HF6S
+//
+
+// VCVTBF82BF6S
+
+__m128i test_mm_cvtbf8_bf6s(__m128i __A) {
+ // CHECK-LABEL: @test_mm_cvtbf8_bf6s(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.vcvtbf82bf6s.128(
+ return _mm_cvtbf8_bf6s(__A);
+}
+
+__m256i test_mm256_cvtbf8_bf6s(__m256i __A) {
+ // CHECK-LABEL: @test_mm256_cvtbf8_bf6s(
+ // CHECK: call <32 x i8> @llvm.x86.avx10.vcvtbf82bf6s.256(
+ return _mm256_cvtbf8_bf6s(__A);
+}
+
+__m512i test_mm512_cvtbf8_bf6s(__m512i __A) {
+ // CHECK-LABEL: @test_mm512_cvtbf8_bf6s(
+ // CHECK: call <64 x i8> @llvm.x86.avx10.vcvtbf82bf6s.512(
+ return _mm512_cvtbf8_bf6s(__A);
+}
+
+// VCVTHF82HF6S
+
+__m128i test_mm_cvthf8_hf6s(__m128i __A) {
+ // CHECK-LABEL: @test_mm_cvthf8_hf6s(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.vcvthf82hf6s.128(
+ return _mm_cvthf8_hf6s(__A);
+}
+
+__m256i test_mm256_cvthf8_hf6s(__m256i __A) {
+ // CHECK-LABEL: @test_mm256_cvthf8_hf6s(
+ // CHECK: call <32 x i8> @llvm.x86.avx10.vcvthf82hf6s.256(
+ return _mm256_cvthf8_hf6s(__A);
+}
+
+__m512i test_mm512_cvthf8_hf6s(__m512i __A) {
+ // CHECK-LABEL: @test_mm512_cvthf8_hf6s(
+ // CHECK: call <64 x i8> @llvm.x86.avx10.vcvthf82hf6s.512(
+ return _mm512_cvthf8_hf6s(__A);
+}
+
+//
+// Group F: VCVTBF42HF8 / VCVTBF62HF8 / VCVTHF62HF8
+//
+
+// VCVTBF42HF8 - 128-bit
+
+__m128i test_mm_cvtbf4_hf8(__m128i __A) {
+ // CHECK-LABEL: @test_mm_cvtbf4_hf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.vcvtbf42hf8.128(
+ return _mm_cvtbf4_hf8(__A);
+}
+
+__m128i test_mm_mask_cvtbf4_hf8(__m128i __W, __mmask16 __U, __m128i __A) {
+ // CHECK-LABEL: @test_mm_mask_cvtbf4_hf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.vcvtbf42hf8.128(
+ // CHECK: select <16 x i1>
+ return _mm_mask_cvtbf4_hf8(__W, __U, __A);
+}
+
+__m128i test_mm_maskz_cvtbf4_hf8(__mmask16 __U, __m128i __A) {
+ // CHECK-LABEL: @test_mm_maskz_cvtbf4_hf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.vcvtbf42hf8.128(
+ // CHECK: select <16 x i1>
+ return _mm_maskz_cvtbf4_hf8(__U, __A);
+}
+
+// VCVTBF42HF8 - 256-bit
+
+__m256i test_mm256_cvtbf4_hf8(__m128i __A) {
+ // CHECK-LABEL: @test_mm256_cvtbf4_hf8(
+ // CHECK: call <32 x i8> @llvm.x86.avx10.vcvtbf42hf8.256(
+ return _mm256_cvtbf4_hf8(__A);
+}
+
+__m256i test_mm256_mask_cvtbf4_hf8(__m256i __W, __mmask32 __U, __m128i __A) {
+ // CHECK-LABEL: @test_mm256_mask_cvtbf4_hf8(
+ // CHECK: call <32 x i8> @llvm.x86.avx10.vcvtbf42hf8.256(
+ // CHECK: select <32 x i1>
+ return _mm256_mask_cvtbf4_hf8(__W, __U, __A);
+}
+
+__m256i test_mm256_maskz_cvtbf4_hf8(__mmask32 __U, __m128i __A) {
+ // CHECK-LABEL: @test_mm256_maskz_cvtbf4_hf8(
+ // CHECK: call <32 x i8> @llvm.x86.avx10.vcvtbf42hf8.256(
+ // CHECK: select <32 x i1>
+ return _mm256_maskz_cvtbf4_hf8(__U, __A);
+}
+
+// VCVTBF42HF8 - 512-bit
+
+__m512i test_mm512_cvtbf4_hf8(__m256i __A) {
+ // CHECK-LABEL: @test_mm512_cvtbf4_hf8(
+ // CHECK: call <64 x i8> @llvm.x86.avx10.vcvtbf42hf8.512(
+ return _mm512_cvtbf4_hf8(__A);
+}
+
+__m512i test_mm512_mask_cvtbf4_hf8(__m512i __W, __mmask64 __U, __m256i __A) {
+ // CHECK-LABEL: @test_mm512_mask_cvtbf4_hf8(
+ // CHECK: call <64 x i8> @llvm.x86.avx10.vcvtbf42hf8.512(
+ // CHECK: select <64 x i1>
+ return _mm512_mask_cvtbf4_hf8(__W, __U, __A);
+}
+
+__m512i test_mm512_maskz_cvtbf4_hf8(__mmask64 __U, __m256i __A) {
+ // CHECK-LABEL: @test_mm512_maskz_cvtbf4_hf8(
+ // CHECK: call <64 x i8> @llvm.x86.avx10.vcvtbf42hf8.512(
+ // CHECK: select <64 x i1>
+ return _mm512_maskz_cvtbf4_hf8(__U, __A);
+}
+
+// VCVTBF62HF8 - 128-bit
+
+__m128i test_mm_cvtbf6_hf8(__m128i __A) {
+ // CHECK-LABEL: @test_mm_cvtbf6_hf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.vcvtbf62hf8.128(
+ return _mm_cvtbf6_hf8(__A);
+}
+
+__m128i test_mm_mask_cvtbf6_hf8(__m128i __W, __mmask16 __U, __m128i __A) {
+ // CHECK-LABEL: @test_mm_mask_cvtbf6_hf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.vcvtbf62hf8.128(
+ // CHECK: select <16 x i1>
+ return _mm_mask_cvtbf6_hf8(__W, __U, __A);
+}
+
+__m128i test_mm_maskz_cvtbf6_hf8(__mmask16 __U, __m128i __A) {
+ // CHECK-LABEL: @test_mm_maskz_cvtbf6_hf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.vcvtbf62hf8.128(
+ // CHECK: select <16 x i1>
+ return _mm_maskz_cvtbf6_hf8(__U, __A);
+}
+
+// VCVTBF62HF8 - 256-bit
+
+__m256i test_mm256_cvtbf6_hf8(__m256i __A) {
+ // CHECK-LABEL: @test_mm256_cvtbf6_hf8(
+ // CHECK: call <32 x i8> @llvm.x86.avx10.vcvtbf62hf8.256(
+ return _mm256_cvtbf6_hf8(__A);
+}
+
+__m256i test_mm256_mask_cvtbf6_hf8(__m256i __W, __mmask32 __U, __m256i __A) {
+ // CHECK-LABEL: @test_mm256_mask_cvtbf6_hf8(
+ // CHECK: call <32 x i8> @llvm.x86.avx10.vcvtbf62hf8.256(
+ // CHECK: select <32 x i1>
+ return _mm256_mask_cvtbf6_hf8(__W, __U, __A);
+}
+
+__m256i test_mm256_maskz_cvtbf6_hf8(__mmask32 __U, __m256i __A) {
+ // CHECK-LABEL: @test_mm256_maskz_cvtbf6_hf8(
+ // CHECK: call <32 x i8> @llvm.x86.avx10.vcvtbf62hf8.256(
+ // CHECK: select <32 x i1>
+ return _mm256_maskz_cvtbf6_hf8(__U, __A);
+}
+
+// VCVTBF62HF8 - 512-bit
+
+__m512i test_mm512_cvtbf6_hf8(__m512i __A) {
+ // CHECK-LABEL: @test_mm512_cvtbf6_hf8(
+ // CHECK: call <64 x i8> @llvm.x86.avx10.vcvtbf62hf8.512(
+ return _mm512_cvtbf6_hf8(__A);
+}
+
+__m512i test_mm512_mask_cvtbf6_hf8(__m512i __W, __mmask64 __U, __m512i __A) {
+ // CHECK-LABEL: @test_mm512_mask_cvtbf6_hf8(
+ // CHECK: call <64 x i8> @llvm.x86.avx10.vcvtbf62hf8.512(
+ // CHECK: select <64 x i1>
+ return _mm512_mask_cvtbf6_hf8(__W, __U, __A);
+}
+
+__m512i test_mm512_maskz_cvtbf6_hf8(__mmask64 __U, __m512i __A) {
+ // CHECK-LABEL: @test_mm512_maskz_cvtbf6_hf8(
+ // CHECK: call <64 x i8> @llvm.x86.avx10.vcvtbf62hf8.512(
+ // CHECK: select <64 x i1>
+ return _mm512_maskz_cvtbf6_hf8(__U, __A);
+}
+
+// VCVTHF62HF8 - 128-bit
+
+__m128i test_mm_cvthf6_hf8(__m128i __A) {
+ // CHECK-LABEL: @test_mm_cvthf6_hf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.vcvthf62hf8.128(
+ return _mm_cvthf6_hf8(__A);
+}
+
+__m128i test_mm_mask_cvthf6_hf8(__m128i __W, __mmask16 __U, __m128i __A) {
+ // CHECK-LABEL: @test_mm_mask_cvthf6_hf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.vcvthf62hf8.128(
+ // CHECK: select <16 x i1>
+ return _mm_mask_cvthf6_hf8(__W, __U, __A);
+}
+
+__m128i test_mm_maskz_cvthf6_hf8(__mmask16 __U, __m128i __A) {
+ // CHECK-LABEL: @test_mm_maskz_cvthf6_hf8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.vcvthf62hf8.128(
+ // CHECK: select <16 x i1>
+ return _mm_maskz_cvthf6_hf8(__U, __A);
+}
+
+// VCVTHF62HF8 - 256-bit
+
+__m256i test_mm256_cvthf6_hf8(__m256i __A) {
+ // CHECK-LABEL: @test_mm256_cvthf6_hf8(
+ // CHECK: call <32 x i8> @llvm.x86.avx10.vcvthf62hf8.256(
+ return _mm256_cvthf6_hf8(__A);
+}
+
+__m256i test_mm256_mask_cvthf6_hf8(__m256i __W, __mmask32 __U, __m256i __A) {
+ // CHECK-LABEL: @test_mm256_mask_cvthf6_hf8(
+ // CHECK: call <32 x i8> @llvm.x86.avx10.vcvthf62hf8.256(
+ // CHECK: select <32 x i1>
+ return _mm256_mask_cvthf6_hf8(__W, __U, __A);
+}
+
+__m256i test_mm256_maskz_cvthf6_hf8(__mmask32 __U, __m256i __A) {
+ // CHECK-LABEL: @test_mm256_maskz_cvthf6_hf8(
+ // CHECK: call <32 x i8> @llvm.x86.avx10.vcvthf62hf8.256(
+ // CHECK: select <32 x i1>
+ return _mm256_maskz_cvthf6_hf8(__U, __A);
+}
+
+// VCVTHF62HF8 - 512-bit
+
+__m512i test_mm512_cvthf6_hf8(__m512i __A) {
+ // CHECK-LABEL: @test_mm512_cvthf6_hf8(
+ // CHECK: call <64 x i8> @llvm.x86.avx10.vcvthf62hf8.512(
+ return _mm512_cvthf6_hf8(__A);
+}
+
+__m512i test_mm512_mask_cvthf6_hf8(__m512i __W, __mmask64 __U, __m512i __A) {
+ // CHECK-LABEL: @test_mm512_mask_cvthf6_hf8(
+ // CHECK: call <64 x i8> @llvm.x86.avx10.vcvthf62hf8.512(
+ // CHECK: select <64 x i1>
+ return _mm512_mask_cvthf6_hf8(__W, __U, __A);
+}
+
+__m512i test_mm512_maskz_cvthf6_hf8(__mmask64 __U, __m512i __A) {
+ // CHECK-LABEL: @test_mm512_maskz_cvthf6_hf8(
+ // CHECK: call <64 x i8> @llvm.x86.avx10.vcvthf62hf8.512(
+ // CHECK: select <64 x i1>
+ return _mm512_maskz_cvthf6_hf8(__U, __A);
+}
+
+//
+// Group H: VUNPACKB
+//
+
+// VUNPACKB - 128-bit
+
+__m128i test_mm_unpackb_epi8(__m128i __A) {
+ // CHECK-LABEL: @test_mm_unpackb_epi8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.vunpackb.128(
+ return _mm_unpackb_epi8(__A, 1);
+}
+
+__m128i test_mm_mask_unpackb_epi8(__m128i __W, __mmask16 __U, __m128i __A) {
+ // CHECK-LABEL: @test_mm_mask_unpackb_epi8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.vunpackb.128(
+ // CHECK: select <16 x i1>
+ return _mm_mask_unpackb_epi8(__W, __U, __A, 1);
+}
+
+__m128i test_mm_maskz_unpackb_epi8(__mmask16 __U, __m128i __A) {
+ // CHECK-LABEL: @test_mm_maskz_unpackb_epi8(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.vunpackb.128(
+ // CHECK: select <16 x i1>
+ return _mm_maskz_unpackb_epi8(__U, __A, 1);
+}
+
+// VUNPACKB - 256-bit
+
+__m256i test_mm256_unpackb_epi8(__m256i __A) {
+ // CHECK-LABEL: @test_mm256_unpackb_epi8(
+ // CHECK: call <32 x i8> @llvm.x86.avx10.vunpackb.256(
+ return _mm256_unpackb_epi8(__A, 2);
+}
+
+__m256i test_mm256_mask_unpackb_epi8(__m256i __W, __mmask32 __U, __m256i __A) {
+ // CHECK-LABEL: @test_mm256_mask_unpackb_epi8(
+ // CHECK: call <32 x i8> @llvm.x86.avx10.vunpackb.256(
+ // CHECK: select <32 x i1>
+ return _mm256_mask_unpackb_epi8(__W, __U, __A, 2);
+}
+
+__m256i test_mm256_maskz_unpackb_epi8(__mmask32 __U, __m256i __A) {
+ // CHECK-LABEL: @test_mm256_maskz_unpackb_epi8(
+ // CHECK: call <32 x i8> @llvm.x86.avx10.vunpackb.256(
+ // CHECK: select <32 x i1>
+ return _mm256_maskz_unpackb_epi8(__U, __A, 2);
+}
+
+// VUNPACKB - 512-bit
+
+__m512i test_mm512_unpackb_epi8(__m512i __A) {
+ // CHECK-LABEL: @test_mm512_unpackb_epi8(
+ // CHECK: call <64 x i8> @llvm.x86.avx10.vunpackb.512(
+ return _mm512_unpackb_epi8(__A, 3);
+}
+
+__m512i test_mm512_mask_unpackb_epi8(__m512i __W, __mmask64 __U, __m512i __A) {
+ // CHECK-LABEL: @test_mm512_mask_unpackb_epi8(
+ // CHECK: call <64 x i8> @llvm.x86.avx10.vunpackb.512(
+ // CHECK: select <64 x i1>
+ return _mm512_mask_unpackb_epi8(__W, __U, __A, 3);
+}
+
+__m512i test_mm512_maskz_unpackb_epi8(__mmask64 __U, __m512i __A) {
+ // CHECK-LABEL: @test_mm512_maskz_unpackb_epi8(
+ // CHECK: call <64 x i8> @llvm.x86.avx10.vunpackb.512(
+ // CHECK: select <64 x i1>
+ return _mm512_maskz_unpackb_epi8(__U, __A, 3);
+}
diff --git a/clang/test/CodeGen/attr-target-x86.c b/clang/test/CodeGen/attr-target-x86.c
index 474fa93629d89..3105517711e5e 100644
--- a/clang/test/CodeGen/attr-target-x86.c
+++ b/clang/test/CodeGen/attr-target-x86.c
@@ -33,7 +33,7 @@ __attribute__((target("fpmath=387")))
void f_fpmath_387(void) {}
// CHECK-NOT: tune-cpu
-// CHECK: [[f_no_sse2]] = {{.*}}"target-cpu"="i686" "target-features"="+cmov,+cx8,+x87,-aes,-amx-avx512,-avx,-avx10.1,-avx10.2,-avx2,-avx512bf16,-avx512bitalg,-avx512bw,-avx512cd,-avx512dq,-avx512f,-avx512fp16,-avx512ifma,-avx512vbmi,-avx512vbmi2,-avx512vl,-avx512vnni,-avx512vp2intersect,-avx512vpopcntdq,-avxifma,-avxneconvert,-avxvnni,-avxvnniint16,-avxvnniint8,-f16c,-fma,-fma4,-gfni,-kl,-pclmul,-sha,-sha512,-sm3,-sm4,-sse2,-sse3,-sse4.1,-sse4.2,-sse4a,-ssse3,-vaes,-vpclmulqdq,-widekl,-xop" "tune-cpu"="i686"
+// CHECK: [[f_no_sse2]] = {{.*}}"target-cpu"="i686" "target-features"="+cmov,+cx8,+x87,-aes,-amx-avx512,-avx,-avx10-v2-aux,-avx10.1,-avx10.2,-avx2,-avx512bf16,-avx512bitalg,-avx512bw,-avx512cd,-avx512dq,-avx512f,-avx512fp16,-avx512ifma,-avx512vbmi,-avx512vbmi2,-avx512vl,-avx512vnni,-avx512vp2intersect,-avx512vpopcntdq,-avxifma,-avxneconvert,-avxvnni,-avxvnniint16,-avxvnniint8,-f16c,-fma,-fma4,-gfni,-kl,-pclmul,-sha,-sha512,-sm3,-sm4,-sse2,-sse3,-sse4.1,-sse4.2,-sse4a,-ssse3,-vaes,-vpclmulqdq,-widekl,-xop" "tune-cpu"="i686"
__attribute__((target("no-sse2")))
void f_no_sse2(void) {}
@@ -41,7 +41,7 @@ void f_no_sse2(void) {}
__attribute__((target("sse4")))
void f_sse4(void) {}
-// CHECK: [[f_no_sse4]] = {{.*}}"target-cpu"="i686" "target-features"="+cmov,+cx8,+x87,-amx-avx512,-avx,-avx10.1,-avx10.2,-avx2,-avx512bf16,-avx512bitalg,-avx512bw,-avx512cd,-avx512dq,-avx512f,-avx512fp16,-avx512ifma,-avx512vbmi,-avx512vbmi2,-avx512vl,-avx512vnni,-avx512vp2intersect,-avx512vpopcntdq,-avxifma,-avxneconvert,-avxvnni,-avxvnniint16,-avxvnniint8,-f16c,-fma,-fma4,-sha512,-sm3,-sm4,-sse4.1,-sse4.2,-vaes,-vpclmulqdq,-xop" "tune-cpu"="i686"
+// CHECK: [[f_no_sse4]] = {{.*}}"target-cpu"="i686" "target-features"="+cmov,+cx8,+x87,-amx-avx512,-avx,-avx10-v2-aux,-avx10.1,-avx10.2,-avx2,-avx512bf16,-avx512bitalg,-avx512bw,-avx512cd,-avx512dq,-avx512f,-avx512fp16,-avx512ifma,-avx512vbmi,-avx512vbmi2,-avx512vl,-avx512vnni,-avx512vp2intersect,-avx512vpopcntdq,-avxifma,-avxneconvert,-avxvnni,-avxvnniint16,-avxvnniint8,-f16c,-fma,-fma4,-sha512,-sm3,-sm4,-sse4.1,-sse4.2,-vaes,-vpclmulqdq,-xop" "tune-cpu"="i686"
__attribute__((target("no-sse4")))
void f_no_sse4(void) {}
diff --git a/llvm/include/llvm/IR/IntrinsicsX86.td b/llvm/include/llvm/IR/IntrinsicsX86.td
index 5c7785731111c..b0bbd6f35359e 100644
--- a/llvm/include/llvm/IR/IntrinsicsX86.td
+++ b/llvm/include/llvm/IR/IntrinsicsX86.td
@@ -7022,6 +7022,203 @@ def int_x86_avx10_mask_vcvtph2hf8s512 : ClangBuiltin<"__builtin_ia32_vcvtph2hf8s
[IntrNoMem]>;
}
+// AVX10 V2 AUX - Convert instructions
+let TargetPrefix = "x86" in {
+// Group A: PS(f32) -> i8 truncating conversions (quarter-size: output always v16i8)
+
+// VCVTPS2BF8
+def int_x86_avx10_mask_vcvtps2bf8_128 : ClangBuiltin<"__builtin_ia32_vcvtps2bf8_128_mask">,
+ DefaultAttrsIntrinsic<[llvm_v16i8_ty], [llvm_v4f32_ty, llvm_v16i8_ty, llvm_i8_ty],
+ [IntrNoMem]>;
+def int_x86_avx10_mask_vcvtps2bf8_256 : ClangBuiltin<"__builtin_ia32_vcvtps2bf8_256_mask">,
+ DefaultAttrsIntrinsic<[llvm_v16i8_ty], [llvm_v8f32_ty, llvm_v16i8_ty, llvm_i8_ty],
+ [IntrNoMem]>;
+def int_x86_avx10_mask_vcvtps2bf8_512 : ClangBuiltin<"__builtin_ia32_vcvtps2bf8_512_mask">,
+ DefaultAttrsIntrinsic<[llvm_v16i8_ty], [llvm_v16f32_ty, llvm_v16i8_ty, llvm_i16_ty],
+ [IntrNoMem]>;
+
+// VCVTPS2BF8S
+def int_x86_avx10_mask_vcvtps2bf8s_128 : ClangBuiltin<"__builtin_ia32_vcvtps2bf8s_128_mask">,
+ DefaultAttrsIntrinsic<[llvm_v16i8_ty], [llvm_v4f32_ty, llvm_v16i8_ty, llvm_i8_ty],
+ [IntrNoMem]>;
+def int_x86_avx10_mask_vcvtps2bf8s_256 : ClangBuiltin<"__builtin_ia32_vcvtps2bf8s_256_mask">,
+ DefaultAttrsIntrinsic<[llvm_v16i8_ty], [llvm_v8f32_ty, llvm_v16i8_ty, llvm_i8_ty],
+ [IntrNoMem]>;
+def int_x86_avx10_mask_vcvtps2bf8s_512 : ClangBuiltin<"__builtin_ia32_vcvtps2bf8s_512_mask">,
+ DefaultAttrsIntrinsic<[llvm_v16i8_ty], [llvm_v16f32_ty, llvm_v16i8_ty, llvm_i16_ty],
+ [IntrNoMem]>;
+
+// VCVTPS2HF8
+def int_x86_avx10_mask_vcvtps2hf8_128 : ClangBuiltin<"__builtin_ia32_vcvtps2hf8_128_mask">,
+ DefaultAttrsIntrinsic<[llvm_v16i8_ty], [llvm_v4f32_ty, llvm_v16i8_ty, llvm_i8_ty],
+ [IntrNoMem]>;
+def int_x86_avx10_mask_vcvtps2hf8_256 : ClangBuiltin<"__builtin_ia32_vcvtps2hf8_256_mask">,
+ DefaultAttrsIntrinsic<[llvm_v16i8_ty], [llvm_v8f32_ty, llvm_v16i8_ty, llvm_i8_ty],
+ [IntrNoMem]>;
+def int_x86_avx10_mask_vcvtps2hf8_512 : ClangBuiltin<"__builtin_ia32_vcvtps2hf8_512_mask">,
+ DefaultAttrsIntrinsic<[llvm_v16i8_ty], [llvm_v16f32_ty, llvm_v16i8_ty, llvm_i16_ty],
+ [IntrNoMem]>;
+
+// VCVTPS2HF8S
+def int_x86_avx10_mask_vcvtps2hf8s_128 : ClangBuiltin<"__builtin_ia32_vcvtps2hf8s_128_mask">,
+ DefaultAttrsIntrinsic<[llvm_v16i8_ty], [llvm_v4f32_ty, llvm_v16i8_ty, llvm_i8_ty],
+ [IntrNoMem]>;
+def int_x86_avx10_mask_vcvtps2hf8s_256 : ClangBuiltin<"__builtin_ia32_vcvtps2hf8s_256_mask">,
+ DefaultAttrsIntrinsic<[llvm_v16i8_ty], [llvm_v8f32_ty, llvm_v16i8_ty, llvm_i8_ty],
+ [IntrNoMem]>;
+def int_x86_avx10_mask_vcvtps2hf8s_512 : ClangBuiltin<"__builtin_ia32_vcvtps2hf8s_512_mask">,
+ DefaultAttrsIntrinsic<[llvm_v16i8_ty], [llvm_v16f32_ty, llvm_v16i8_ty, llvm_i16_ty],
+ [IntrNoMem]>;
+
+// VCVTROPS2HF8
+def int_x86_avx10_mask_vcvtrops2hf8_128 : ClangBuiltin<"__builtin_ia32_vcvtrops2hf8_128_mask">,
+ DefaultAttrsIntrinsic<[llvm_v16i8_ty], [llvm_v4f32_ty, llvm_v16i8_ty, llvm_i8_ty],
+ [IntrNoMem]>;
+def int_x86_avx10_mask_vcvtrops2hf8_256 : ClangBuiltin<"__builtin_ia32_vcvtrops2hf8_256_mask">,
+ DefaultAttrsIntrinsic<[llvm_v16i8_ty], [llvm_v8f32_ty, llvm_v16i8_ty, llvm_i8_ty],
+ [IntrNoMem]>;
+def int_x86_avx10_mask_vcvtrops2hf8_512 : ClangBuiltin<"__builtin_ia32_vcvtrops2hf8_512_mask">,
+ DefaultAttrsIntrinsic<[llvm_v16i8_ty], [llvm_v16f32_ty, llvm_v16i8_ty, llvm_i16_ty],
+ [IntrNoMem]>;
+
+// VCVTROPS2HF8S
+def int_x86_avx10_mask_vcvtrops2hf8s_128 : ClangBuiltin<"__builtin_ia32_vcvtrops2hf8s_128_mask">,
+ DefaultAttrsIntrinsic<[llvm_v16i8_ty], [llvm_v4f32_ty, llvm_v16i8_ty, llvm_i8_ty],
+ [IntrNoMem]>;
+def int_x86_avx10_mask_vcvtrops2hf8s_256 : ClangBuiltin<"__builtin_ia32_vcvtrops2hf8s_256_mask">,
+ DefaultAttrsIntrinsic<[llvm_v16i8_ty], [llvm_v8f32_ty, llvm_v16i8_ty, llvm_i8_ty],
+ [IntrNoMem]>;
+def int_x86_avx10_mask_vcvtrops2hf8s_512 : ClangBuiltin<"__builtin_ia32_vcvtrops2hf8s_512_mask">,
+ DefaultAttrsIntrinsic<[llvm_v16i8_ty], [llvm_v16f32_ty, llvm_v16i8_ty, llvm_i16_ty],
+ [IntrNoMem]>;
+
+// Group B: Bias PS -> i8 conversions (3-operand: bias + f32 source -> i8 dest)
+
+// VCVTBIASPS2BF8
+def int_x86_avx10_mask_vcvtbiasps2bf8_128 : ClangBuiltin<"__builtin_ia32_vcvtbiasps2bf8_128_mask">,
+ DefaultAttrsIntrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v4f32_ty, llvm_v16i8_ty, llvm_i8_ty],
+ [IntrNoMem]>;
+def int_x86_avx10_mask_vcvtbiasps2bf8_256 : ClangBuiltin<"__builtin_ia32_vcvtbiasps2bf8_256_mask">,
+ DefaultAttrsIntrinsic<[llvm_v16i8_ty], [llvm_v32i8_ty, llvm_v8f32_ty, llvm_v16i8_ty, llvm_i8_ty],
+ [IntrNoMem]>;
+def int_x86_avx10_mask_vcvtbiasps2bf8_512 : ClangBuiltin<"__builtin_ia32_vcvtbiasps2bf8_512_mask">,
+ DefaultAttrsIntrinsic<[llvm_v16i8_ty], [llvm_v64i8_ty, llvm_v16f32_ty, llvm_v16i8_ty, llvm_i16_ty],
+ [IntrNoMem]>;
+
+// VCVTBIASPS2BF8S
+def int_x86_avx10_mask_vcvtbiasps2bf8s_128 : ClangBuiltin<"__builtin_ia32_vcvtbiasps2bf8s_128_mask">,
+ DefaultAttrsIntrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v4f32_ty, llvm_v16i8_ty, llvm_i8_ty],
+ [IntrNoMem]>;
+def int_x86_avx10_mask_vcvtbiasps2bf8s_256 : ClangBuiltin<"__builtin_ia32_vcvtbiasps2bf8s_256_mask">,
+ DefaultAttrsIntrinsic<[llvm_v16i8_ty], [llvm_v32i8_ty, llvm_v8f32_ty, llvm_v16i8_ty, llvm_i8_ty],
+ [IntrNoMem]>;
+def int_x86_avx10_mask_vcvtbiasps2bf8s_512 : ClangBuiltin<"__builtin_ia32_vcvtbiasps2bf8s_512_mask">,
+ DefaultAttrsIntrinsic<[llvm_v16i8_ty], [llvm_v64i8_ty, llvm_v16f32_ty, llvm_v16i8_ty, llvm_i16_ty],
+ [IntrNoMem]>;
+
+// VCVTBIASPS2HF8
+def int_x86_avx10_mask_vcvtbiasps2hf8_128 : ClangBuiltin<"__builtin_ia32_vcvtbiasps2hf8_128_mask">,
+ DefaultAttrsIntrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v4f32_ty, llvm_v16i8_ty, llvm_i8_ty],
+ [IntrNoMem]>;
+def int_x86_avx10_mask_vcvtbiasps2hf8_256 : ClangBuiltin<"__builtin_ia32_vcvtbiasps2hf8_256_mask">,
+ DefaultAttrsIntrinsic<[llvm_v16i8_ty], [llvm_v32i8_ty, llvm_v8f32_ty, llvm_v16i8_ty, llvm_i8_ty],
+ [IntrNoMem]>;
+def int_x86_avx10_mask_vcvtbiasps2hf8_512 : ClangBuiltin<"__builtin_ia32_vcvtbiasps2hf8_512_mask">,
+ DefaultAttrsIntrinsic<[llvm_v16i8_ty], [llvm_v64i8_ty, llvm_v16f32_ty, llvm_v16i8_ty, llvm_i16_ty],
+ [IntrNoMem]>;
+
+// VCVTBIASPS2HF8S
+def int_x86_avx10_mask_vcvtbiasps2hf8s_128 : ClangBuiltin<"__builtin_ia32_vcvtbiasps2hf8s_128_mask">,
+ DefaultAttrsIntrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v4f32_ty, llvm_v16i8_ty, llvm_i8_ty],
+ [IntrNoMem]>;
+def int_x86_avx10_mask_vcvtbiasps2hf8s_256 : ClangBuiltin<"__builtin_ia32_vcvtbiasps2hf8s_256_mask">,
+ DefaultAttrsIntrinsic<[llvm_v16i8_ty], [llvm_v32i8_ty, llvm_v8f32_ty, llvm_v16i8_ty, llvm_i8_ty],
+ [IntrNoMem]>;
+def int_x86_avx10_mask_vcvtbiasps2hf8s_512 : ClangBuiltin<"__builtin_ia32_vcvtbiasps2hf8s_512_mask">,
+ DefaultAttrsIntrinsic<[llvm_v16i8_ty], [llvm_v64i8_ty, llvm_v16f32_ty, llvm_v16i8_ty, llvm_i16_ty],
+ [IntrNoMem]>;
+
+// Group C: 8bit -> PS expanding conversions
+
+// VCVTBF82PS
+def int_x86_avx10_mask_vcvtbf82ps_128 : ClangBuiltin<"__builtin_ia32_vcvtbf8_2ps128_mask">,
+ DefaultAttrsIntrinsic<[llvm_v4f32_ty], [llvm_v16i8_ty, llvm_v4f32_ty, llvm_i8_ty],
+ [IntrNoMem]>;
+def int_x86_avx10_mask_vcvtbf82ps_256 : ClangBuiltin<"__builtin_ia32_vcvtbf8_2ps256_mask">,
+ DefaultAttrsIntrinsic<[llvm_v8f32_ty], [llvm_v16i8_ty, llvm_v8f32_ty, llvm_i8_ty],
+ [IntrNoMem]>;
+def int_x86_avx10_mask_vcvtbf82ps_512 : ClangBuiltin<"__builtin_ia32_vcvtbf8_2ps512_mask">,
+ DefaultAttrsIntrinsic<[llvm_v16f32_ty], [llvm_v16i8_ty, llvm_v16f32_ty, llvm_i16_ty],
+ [IntrNoMem]>;
+
+// VCVTHF82PS
+def int_x86_avx10_mask_vcvthf82ps_128 : ClangBuiltin<"__builtin_ia32_vcvthf8_2ps128_mask">,
+ DefaultAttrsIntrinsic<[llvm_v4f32_ty], [llvm_v16i8_ty, llvm_v4f32_ty, llvm_i8_ty],
+ [IntrNoMem]>;
+def int_x86_avx10_mask_vcvthf82ps_256 : ClangBuiltin<"__builtin_ia32_vcvthf8_2ps256_mask">,
+ DefaultAttrsIntrinsic<[llvm_v8f32_ty], [llvm_v16i8_ty, llvm_v8f32_ty, llvm_i8_ty],
+ [IntrNoMem]>;
+def int_x86_avx10_mask_vcvthf82ps_512 : ClangBuiltin<"__builtin_ia32_vcvthf8_2ps512_mask">,
+ DefaultAttrsIntrinsic<[llvm_v16f32_ty], [llvm_v16i8_ty, llvm_v16f32_ty, llvm_i16_ty],
+ [IntrNoMem]>;
+
+// Group E: Same-size reg-only conversions (no masking)
+
+// VCVTBF82BF6S
+def int_x86_avx10_vcvtbf82bf6s_128 : ClangBuiltin<"__builtin_ia32_vcvtbf82bf6s128">,
+ DefaultAttrsIntrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty], [IntrNoMem]>;
+def int_x86_avx10_vcvtbf82bf6s_256 : ClangBuiltin<"__builtin_ia32_vcvtbf82bf6s256">,
+ DefaultAttrsIntrinsic<[llvm_v32i8_ty], [llvm_v32i8_ty], [IntrNoMem]>;
+def int_x86_avx10_vcvtbf82bf6s_512 : ClangBuiltin<"__builtin_ia32_vcvtbf82bf6s512">,
+ DefaultAttrsIntrinsic<[llvm_v64i8_ty], [llvm_v64i8_ty], [IntrNoMem]>;
+
+// VCVTHF82HF6S
+def int_x86_avx10_vcvthf82hf6s_128 : ClangBuiltin<"__builtin_ia32_vcvthf82hf6s128">,
+ DefaultAttrsIntrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty], [IntrNoMem]>;
+def int_x86_avx10_vcvthf82hf6s_256 : ClangBuiltin<"__builtin_ia32_vcvthf82hf6s256">,
+ DefaultAttrsIntrinsic<[llvm_v32i8_ty], [llvm_v32i8_ty], [IntrNoMem]>;
+def int_x86_avx10_vcvthf82hf6s_512 : ClangBuiltin<"__builtin_ia32_vcvthf82hf6s512">,
+ DefaultAttrsIntrinsic<[llvm_v64i8_ty], [llvm_v64i8_ty], [IntrNoMem]>;
+
+// Group F: Expanding/same-size conversions with masking
+
+// VCVTBF42HF8: expanding (half-size input -> full output)
+def int_x86_avx10_vcvtbf42hf8_128 : ClangBuiltin<"__builtin_ia32_vcvtbf42hf8128">,
+ DefaultAttrsIntrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty], [IntrNoMem]>;
+def int_x86_avx10_vcvtbf42hf8_256 : ClangBuiltin<"__builtin_ia32_vcvtbf42hf8256">,
+ DefaultAttrsIntrinsic<[llvm_v32i8_ty], [llvm_v16i8_ty], [IntrNoMem]>;
+def int_x86_avx10_vcvtbf42hf8_512 : ClangBuiltin<"__builtin_ia32_vcvtbf42hf8512">,
+ DefaultAttrsIntrinsic<[llvm_v64i8_ty], [llvm_v32i8_ty], [IntrNoMem]>;
+
+// VCVTBF62HF8: same-size, reg-only
+def int_x86_avx10_vcvtbf62hf8_128 : ClangBuiltin<"__builtin_ia32_vcvtbf62hf8128">,
+ DefaultAttrsIntrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty], [IntrNoMem]>;
+def int_x86_avx10_vcvtbf62hf8_256 : ClangBuiltin<"__builtin_ia32_vcvtbf62hf8256">,
+ DefaultAttrsIntrinsic<[llvm_v32i8_ty], [llvm_v32i8_ty], [IntrNoMem]>;
+def int_x86_avx10_vcvtbf62hf8_512 : ClangBuiltin<"__builtin_ia32_vcvtbf62hf8512">,
+ DefaultAttrsIntrinsic<[llvm_v64i8_ty], [llvm_v64i8_ty], [IntrNoMem]>;
+
+// VCVTHF62HF8: same-size, reg-only
+def int_x86_avx10_vcvthf62hf8_128 : ClangBuiltin<"__builtin_ia32_vcvthf62hf8128">,
+ DefaultAttrsIntrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty], [IntrNoMem]>;
+def int_x86_avx10_vcvthf62hf8_256 : ClangBuiltin<"__builtin_ia32_vcvthf62hf8256">,
+ DefaultAttrsIntrinsic<[llvm_v32i8_ty], [llvm_v32i8_ty], [IntrNoMem]>;
+def int_x86_avx10_vcvthf62hf8_512 : ClangBuiltin<"__builtin_ia32_vcvthf62hf8512">,
+ DefaultAttrsIntrinsic<[llvm_v64i8_ty], [llvm_v64i8_ty], [IntrNoMem]>;
+
+// Group H: VUNPACKB - Byte unpack with immediate
+
+def int_x86_avx10_vunpackb_128 : ClangBuiltin<"__builtin_ia32_vunpackb128">,
+ DefaultAttrsIntrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i8_ty],
+ [IntrNoMem, ImmArg<ArgIndex<1>>]>;
+def int_x86_avx10_vunpackb_256 : ClangBuiltin<"__builtin_ia32_vunpackb256">,
+ DefaultAttrsIntrinsic<[llvm_v32i8_ty], [llvm_v32i8_ty, llvm_i8_ty],
+ [IntrNoMem, ImmArg<ArgIndex<1>>]>;
+def int_x86_avx10_vunpackb_512 : ClangBuiltin<"__builtin_ia32_vunpackb512">,
+ DefaultAttrsIntrinsic<[llvm_v64i8_ty], [llvm_v64i8_ty, llvm_i8_ty],
+ [IntrNoMem, ImmArg<ArgIndex<1>>]>;
+}
+
//===----------------------------------------------------------------------===//
let TargetPrefix = "x86" in {
def int_x86_avx10_vaddbf16512 : ClangBuiltin<"__builtin_ia32_vaddbf16512">,
diff --git a/llvm/include/llvm/TargetParser/X86TargetParser.def b/llvm/include/llvm/TargetParser/X86TargetParser.def
index bf1b6c894d959..916f90a4bfd75 100644
--- a/llvm/include/llvm/TargetParser/X86TargetParser.def
+++ b/llvm/include/llvm/TargetParser/X86TargetParser.def
@@ -274,6 +274,7 @@ X86_FEATURE (NDD, "ndd")
X86_FEATURE (EGPR, "egpr")
X86_FEATURE (ZU, "zu")
X86_FEATURE (JMPABS, "jmpabs")
+X86_FEATURE (AVX10_V2_AUX, "avx10-v2-aux")
// These features aren't really CPU features, but the frontend can set them.
X86_FEATURE (RETPOLINE_EXTERNAL_THUNK, "retpoline-external-thunk")
diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td
index 5797171fef23d..443f5bf3ff372 100644
--- a/llvm/lib/Target/X86/X86.td
+++ b/llvm/lib/Target/X86/X86.td
@@ -361,6 +361,9 @@ def FeatureAVX10_2 : SubtargetFeature<"avx10.2", "HasAVX10_2", "true",
def FeatureAVX10_2_512 : SubtargetFeature<"avx10.2-512", "HasAVX10_2_512", "true",
"Support AVX10.2 instruction",
[FeatureAVX10_2]>;
+def FeatureAVX10_V2_AUX : SubtargetFeature<"avx10-v2-aux", "HasAVX10_V2_AUX", "true",
+ "Support AVX10 V2 AUX instructions",
+ [FeatureAVX10_2]>;
def FeatureEGPR : SubtargetFeature<"egpr", "HasEGPR", "true",
"Support extended general purpose register">;
def FeaturePush2Pop2 : SubtargetFeature<"push2pop2", "HasPush2Pop2", "true",
diff --git a/llvm/lib/Target/X86/X86InstrAVX10_V2_AUX.td b/llvm/lib/Target/X86/X86InstrAVX10_V2_AUX.td
new file mode 100644
index 0000000000000..29777281440ce
--- /dev/null
+++ b/llvm/lib/Target/X86/X86InstrAVX10_V2_AUX.td
@@ -0,0 +1,588 @@
+//===-- X86InstrAVX10_V2_AUX.td - AVX10 V2 AUX Instructions --*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the X86 AVX10 V2 AUX instruction set, defining the
+// instructions and their encoding.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// AVX10 V2 AUX Multiclass Definitions
+//===----------------------------------------------------------------------===//
+
+// Group A multiclass: PS(f32) -> i8 truncating conversion (quarter-size output)
+// Output is always xmm for all VL variants.
+// Adapts avx512_vcvt_fp for each VL level with explicit dest/src type mappings.
+multiclass avx10_v2aux_cvt_trunc_ps2i8<bits<8> opc, string OpcodeStr,
+ SDPatternOperator OpNode,
+ SDPatternOperator MaskOpNode> {
+ let Predicates = [HasAVX10_V2_AUX] in {
+ let ExeDomain = SSEPackedSingle in {
+ let Uses = []<Register>, mayRaiseFPException = 0 in {
+ defm Z : avx512_vcvt_fp<opc, OpcodeStr, v16i8x_info, v16f32_info,
+ OpNode, OpNode, WriteCvtPH2PSZ>, EVEX_V512;
+ // Z256/Z128: use null_frag because element count mismatch between
+ // dest (v16i8) and source (v8f32/v4f32) prevents avx512_vcvt_fp from
+ // generating correct masked patterns. Explicit Pat patterns below.
+ defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v16i8x_info, v8f32x_info,
+ null_frag, null_frag,
+ WriteCvtPH2PSZ, v8f32x_info.BroadcastStr,
+ "{y}", v8f32x_info.MemOp,
+ v8f32x_info.KRCWM>, EVEX_V256;
+ defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v16i8x_info, v4f32x_info,
+ null_frag, null_frag,
+ WriteCvtPH2PSZ, v4f32x_info.BroadcastStr,
+ "{x}", f128mem,
+ v4f32x_info.KRCWM>, EVEX_V128;
+ }
+ }
+
+ // InstAliases for x/y suffixes
+ def : InstAlias<OpcodeStr#"x\t{$src, $dst|$dst, $src}",
+ (!cast<Instruction>(NAME # "Z128rr") VR128X:$dst,
+ VR128X:$src), 0>;
+ def : InstAlias<OpcodeStr#"x\t{$src, $dst|$dst, $src}",
+ (!cast<Instruction>(NAME # "Z128rm") VR128X:$dst,
+ f128mem:$src), 0, "intel">;
+ def : InstAlias<OpcodeStr#"y\t{$src, $dst|$dst, $src}",
+ (!cast<Instruction>(NAME # "Z256rr") VR128X:$dst,
+ VR256X:$src), 0>;
+ def : InstAlias<OpcodeStr#"y\t{$src, $dst|$dst, $src}",
+ (!cast<Instruction>(NAME # "Z256rm") VR128X:$dst,
+ f256mem:$src), 0, "intel">;
+
+ // Explicit patterns for Z256 (8 source elements, VK8WM mask)
+ // Unmasked
+ def : Pat<(v16i8 (OpNode (v8f32 VR256X:$src))),
+ (!cast<Instruction>(NAME # "Z256rr") VR256X:$src)>;
+ // Masked (merge)
+ def : Pat<(MaskOpNode (v8f32 VR256X:$src), (v16i8 VR128X:$src0),
+ VK8WM:$mask),
+ (!cast<Instruction>(NAME # "Z256rrk") VR128X:$src0, VK8WM:$mask,
+ VR256X:$src)>;
+ // Masked (zero)
+ def : Pat<(MaskOpNode (v8f32 VR256X:$src), v16i8x_info.ImmAllZerosV,
+ VK8WM:$mask),
+ (!cast<Instruction>(NAME # "Z256rrkz") VK8WM:$mask,
+ VR256X:$src)>;
+ // Memory
+ def : Pat<(v16i8 (OpNode (loadv8f32 addr:$src))),
+ (!cast<Instruction>(NAME # "Z256rm") addr:$src)>;
+ def : Pat<(MaskOpNode (loadv8f32 addr:$src), (v16i8 VR128X:$src0),
+ VK8WM:$mask),
+ (!cast<Instruction>(NAME # "Z256rmk") VR128X:$src0, VK8WM:$mask,
+ addr:$src)>;
+ def : Pat<(MaskOpNode (loadv8f32 addr:$src), v16i8x_info.ImmAllZerosV,
+ VK8WM:$mask),
+ (!cast<Instruction>(NAME # "Z256rmkz") VK8WM:$mask, addr:$src)>;
+ // Broadcast
+ def : Pat<(v16i8 (OpNode (v8f32 (X86VBroadcastld32 addr:$src)))),
+ (!cast<Instruction>(NAME # "Z256rmb") addr:$src)>;
+ def : Pat<(MaskOpNode (v8f32 (X86VBroadcastld32 addr:$src)),
+ (v16i8 VR128X:$src0), VK8WM:$mask),
+ (!cast<Instruction>(NAME # "Z256rmbk") VR128X:$src0, VK8WM:$mask,
+ addr:$src)>;
+ def : Pat<(MaskOpNode (v8f32 (X86VBroadcastld32 addr:$src)),
+ v16i8x_info.ImmAllZerosV, VK8WM:$mask),
+ (!cast<Instruction>(NAME # "Z256rmbkz") VK8WM:$mask, addr:$src)>;
+
+ // Explicit patterns for Z128 (4 source elements, VK4WM mask)
+ // Unmasked
+ def : Pat<(v16i8 (OpNode (v4f32 VR128X:$src))),
+ (!cast<Instruction>(NAME # "Z128rr") VR128X:$src)>;
+ // Masked (merge)
+ def : Pat<(MaskOpNode (v4f32 VR128X:$src), (v16i8 VR128X:$src0),
+ VK4WM:$mask),
+ (!cast<Instruction>(NAME # "Z128rrk") VR128X:$src0, VK4WM:$mask,
+ VR128X:$src)>;
+ // Masked (zero)
+ def : Pat<(MaskOpNode (v4f32 VR128X:$src), v16i8x_info.ImmAllZerosV,
+ VK4WM:$mask),
+ (!cast<Instruction>(NAME # "Z128rrkz") VK4WM:$mask,
+ VR128X:$src)>;
+ // Memory
+ def : Pat<(v16i8 (OpNode (loadv4f32 addr:$src))),
+ (!cast<Instruction>(NAME # "Z128rm") addr:$src)>;
+ def : Pat<(MaskOpNode (loadv4f32 addr:$src), (v16i8 VR128X:$src0),
+ VK4WM:$mask),
+ (!cast<Instruction>(NAME # "Z128rmk") VR128X:$src0, VK4WM:$mask,
+ addr:$src)>;
+ def : Pat<(MaskOpNode (loadv4f32 addr:$src), v16i8x_info.ImmAllZerosV,
+ VK4WM:$mask),
+ (!cast<Instruction>(NAME # "Z128rmkz") VK4WM:$mask, addr:$src)>;
+ // Broadcast
+ def : Pat<(v16i8 (OpNode (v4f32 (X86VBroadcastld32 addr:$src)))),
+ (!cast<Instruction>(NAME # "Z128rmb") addr:$src)>;
+ def : Pat<(MaskOpNode (v4f32 (X86VBroadcastld32 addr:$src)),
+ (v16i8 VR128X:$src0), VK4WM:$mask),
+ (!cast<Instruction>(NAME # "Z128rmbk") VR128X:$src0, VK4WM:$mask,
+ addr:$src)>;
+ def : Pat<(MaskOpNode (v4f32 (X86VBroadcastld32 addr:$src)),
+ v16i8x_info.ImmAllZerosV, VK4WM:$mask),
+ (!cast<Instruction>(NAME # "Z128rmbkz") VK4WM:$mask, addr:$src)>;
+ }
+}
+
+// Group B multiclass: 3-operand bias PS(f32) -> i8 conversion (quarter-size output)
+// bias + f32 source -> i8 dest
+// Reuses avx10_convert_3op_packed from X86InstrAVX10.td for each VL variant.
+multiclass avx10_v2aux_convert_3op_ps<bits<8> OpCode, string OpcodeStr,
+ SDPatternOperator OpNode,
+ SDPatternOperator MaskOpNode> {
+ let Predicates = [HasAVX10_V2_AUX] in {
+ // Z (512-bit): bias=v64i8(zmm), src=v16f32(zmm), dst=v16i8(xmm)
+ // Element counts match (16), so vselect_mask works directly.
+ defm Z : avx10_convert_3op_packed<OpCode, OpcodeStr, v16i8x_info,
+ v64i8_info, v16f32_info, OpNode, OpNode, WriteCvtPH2PSZ>,
+ EVEX_V512, EVEX_CD8<32, CD8VF>;
+ // Z256/Z128: use null_frag because element count mismatch between
+ // dest (v16i8) and source (v8f32/v4f32) prevents vselect_mask from
+ // generating correct masked patterns. Explicit Pat patterns below.
+ defm Z256 : avx10_convert_3op_packed<OpCode, OpcodeStr, v16i8x_info,
+ v32i8x_info, v8f32x_info,
+ null_frag, null_frag, WriteCvtPH2PSZ>,
+ EVEX_V256, EVEX_CD8<32, CD8VF>;
+ defm Z128 : avx10_convert_3op_packed<OpCode, OpcodeStr, v16i8x_info,
+ v16i8x_info, v4f32x_info,
+ null_frag, null_frag, WriteCvtPH2PSZ>,
+ EVEX_V128, EVEX_CD8<32, CD8VF>;
+
+ // Explicit patterns for Z256 (8 source elements, VK8WM mask)
+ def : Pat<(v16i8 (OpNode (v32i8 VR256X:$src1), (v8f32 VR256X:$src2))),
+ (!cast<Instruction>(NAME # "Z256rr") VR256X:$src1, VR256X:$src2)>;
+ def : Pat<(MaskOpNode (v32i8 VR256X:$src1), (v8f32 VR256X:$src2),
+ (v16i8 VR128X:$src0), VK8WM:$mask),
+ (!cast<Instruction>(NAME # "Z256rrk") VR128X:$src0, VK8WM:$mask,
+ VR256X:$src1, VR256X:$src2)>;
+ def : Pat<(MaskOpNode (v32i8 VR256X:$src1), (v8f32 VR256X:$src2),
+ v16i8x_info.ImmAllZerosV, VK8WM:$mask),
+ (!cast<Instruction>(NAME # "Z256rrkz") VK8WM:$mask,
+ VR256X:$src1, VR256X:$src2)>;
+ // Memory
+ def : Pat<(v16i8 (OpNode (v32i8 VR256X:$src1), (loadv8f32 addr:$src2))),
+ (!cast<Instruction>(NAME # "Z256rm") VR256X:$src1, addr:$src2)>;
+ def : Pat<(MaskOpNode (v32i8 VR256X:$src1), (loadv8f32 addr:$src2),
+ (v16i8 VR128X:$src0), VK8WM:$mask),
+ (!cast<Instruction>(NAME # "Z256rmk") VR128X:$src0, VK8WM:$mask,
+ VR256X:$src1, addr:$src2)>;
+ def : Pat<(MaskOpNode (v32i8 VR256X:$src1), (loadv8f32 addr:$src2),
+ v16i8x_info.ImmAllZerosV, VK8WM:$mask),
+ (!cast<Instruction>(NAME # "Z256rmkz") VK8WM:$mask,
+ VR256X:$src1, addr:$src2)>;
+ // Broadcast
+ def : Pat<(v16i8 (OpNode (v32i8 VR256X:$src1),
+ (v8f32 (X86VBroadcastld32 addr:$src2)))),
+ (!cast<Instruction>(NAME # "Z256rmb") VR256X:$src1, addr:$src2)>;
+ def : Pat<(MaskOpNode (v32i8 VR256X:$src1),
+ (v8f32 (X86VBroadcastld32 addr:$src2)),
+ (v16i8 VR128X:$src0), VK8WM:$mask),
+ (!cast<Instruction>(NAME # "Z256rmbk") VR128X:$src0, VK8WM:$mask,
+ VR256X:$src1, addr:$src2)>;
+ def : Pat<(MaskOpNode (v32i8 VR256X:$src1),
+ (v8f32 (X86VBroadcastld32 addr:$src2)),
+ v16i8x_info.ImmAllZerosV, VK8WM:$mask),
+ (!cast<Instruction>(NAME # "Z256rmbkz") VK8WM:$mask,
+ VR256X:$src1, addr:$src2)>;
+
+ // Explicit patterns for Z128 (4 source elements, VK4WM mask)
+ def : Pat<(v16i8 (OpNode (v16i8 VR128X:$src1), (v4f32 VR128X:$src2))),
+ (!cast<Instruction>(NAME # "Z128rr") VR128X:$src1, VR128X:$src2)>;
+ def : Pat<(MaskOpNode (v16i8 VR128X:$src1), (v4f32 VR128X:$src2),
+ (v16i8 VR128X:$src0), VK4WM:$mask),
+ (!cast<Instruction>(NAME # "Z128rrk") VR128X:$src0, VK4WM:$mask,
+ VR128X:$src1, VR128X:$src2)>;
+ def : Pat<(MaskOpNode (v16i8 VR128X:$src1), (v4f32 VR128X:$src2),
+ v16i8x_info.ImmAllZerosV, VK4WM:$mask),
+ (!cast<Instruction>(NAME # "Z128rrkz") VK4WM:$mask,
+ VR128X:$src1, VR128X:$src2)>;
+ // Memory
+ def : Pat<(v16i8 (OpNode (v16i8 VR128X:$src1), (loadv4f32 addr:$src2))),
+ (!cast<Instruction>(NAME # "Z128rm") VR128X:$src1, addr:$src2)>;
+ def : Pat<(MaskOpNode (v16i8 VR128X:$src1), (loadv4f32 addr:$src2),
+ (v16i8 VR128X:$src0), VK4WM:$mask),
+ (!cast<Instruction>(NAME # "Z128rmk") VR128X:$src0, VK4WM:$mask,
+ VR128X:$src1, addr:$src2)>;
+ def : Pat<(MaskOpNode (v16i8 VR128X:$src1), (loadv4f32 addr:$src2),
+ v16i8x_info.ImmAllZerosV, VK4WM:$mask),
+ (!cast<Instruction>(NAME # "Z128rmkz") VK4WM:$mask,
+ VR128X:$src1, addr:$src2)>;
+ // Broadcast
+ def : Pat<(v16i8 (OpNode (v16i8 VR128X:$src1),
+ (v4f32 (X86VBroadcastld32 addr:$src2)))),
+ (!cast<Instruction>(NAME # "Z128rmb") VR128X:$src1, addr:$src2)>;
+ def : Pat<(MaskOpNode (v16i8 VR128X:$src1),
+ (v4f32 (X86VBroadcastld32 addr:$src2)),
+ (v16i8 VR128X:$src0), VK4WM:$mask),
+ (!cast<Instruction>(NAME # "Z128rmbk") VR128X:$src0, VK4WM:$mask,
+ VR128X:$src1, addr:$src2)>;
+ def : Pat<(MaskOpNode (v16i8 VR128X:$src1),
+ (v4f32 (X86VBroadcastld32 addr:$src2)),
+ v16i8x_info.ImmAllZerosV, VK4WM:$mask),
+ (!cast<Instruction>(NAME # "Z128rmbkz") VK4WM:$mask,
+ VR128X:$src1, addr:$src2)>;
+ }
+}
+
+// Group C multiclass: i8 -> f32 expanding conversion (4x expansion, no broadcast)
+multiclass avx10_v2aux_convert_2op_i8_to_f32<string OpcodeStr, bits<8> opc,
+ SDNode OpNode> {
+ let Predicates = [HasAVX10_V2_AUX] in {
+ defm Z : avx10_convert_2op_nomb_packed<opc, OpcodeStr, v16f32_info,
+ v16i8x_info, OpNode, f128mem,
+ WriteCvtPH2PSZ>, EVEX_V512;
+ defm Z128 : avx10_convert_2op_nomb_packed<opc, OpcodeStr, v4f32x_info,
+ v16i8x_info, OpNode, f32mem,
+ WriteCvtPH2PSZ>, EVEX_V128;
+ defm Z256 : avx10_convert_2op_nomb_packed<opc, OpcodeStr, v8f32x_info,
+ v16i8x_info, OpNode, f64mem,
+ WriteCvtPH2PSZ>, EVEX_V256;
+ }
+}
+
+// Group D multiclass: Store-like truncation (reg/mem dest, no masking)
+// Uses MRMDestReg/MRMDestMem since destination can be memory operand.
+// Source is in reg field, destination is in r/m field.
+multiclass avx10_v2aux_trunc_store<bits<8> opc, string OpcodeStr,
+ X86VectorVTInfo SrcInfo,
+ X86VectorVTInfo DestInfo,
+ X86MemOperand x86memop> {
+ let hasSideEffects = 0 in {
+ def rr : I<opc, MRMDestReg, (outs DestInfo.RC:$dst),
+ (ins SrcInfo.RC:$src),
+ OpcodeStr # "\t{$src, $dst|$dst, $src}", []>,
+ EVEX, Sched<[WriteCvtPH2PSZ]>;
+ let mayStore = 1 in
+ def mr : I<opc, MRMDestMem, (outs),
+ (ins x86memop:$dst, SrcInfo.RC:$src),
+ OpcodeStr # "\t{$src, $dst|$dst, $src}", []>,
+ EVEX, Sched<[WriteCvtPH2PSZ.Folded]>;
+ }
+}
+
+// Group F helper: expanding conversion with masking, no broadcast (reg+mem)
+multiclass avx10_v2aux_convert_expand_masked<bits<8> opc, string OpcodeStr,
+ X86VectorVTInfo _dest,
+ X86VectorVTInfo _src,
+ X86MemOperand x86memop> {
+ let ExeDomain = _dest.ExeDomain in {
+ defm rr : AVX512_maskable_custom<opc, MRMSrcReg,
+ (outs _dest.RC:$dst),
+ (ins _src.RC:$src),
+ (ins _dest.RC:$src0, _dest.KRCWM:$mask, _src.RC:$src),
+ (ins _dest.KRCWM:$mask, _src.RC:$src),
+ OpcodeStr, "$src", "$src", [], [], [],
+ "$src0 = $dst">,
+ EVEX, Sched<[WriteCvtPH2PSZ]>;
+ let mayLoad = 1 in
+ defm rm : AVX512_maskable_custom<opc, MRMSrcMem,
+ (outs _dest.RC:$dst),
+ (ins x86memop:$src),
+ (ins _dest.RC:$src0, _dest.KRCWM:$mask, x86memop:$src),
+ (ins _dest.KRCWM:$mask, x86memop:$src),
+ OpcodeStr, "$src", "$src", [], [], [],
+ "$src0 = $dst">,
+ EVEX, Sched<[WriteCvtPH2PSZ.Folded]>;
+ }
+}
+
+// Group F helper: same-size conversion with masking (reg-only)
+multiclass avx10_v2aux_convert_samesize_masked<bits<8> opc, string OpcodeStr,
+ X86VectorVTInfo _> {
+ let ExeDomain = _.ExeDomain in {
+ defm rr : AVX512_maskable_custom<opc, MRMSrcReg,
+ (outs _.RC:$dst),
+ (ins _.RC:$src),
+ (ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src),
+ (ins _.KRCWM:$mask, _.RC:$src),
+ OpcodeStr, "$src", "$src", [], [], [],
+ "$src0 = $dst">,
+ EVEX, Sched<[WriteCvtPH2PSZ]>;
+ }
+}
+
+// Group H multiclass: Byte unpack with immediate
+multiclass avx10_v2aux_unpackb<bits<8> opc, string OpcodeStr,
+ X86VectorVTInfo _> {
+ let ImmT = Imm8 in {
+ defm ri : AVX512_maskable_custom<opc, MRMSrcReg,
+ (outs _.RC:$dst),
+ (ins _.RC:$src1, u8imm:$src2),
+ (ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src1, u8imm:$src2),
+ (ins _.KRCWM:$mask, _.RC:$src1, u8imm:$src2),
+ OpcodeStr, "$src2, $src1", "$src1, $src2",
+ [], [], [],
+ "$src0 = $dst">,
+ Sched<[WriteShuffle]>;
+ let mayLoad = 1 in
+ defm mi : AVX512_maskable_custom<opc, MRMSrcMem,
+ (outs _.RC:$dst),
+ (ins _.MemOp:$src1, u8imm:$src2),
+ (ins _.RC:$src0, _.KRCWM:$mask, _.MemOp:$src1, u8imm:$src2),
+ (ins _.KRCWM:$mask, _.MemOp:$src1, u8imm:$src2),
+ OpcodeStr, "$src2, $src1", "$src1, $src2",
+ [], [], [],
+ "$src0 = $dst">,
+ Sched<[WriteShuffle.Folded]>;
+ }
+}
+
+//===----------------------------------------------------------------------===//
+// AVX10 V2 AUX Instruction Definitions
+//===----------------------------------------------------------------------===//
+
+//-------------------------------------------------
+// Group A: PS->8bit truncating conversions
+//-------------------------------------------------
+
+defm VCVTPS2BF8 : avx10_v2aux_cvt_trunc_ps2i8<0x39, "vcvtps2bf8",
+ X86vcvtps2bf8, X86vmcvtps2bf8>,
+ T_MAP5, XS, EVEX_CD8<32, CD8VF>;
+defm VCVTPS2BF8S : avx10_v2aux_cvt_trunc_ps2i8<0x3B, "vcvtps2bf8s",
+ X86vcvtps2bf8s, X86vmcvtps2bf8s>,
+ T_MAP5, XS, EVEX_CD8<32, CD8VF>;
+defm VCVTPS2HF8 : avx10_v2aux_cvt_trunc_ps2i8<0x38, "vcvtps2hf8",
+ X86vcvtps2hf8, X86vmcvtps2hf8>,
+ T_MAP5, XS, EVEX_CD8<32, CD8VF>;
+defm VCVTPS2HF8S : avx10_v2aux_cvt_trunc_ps2i8<0x3A, "vcvtps2hf8s",
+ X86vcvtps2hf8s, X86vmcvtps2hf8s>,
+ T_MAP5, XS, EVEX_CD8<32, CD8VF>;
+defm VCVTROPS2HF8 : avx10_v2aux_cvt_trunc_ps2i8<0x38, "vcvtrops2hf8",
+ X86vcvtrops2hf8, X86vmcvtrops2hf8>,
+ T_MAP5, PD, EVEX_CD8<32, CD8VF>;
+defm VCVTROPS2HF8S : avx10_v2aux_cvt_trunc_ps2i8<0x3A, "vcvtrops2hf8s",
+ X86vcvtrops2hf8s, X86vmcvtrops2hf8s>,
+ T_MAP5, PD, EVEX_CD8<32, CD8VF>;
+
+//-------------------------------------------------
+// Group B: Bias PS->8bit conversions (3-operand)
+//-------------------------------------------------
+
+defm VCVTBIASPS2BF8 : avx10_v2aux_convert_3op_ps<0x39, "vcvtbiasps2bf8",
+ X86vcvtbiasps2bf8,
+ X86vmcvtbiasps2bf8>,
+ T_MAP5, PS;
+defm VCVTBIASPS2BF8S : avx10_v2aux_convert_3op_ps<0x3B, "vcvtbiasps2bf8s",
+ X86vcvtbiasps2bf8s,
+ X86vmcvtbiasps2bf8s>,
+ T_MAP5, PS;
+defm VCVTBIASPS2HF8 : avx10_v2aux_convert_3op_ps<0x38, "vcvtbiasps2hf8",
+ X86vcvtbiasps2hf8,
+ X86vmcvtbiasps2hf8>,
+ T_MAP5, PS;
+defm VCVTBIASPS2HF8S : avx10_v2aux_convert_3op_ps<0x3A, "vcvtbiasps2hf8s",
+ X86vcvtbiasps2hf8s,
+ X86vmcvtbiasps2hf8s>,
+ T_MAP5, PS;
+
+//-------------------------------------------------
+// Group C: 8bit->PS expanding conversions
+//-------------------------------------------------
+
+defm VCVTBF82PS : avx10_v2aux_convert_2op_i8_to_f32<"vcvtbf82ps", 0x36,
+ X86vcvtbf82ps>,
+ PS, T_MAP5, EVEX, EVEX_CD8<32, CD8VQ>, REX_W;
+defm VCVTHF82PS : avx10_v2aux_convert_2op_i8_to_f32<"vcvthf82ps", 0x36,
+ X86vcvthf82ps>,
+ PS, T_MAP5, EVEX, EVEX_CD8<32, CD8VQ>;
+
+// X //-------------------------------------------------
+// Group D: BF8/HF8->BF4S store-like truncations
+//-------------------------------------------------
+
+let Predicates = [HasAVX10_V2_AUX] in {
+ defm VCVTBF82BF4SZ : avx10_v2aux_trunc_store<0x3D, "vcvtbf82bf4s",
+ v64i8_info, v32i8x_info, i256mem>,
+ T_MAP5, XS, REX_W, EVEX_V512, EVEX_CD8<8, CD8VH>;
+ defm VCVTBF82BF4SZ256 : avx10_v2aux_trunc_store<0x3D, "vcvtbf82bf4s",
+ v32i8x_info, v16i8x_info, i128mem>,
+ T_MAP5, XS, REX_W, EVEX_V256, EVEX_CD8<8, CD8VH>;
+ defm VCVTBF82BF4SZ128 : avx10_v2aux_trunc_store<0x3D, "vcvtbf82bf4s",
+ v16i8x_info, v16i8x_info, i64mem>,
+ T_MAP5, XS, REX_W, EVEX_V128, EVEX_CD8<8, CD8VH>;
+
+ defm VCVTHF82BF4SZ : avx10_v2aux_trunc_store<0x3D, "vcvthf82bf4s",
+ v64i8_info, v32i8x_info, i256mem>,
+ T_MAP5, XS, EVEX_V512, EVEX_CD8<8, CD8VH>;
+ defm VCVTHF82BF4SZ256 : avx10_v2aux_trunc_store<0x3D, "vcvthf82bf4s",
+ v32i8x_info, v16i8x_info, i128mem>,
+ T_MAP5, XS, EVEX_V256, EVEX_CD8<8, CD8VH>;
+ defm VCVTHF82BF4SZ128 : avx10_v2aux_trunc_store<0x3D, "vcvthf82bf4s",
+ v16i8x_info, v16i8x_info, i64mem>,
+ T_MAP5, XS, EVEX_V128, EVEX_CD8<8, CD8VH>;
+}
+
+//-------------------------------------------------
+// Group E: Same-size reg-only conversions (no masking)
+//-------------------------------------------------
+
+let Predicates = [HasAVX10_V2_AUX], hasSideEffects = 0 in {
+ def VCVTBF82BF6SZrr : I<0x3E, MRMSrcReg, (outs VR512:$dst),
+ (ins VR512:$src),
+ "vcvtbf82bf6s\t{$src, $dst|$dst, $src}", []>,
+ EVEX, T_MAP5, XS, REX_W, EVEX_V512,
+ Sched<[WriteCvtPH2PSZ]>;
+ def VCVTBF82BF6SZ256rr : I<0x3E, MRMSrcReg, (outs VR256X:$dst),
+ (ins VR256X:$src),
+ "vcvtbf82bf6s\t{$src, $dst|$dst, $src}", []>,
+ EVEX, T_MAP5, XS, REX_W, EVEX_V256,
+ Sched<[WriteCvtPH2PSZ]>;
+ def VCVTBF82BF6SZ128rr : I<0x3E, MRMSrcReg, (outs VR128X:$dst),
+ (ins VR128X:$src),
+ "vcvtbf82bf6s\t{$src, $dst|$dst, $src}", []>,
+ EVEX, T_MAP5, XS, REX_W, EVEX_V128,
+ Sched<[WriteCvtPH2PSZ]>;
+
+ def VCVTHF82HF6SZrr : I<0x3C, MRMSrcReg, (outs VR512:$dst),
+ (ins VR512:$src),
+ "vcvthf82hf6s\t{$src, $dst|$dst, $src}", []>,
+ EVEX, T_MAP5, XS, EVEX_V512,
+ Sched<[WriteCvtPH2PSZ]>;
+ def VCVTHF82HF6SZ256rr : I<0x3C, MRMSrcReg, (outs VR256X:$dst),
+ (ins VR256X:$src),
+ "vcvthf82hf6s\t{$src, $dst|$dst, $src}", []>,
+ EVEX, T_MAP5, XS, EVEX_V256,
+ Sched<[WriteCvtPH2PSZ]>;
+ def VCVTHF82HF6SZ128rr : I<0x3C, MRMSrcReg, (outs VR128X:$dst),
+ (ins VR128X:$src),
+ "vcvthf82hf6s\t{$src, $dst|$dst, $src}", []>,
+ EVEX, T_MAP5, XS, EVEX_V128,
+ Sched<[WriteCvtPH2PSZ]>;
+}
+
+// Intrinsic patterns for Group E
+let Predicates = [HasAVX10_V2_AUX] in {
+ def : Pat<(v16i8 (int_x86_avx10_vcvtbf82bf6s_128 (v16i8 VR128X:$src))),
+ (VCVTBF82BF6SZ128rr VR128X:$src)>;
+ def : Pat<(v32i8 (int_x86_avx10_vcvtbf82bf6s_256 (v32i8 VR256X:$src))),
+ (VCVTBF82BF6SZ256rr VR256X:$src)>;
+ def : Pat<(v64i8 (int_x86_avx10_vcvtbf82bf6s_512 (v64i8 VR512:$src))),
+ (VCVTBF82BF6SZrr VR512:$src)>;
+
+ def : Pat<(v16i8 (int_x86_avx10_vcvthf82hf6s_128 (v16i8 VR128X:$src))),
+ (VCVTHF82HF6SZ128rr VR128X:$src)>;
+ def : Pat<(v32i8 (int_x86_avx10_vcvthf82hf6s_256 (v32i8 VR256X:$src))),
+ (VCVTHF82HF6SZ256rr VR256X:$src)>;
+ def : Pat<(v64i8 (int_x86_avx10_vcvthf82hf6s_512 (v64i8 VR512:$src))),
+ (VCVTHF82HF6SZrr VR512:$src)>;
+}
+
+//-------------------------------------------------
+// Group F: Expanding/same-size conversions with masking
+//-------------------------------------------------
+
+// VCVTBF42HF8: expanding (2x), with masking, no broadcast
+// Z128: xmm{k}{z}, xmm/m64 Z256: ymm{k}{z}, xmm/m128 Z: zmm{k}{z}, ymm/m256
+let Predicates = [HasAVX10_V2_AUX] in {
+ defm VCVTBF42HF8Z : avx10_v2aux_convert_expand_masked<0x37, "vcvtbf42hf8",
+ v64i8_info, v32i8x_info, f256mem>,
+ T_MAP5, PS, EVEX_V512, EVEX_CD8<8, CD8VH>;
+ defm VCVTBF42HF8Z128 : avx10_v2aux_convert_expand_masked<0x37, "vcvtbf42hf8",
+ v16i8x_info, v16i8x_info, f64mem>,
+ T_MAP5, PS, EVEX_V128, EVEX_CD8<8, CD8VH>;
+ defm VCVTBF42HF8Z256 : avx10_v2aux_convert_expand_masked<0x37, "vcvtbf42hf8",
+ v32i8x_info, v16i8x_info, f128mem>,
+ T_MAP5, PS, EVEX_V256, EVEX_CD8<8, CD8VH>;
+}
+let Predicates = [HasAVX10_V2_AUX] in {
+ let ExeDomain = SSEPackedInt in {
+ // VCVTBF62HF8: same-size with masking, reg-only (66.MAP5.W1)
+ defm VCVTBF62HF8Z : avx10_v2aux_convert_samesize_masked<0x37,
+ "vcvtbf62hf8", v64i8_info>,
+ T_MAP5, PD, REX_W, EVEX_V512;
+ defm VCVTBF62HF8Z256 : avx10_v2aux_convert_samesize_masked<0x37,
+ "vcvtbf62hf8", v32i8x_info>,
+ T_MAP5, PD, REX_W, EVEX_V256;
+ defm VCVTBF62HF8Z128 : avx10_v2aux_convert_samesize_masked<0x37,
+ "vcvtbf62hf8", v16i8x_info>,
+ T_MAP5, PD, REX_W, EVEX_V128;
+
+ // VCVTHF62HF8: same-size with masking, reg-only (66.MAP5.W0)
+ defm VCVTHF62HF8Z : avx10_v2aux_convert_samesize_masked<0x37,
+ "vcvthf62hf8", v64i8_info>,
+ T_MAP5, PD, EVEX_V512;
+ defm VCVTHF62HF8Z256 : avx10_v2aux_convert_samesize_masked<0x37,
+ "vcvthf62hf8", v32i8x_info>,
+ T_MAP5, PD, EVEX_V256;
+ defm VCVTHF62HF8Z128 : avx10_v2aux_convert_samesize_masked<0x37,
+ "vcvthf62hf8", v16i8x_info>,
+ T_MAP5, PD, EVEX_V128;
+ }
+}
+
+// Intrinsic patterns for Group F (unmasked only; masking via selectb in C header)
+
+let Predicates = [HasAVX10_V2_AUX] in {
+ // VCVTBF42HF8
+ def : Pat<(v16i8 (int_x86_avx10_vcvtbf42hf8_128 (v16i8 VR128X:$src))),
+ (VCVTBF42HF8Z128rr VR128X:$src)>;
+ def : Pat<(v32i8 (int_x86_avx10_vcvtbf42hf8_256 (v16i8 VR128X:$src))),
+ (VCVTBF42HF8Z256rr VR128X:$src)>;
+ def : Pat<(v64i8 (int_x86_avx10_vcvtbf42hf8_512 (v32i8 VR256X:$src))),
+ (VCVTBF42HF8Zrr VR256X:$src)>;
+
+ // VCVTBF62HF8
+ def : Pat<(v16i8 (int_x86_avx10_vcvtbf62hf8_128 (v16i8 VR128X:$src))),
+ (VCVTBF62HF8Z128rr VR128X:$src)>;
+ def : Pat<(v32i8 (int_x86_avx10_vcvtbf62hf8_256 (v32i8 VR256X:$src))),
+ (VCVTBF62HF8Z256rr VR256X:$src)>;
+ def : Pat<(v64i8 (int_x86_avx10_vcvtbf62hf8_512 (v64i8 VR512:$src))),
+ (VCVTBF62HF8Zrr VR512:$src)>;
+
+ // VCVTHF62HF8
+ def : Pat<(v16i8 (int_x86_avx10_vcvthf62hf8_128 (v16i8 VR128X:$src))),
+ (VCVTHF62HF8Z128rr VR128X:$src)>;
+ def : Pat<(v32i8 (int_x86_avx10_vcvthf62hf8_256 (v32i8 VR256X:$src))),
+ (VCVTHF62HF8Z256rr VR256X:$src)>;
+ def : Pat<(v64i8 (int_x86_avx10_vcvthf62hf8_512 (v64i8 VR512:$src))),
+ (VCVTHF62HF8Zrr VR512:$src)>;
+}
+
+//-------------------------------------------------
+// Group G: VPMOVSSDB - Integer DWord->Byte signed saturation
+// F3.0F38.W0 0x41
+//-------------------------------------------------
+
+let Predicates = [HasAVX10_V2_AUX] in
+ defm VPMOVSSDZ : avx512_trunc_common<0x41, "vpmovssdb", X86vtruncs,
+ X86vmtruncs, SchedWriteVecTruncate.ZMM,
+ v16i32_info, v16i8x_info, i128mem>,
+ EVEX_V512, EVEX_CD8<8, CD8VQ>;
+let Predicates = [HasVLX, HasAVX10_V2_AUX] in {
+ defm VPMOVSSDZ256 : avx512_trunc_common<0x41, "vpmovssdb", X86vtruncs,
+ X86vmtruncs, SchedWriteVecTruncate.YMM,
+ v8i32x_info, v16i8x_info, i64mem>,
+ EVEX_V256, EVEX_CD8<8, CD8VQ>;
+ defm VPMOVSSDZ128 : avx512_trunc_common<0x41, "vpmovssdb", X86vtruncs,
+ X86vmtruncs, SchedWriteVecTruncate.XMM,
+ v4i32x_info, v16i8x_info, i32mem>,
+ EVEX_V128, EVEX_CD8<8, CD8VQ>;
+}
+
+//-------------------------------------------------
+// Group H: VUNPACKB - Byte unpack with immediate
+//-------------------------------------------------
+
+let Predicates = [HasAVX10_V2_AUX] in {
+ defm VUNPACKBZ : avx10_v2aux_unpackb<0x3D, "vunpackb", v64i8_info>,
+ EVEX_V512, TA, PS, EVEX, EVEX_CD8<8, CD8VF>;
+ defm VUNPACKBZ256 : avx10_v2aux_unpackb<0x3D, "vunpackb", v32i8x_info>,
+ EVEX_V256, TA, PS, EVEX, EVEX_CD8<8, CD8VF>;
+ defm VUNPACKBZ128 : avx10_v2aux_unpackb<0x3D, "vunpackb", v16i8x_info>,
+ EVEX_V128, TA, PS, EVEX, EVEX_CD8<8, CD8VF>;
+
+ // Intrinsic patterns for Group H (unmasked only; masking via selectb in C header)
+ def : Pat<(v16i8 (int_x86_avx10_vunpackb_128
+ (v16i8 VR128X:$src1), timm:$src2)),
+ (VUNPACKBZ128ri VR128X:$src1, timm:$src2)>;
+ def : Pat<(v32i8 (int_x86_avx10_vunpackb_256
+ (v32i8 VR256X:$src1), timm:$src2)),
+ (VUNPACKBZ256ri VR256X:$src1, timm:$src2)>;
+ def : Pat<(v64i8 (int_x86_avx10_vunpackb_512
+ (v64i8 VR512:$src1), timm:$src2)),
+ (VUNPACKBZri VR512:$src1, timm:$src2)>;
+}
diff --git a/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td b/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
index 1a75381aaaa24..c109d682dd915 100644
--- a/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
+++ b/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
@@ -1211,6 +1211,63 @@ def X86vmcvtph2hf8 : SDNode<"X86ISD::VMCVTPH2HF8",
def X86vmcvtph2hf8s : SDNode<"X86ISD::VMCVTPH2HF8S",
SDTAVX10CONVERT_I8F16_MASK>;
+// AVX10 V2 AUX convert SDTypeProfiles
+def SDTAVX10CONVERT_I8F32 : SDTypeProfile<1, 1, [
+ SDTCVecEltisVT<0, i8>, SDTCVecEltisVT<1, f32>
+]>;
+
+def SDTAVX10CONVERT_I8F32_MASK : SDTypeProfile<1, 3, [
+ SDTCVecEltisVT<0, i8>, SDTCVecEltisVT<1, f32>,
+ SDTCisSameAs<0, 2>, SDTCVecEltisVT<3, i1>,
+ SDTCisSameNumEltsAs<1, 3>
+]>;
+
+def SDTAVX10CONVERT_2I8F32 : SDTypeProfile<1, 2, [
+ SDTCVecEltisVT<0, i8>, SDTCVecEltisVT<1, i8>, SDTCVecEltisVT<2, f32>
+]>;
+
+def SDTAVX10CONVERT_2I8F32_MASK : SDTypeProfile<1, 4, [
+ SDTCVecEltisVT<0, i8>, SDTCVecEltisVT<1, i8>,
+ SDTCVecEltisVT<2, f32>, SDTCisSameAs<0, 3>, SDTCVecEltisVT<4, i1>,
+ SDTCisSameNumEltsAs<2, 4>
+]>;
+
+def SDTAVX10CONVERT_F32I8 : SDTypeProfile<1, 1, [
+ SDTCVecEltisVT<0, f32>, SDTCVecEltisVT<1, i8>
+]>;
+
+// AVX10 V2 AUX convert SDNodes
+// Group A: PS->8bit truncating (single source)
+def X86vcvtps2bf8 : SDNode<"X86ISD::VCVTPS2BF8", SDTAVX10CONVERT_I8F32>;
+def X86vcvtps2bf8s : SDNode<"X86ISD::VCVTPS2BF8S", SDTAVX10CONVERT_I8F32>;
+def X86vcvtps2hf8 : SDNode<"X86ISD::VCVTPS2HF8", SDTAVX10CONVERT_I8F32>;
+def X86vcvtps2hf8s : SDNode<"X86ISD::VCVTPS2HF8S", SDTAVX10CONVERT_I8F32>;
+def X86vcvtrops2hf8 : SDNode<"X86ISD::VCVTROPS2HF8", SDTAVX10CONVERT_I8F32>;
+def X86vcvtrops2hf8s : SDNode<"X86ISD::VCVTROPS2HF8S", SDTAVX10CONVERT_I8F32>;
+
+// Masked variants
+def X86vmcvtps2bf8 : SDNode<"X86ISD::VMCVTPS2BF8", SDTAVX10CONVERT_I8F32_MASK>;
+def X86vmcvtps2bf8s : SDNode<"X86ISD::VMCVTPS2BF8S", SDTAVX10CONVERT_I8F32_MASK>;
+def X86vmcvtps2hf8 : SDNode<"X86ISD::VMCVTPS2HF8", SDTAVX10CONVERT_I8F32_MASK>;
+def X86vmcvtps2hf8s : SDNode<"X86ISD::VMCVTPS2HF8S", SDTAVX10CONVERT_I8F32_MASK>;
+def X86vmcvtrops2hf8 : SDNode<"X86ISD::VMCVTROPS2HF8", SDTAVX10CONVERT_I8F32_MASK>;
+def X86vmcvtrops2hf8s : SDNode<"X86ISD::VMCVTROPS2HF8S", SDTAVX10CONVERT_I8F32_MASK>;
+
+// Group B: Bias PS->8bit (3 operand)
+def X86vcvtbiasps2bf8 : SDNode<"X86ISD::VCVTBIASPS2BF8", SDTAVX10CONVERT_2I8F32>;
+def X86vcvtbiasps2bf8s : SDNode<"X86ISD::VCVTBIASPS2BF8S", SDTAVX10CONVERT_2I8F32>;
+def X86vcvtbiasps2hf8 : SDNode<"X86ISD::VCVTBIASPS2HF8", SDTAVX10CONVERT_2I8F32>;
+def X86vcvtbiasps2hf8s : SDNode<"X86ISD::VCVTBIASPS2HF8S", SDTAVX10CONVERT_2I8F32>;
+
+def X86vmcvtbiasps2bf8 : SDNode<"X86ISD::VMCVTBIASPS2BF8", SDTAVX10CONVERT_2I8F32_MASK>;
+def X86vmcvtbiasps2bf8s : SDNode<"X86ISD::VMCVTBIASPS2BF8S", SDTAVX10CONVERT_2I8F32_MASK>;
+def X86vmcvtbiasps2hf8 : SDNode<"X86ISD::VMCVTBIASPS2HF8", SDTAVX10CONVERT_2I8F32_MASK>;
+def X86vmcvtbiasps2hf8s : SDNode<"X86ISD::VMCVTBIASPS2HF8S", SDTAVX10CONVERT_2I8F32_MASK>;
+
+// Group C: 8bit->PS expanding
+def X86vcvtbf82ps : SDNode<"X86ISD::VCVTBF82PS", SDTAVX10CONVERT_F32I8>;
+def X86vcvthf82ps : SDNode<"X86ISD::VCVTHF82PS", SDTAVX10CONVERT_F32I8>;
+
//===----------------------------------------------------------------------===//
// SSE pattern fragments
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/X86/X86InstrInfo.td b/llvm/lib/Target/X86/X86InstrInfo.td
index 0c4abc2c400f6..caf8344dc664c 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.td
+++ b/llvm/lib/Target/X86/X86InstrInfo.td
@@ -85,6 +85,9 @@ include "X86InstrKL.td"
// AMX instructions
include "X86InstrAMX.td"
+// AVX10 V2 AUX instructions
+include "X86InstrAVX10_V2_AUX.td"
+
// RAO-INT instructions
include "X86InstrRAOINT.td"
diff --git a/llvm/lib/Target/X86/X86InstrPredicates.td b/llvm/lib/Target/X86/X86InstrPredicates.td
index afca2e6eafd2c..54633b451e41b 100644
--- a/llvm/lib/Target/X86/X86InstrPredicates.td
+++ b/llvm/lib/Target/X86/X86InstrPredicates.td
@@ -77,6 +77,7 @@ def HasAVX1Only : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX2()">;
def HasAVX10_1 : Predicate<"Subtarget->hasAVX10_1()">;
def HasAVX10_2 : Predicate<"Subtarget->hasAVX10_2()">;
def NoAVX10_2 : Predicate<"!Subtarget->hasAVX10_2()">;
+def HasAVX10_V2_AUX : Predicate<"Subtarget->hasAVX10_V2_AUX()">;
def HasAVX512 : Predicate<"Subtarget->hasAVX512()">;
def UseAVX : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX512()">;
def UseAVX2 : Predicate<"Subtarget->hasAVX2() && !Subtarget->hasAVX512()">;
diff --git a/llvm/lib/Target/X86/X86IntrinsicsInfo.h b/llvm/lib/Target/X86/X86IntrinsicsInfo.h
index a6b0db0230cf3..d92834aa5d5c5 100644
--- a/llvm/lib/Target/X86/X86IntrinsicsInfo.h
+++ b/llvm/lib/Target/X86/X86IntrinsicsInfo.h
@@ -443,6 +443,12 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
X86ISD::VFPROUND2, 0),
X86_INTRINSIC_DATA(avx10_mask_vcvt2ps2phx_512, INTR_TYPE_2OP_MASK,
X86ISD::VFPROUND2, X86ISD::VFPROUND2_RND),
+ X86_INTRINSIC_DATA(avx10_mask_vcvtbf82ps_128, INTR_TYPE_1OP_MASK,
+ X86ISD::VCVTBF82PS, 0),
+ X86_INTRINSIC_DATA(avx10_mask_vcvtbf82ps_256, INTR_TYPE_1OP_MASK,
+ X86ISD::VCVTBF82PS, 0),
+ X86_INTRINSIC_DATA(avx10_mask_vcvtbf82ps_512, INTR_TYPE_1OP_MASK,
+ X86ISD::VCVTBF82PS, 0),
X86_INTRINSIC_DATA(avx10_mask_vcvtbiasph2bf8128, TRUNCATE2_TO_REG,
X86ISD::VCVTBIASPH2BF8, X86ISD::VMCVTBIASPH2BF8),
X86_INTRINSIC_DATA(avx10_mask_vcvtbiasph2bf8256, INTR_TYPE_2OP_MASK,
@@ -467,12 +473,42 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
X86ISD::VCVTBIASPH2HF8S, 0),
X86_INTRINSIC_DATA(avx10_mask_vcvtbiasph2hf8s512, INTR_TYPE_2OP_MASK,
X86ISD::VCVTBIASPH2HF8S, 0),
+ X86_INTRINSIC_DATA(avx10_mask_vcvtbiasps2bf8_128, TRUNCATE2_TO_REG,
+ X86ISD::VCVTBIASPS2BF8, X86ISD::VMCVTBIASPS2BF8),
+ X86_INTRINSIC_DATA(avx10_mask_vcvtbiasps2bf8_256, TRUNCATE2_TO_REG,
+ X86ISD::VCVTBIASPS2BF8, X86ISD::VMCVTBIASPS2BF8),
+ X86_INTRINSIC_DATA(avx10_mask_vcvtbiasps2bf8_512, INTR_TYPE_2OP_MASK,
+ X86ISD::VCVTBIASPS2BF8, 0),
+ X86_INTRINSIC_DATA(avx10_mask_vcvtbiasps2bf8s_128, TRUNCATE2_TO_REG,
+ X86ISD::VCVTBIASPS2BF8S, X86ISD::VMCVTBIASPS2BF8S),
+ X86_INTRINSIC_DATA(avx10_mask_vcvtbiasps2bf8s_256, TRUNCATE2_TO_REG,
+ X86ISD::VCVTBIASPS2BF8S, X86ISD::VMCVTBIASPS2BF8S),
+ X86_INTRINSIC_DATA(avx10_mask_vcvtbiasps2bf8s_512, INTR_TYPE_2OP_MASK,
+ X86ISD::VCVTBIASPS2BF8S, 0),
+ X86_INTRINSIC_DATA(avx10_mask_vcvtbiasps2hf8_128, TRUNCATE2_TO_REG,
+ X86ISD::VCVTBIASPS2HF8, X86ISD::VMCVTBIASPS2HF8),
+ X86_INTRINSIC_DATA(avx10_mask_vcvtbiasps2hf8_256, TRUNCATE2_TO_REG,
+ X86ISD::VCVTBIASPS2HF8, X86ISD::VMCVTBIASPS2HF8),
+ X86_INTRINSIC_DATA(avx10_mask_vcvtbiasps2hf8_512, INTR_TYPE_2OP_MASK,
+ X86ISD::VCVTBIASPS2HF8, 0),
+ X86_INTRINSIC_DATA(avx10_mask_vcvtbiasps2hf8s_128, TRUNCATE2_TO_REG,
+ X86ISD::VCVTBIASPS2HF8S, X86ISD::VMCVTBIASPS2HF8S),
+ X86_INTRINSIC_DATA(avx10_mask_vcvtbiasps2hf8s_256, TRUNCATE2_TO_REG,
+ X86ISD::VCVTBIASPS2HF8S, X86ISD::VMCVTBIASPS2HF8S),
+ X86_INTRINSIC_DATA(avx10_mask_vcvtbiasps2hf8s_512, INTR_TYPE_2OP_MASK,
+ X86ISD::VCVTBIASPS2HF8S, 0),
X86_INTRINSIC_DATA(avx10_mask_vcvthf82ph128, INTR_TYPE_1OP_MASK,
X86ISD::VCVTHF82PH, 0),
X86_INTRINSIC_DATA(avx10_mask_vcvthf82ph256, INTR_TYPE_1OP_MASK,
X86ISD::VCVTHF82PH, 0),
X86_INTRINSIC_DATA(avx10_mask_vcvthf82ph512, INTR_TYPE_1OP_MASK,
X86ISD::VCVTHF82PH, 0),
+ X86_INTRINSIC_DATA(avx10_mask_vcvthf82ps_128, INTR_TYPE_1OP_MASK,
+ X86ISD::VCVTHF82PS, 0),
+ X86_INTRINSIC_DATA(avx10_mask_vcvthf82ps_256, INTR_TYPE_1OP_MASK,
+ X86ISD::VCVTHF82PS, 0),
+ X86_INTRINSIC_DATA(avx10_mask_vcvthf82ps_512, INTR_TYPE_1OP_MASK,
+ X86ISD::VCVTHF82PS, 0),
X86_INTRINSIC_DATA(avx10_mask_vcvtph2bf8128, TRUNCATE_TO_REG,
X86ISD::VCVTPH2BF8, X86ISD::VMCVTPH2BF8),
X86_INTRINSIC_DATA(avx10_mask_vcvtph2bf8256, INTR_TYPE_1OP_MASK,
@@ -509,6 +545,30 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
X86ISD::CVTP2IUBS, 0),
X86_INTRINSIC_DATA(avx10_mask_vcvtph2iubs512, INTR_TYPE_1OP_MASK,
X86ISD::CVTP2IUBS, X86ISD::CVTP2IUBS_RND),
+ X86_INTRINSIC_DATA(avx10_mask_vcvtps2bf8_128, TRUNCATE_TO_REG,
+ X86ISD::VCVTPS2BF8, X86ISD::VMCVTPS2BF8),
+ X86_INTRINSIC_DATA(avx10_mask_vcvtps2bf8_256, TRUNCATE_TO_REG,
+ X86ISD::VCVTPS2BF8, X86ISD::VMCVTPS2BF8),
+ X86_INTRINSIC_DATA(avx10_mask_vcvtps2bf8_512, INTR_TYPE_1OP_MASK,
+ X86ISD::VCVTPS2BF8, 0),
+ X86_INTRINSIC_DATA(avx10_mask_vcvtps2bf8s_128, TRUNCATE_TO_REG,
+ X86ISD::VCVTPS2BF8S, X86ISD::VMCVTPS2BF8S),
+ X86_INTRINSIC_DATA(avx10_mask_vcvtps2bf8s_256, TRUNCATE_TO_REG,
+ X86ISD::VCVTPS2BF8S, X86ISD::VMCVTPS2BF8S),
+ X86_INTRINSIC_DATA(avx10_mask_vcvtps2bf8s_512, INTR_TYPE_1OP_MASK,
+ X86ISD::VCVTPS2BF8S, 0),
+ X86_INTRINSIC_DATA(avx10_mask_vcvtps2hf8_128, TRUNCATE_TO_REG,
+ X86ISD::VCVTPS2HF8, X86ISD::VMCVTPS2HF8),
+ X86_INTRINSIC_DATA(avx10_mask_vcvtps2hf8_256, TRUNCATE_TO_REG,
+ X86ISD::VCVTPS2HF8, X86ISD::VMCVTPS2HF8),
+ X86_INTRINSIC_DATA(avx10_mask_vcvtps2hf8_512, INTR_TYPE_1OP_MASK,
+ X86ISD::VCVTPS2HF8, 0),
+ X86_INTRINSIC_DATA(avx10_mask_vcvtps2hf8s_128, TRUNCATE_TO_REG,
+ X86ISD::VCVTPS2HF8S, X86ISD::VMCVTPS2HF8S),
+ X86_INTRINSIC_DATA(avx10_mask_vcvtps2hf8s_256, TRUNCATE_TO_REG,
+ X86ISD::VCVTPS2HF8S, X86ISD::VMCVTPS2HF8S),
+ X86_INTRINSIC_DATA(avx10_mask_vcvtps2hf8s_512, INTR_TYPE_1OP_MASK,
+ X86ISD::VCVTPS2HF8S, 0),
X86_INTRINSIC_DATA(avx10_mask_vcvtps2ibs128, INTR_TYPE_1OP_MASK,
X86ISD::CVTP2IBS, 0),
X86_INTRINSIC_DATA(avx10_mask_vcvtps2ibs256, INTR_TYPE_1OP_MASK,
@@ -521,6 +581,18 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
X86ISD::CVTP2IUBS, 0),
X86_INTRINSIC_DATA(avx10_mask_vcvtps2iubs512, INTR_TYPE_1OP_MASK,
X86ISD::CVTP2IUBS, X86ISD::CVTP2IUBS_RND),
+ X86_INTRINSIC_DATA(avx10_mask_vcvtrops2hf8_128, TRUNCATE_TO_REG,
+ X86ISD::VCVTROPS2HF8, X86ISD::VMCVTROPS2HF8),
+ X86_INTRINSIC_DATA(avx10_mask_vcvtrops2hf8_256, TRUNCATE_TO_REG,
+ X86ISD::VCVTROPS2HF8, X86ISD::VMCVTROPS2HF8),
+ X86_INTRINSIC_DATA(avx10_mask_vcvtrops2hf8_512, INTR_TYPE_1OP_MASK,
+ X86ISD::VCVTROPS2HF8, 0),
+ X86_INTRINSIC_DATA(avx10_mask_vcvtrops2hf8s_128, TRUNCATE_TO_REG,
+ X86ISD::VCVTROPS2HF8S, X86ISD::VMCVTROPS2HF8S),
+ X86_INTRINSIC_DATA(avx10_mask_vcvtrops2hf8s_256, TRUNCATE_TO_REG,
+ X86ISD::VCVTROPS2HF8S, X86ISD::VMCVTROPS2HF8S),
+ X86_INTRINSIC_DATA(avx10_mask_vcvtrops2hf8s_512, INTR_TYPE_1OP_MASK,
+ X86ISD::VCVTROPS2HF8S, 0),
X86_INTRINSIC_DATA(avx10_mask_vcvttpd2dqs_128, CVTPD2DQ_MASK,
X86ISD::CVTTP2SIS, X86ISD::MCVTTP2SIS),
X86_INTRINSIC_DATA(avx10_mask_vcvttpd2dqs_256, INTR_TYPE_1OP_MASK,
diff --git a/llvm/lib/TargetParser/X86TargetParser.cpp b/llvm/lib/TargetParser/X86TargetParser.cpp
index 5d62d4bb8603f..a8f7c01c69427 100644
--- a/llvm/lib/TargetParser/X86TargetParser.cpp
+++ b/llvm/lib/TargetParser/X86TargetParser.cpp
@@ -669,6 +669,7 @@ constexpr FeatureBitset ImpliedFeaturesAVX10_1 =
FeatureAVX512VBMI2 | FeatureAVX512BITALG | FeatureAVX512FP16 |
FeatureAVX512DQ | FeatureAVX512VL;
constexpr FeatureBitset ImpliedFeaturesAVX10_2 = FeatureAVX10_1;
+constexpr FeatureBitset ImpliedFeaturesAVX10_V2_AUX = FeatureAVX10_2;
// APX Features
constexpr FeatureBitset ImpliedFeaturesEGPR = {};
diff --git a/llvm/test/CodeGen/X86/avx10_2_v2aux-intrinsics.ll b/llvm/test/CodeGen/X86/avx10_2_v2aux-intrinsics.ll
new file mode 100644
index 0000000000000..980ba1447d5f3
--- /dev/null
+++ b/llvm/test/CodeGen/X86/avx10_2_v2aux-intrinsics.ll
@@ -0,0 +1,1931 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+avx10-v2-aux | FileCheck %s --check-prefixes=CHECK,X64
+; RUN: llc < %s -verify-machineinstrs -mtriple=i686-unknown-unknown --show-mc-encoding -mattr=+avx10-v2-aux | FileCheck %s --check-prefixes=CHECK,X86
+
+; ===== Group A: 1-operand truncating conversions (PS->i8) =====
+
+; --- vcvtps2bf8 ---
+
+define <16 x i8> @test_int_x86_avx10_vcvtps2bf8_128(<4 x float> %A) {
+; CHECK-LABEL: test_int_x86_avx10_vcvtps2bf8_128:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vcvtps2bf8 %xmm0, %xmm0 # encoding: [0x62,0xf5,0x7e,0x08,0x39,0xc0]
+; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtps2bf8.128(<4 x float> %A, <16 x i8> zeroinitializer, i8 -1)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_vcvtps2bf8_256(<8 x float> %A) {
+; CHECK-LABEL: test_int_x86_avx10_vcvtps2bf8_256:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vcvtps2bf8 %ymm0, %xmm0 # encoding: [0x62,0xf5,0x7e,0x28,0x39,0xc0]
+; CHECK-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtps2bf8.256(<8 x float> %A, <16 x i8> zeroinitializer, i8 -1)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_vcvtps2bf8_512(<16 x float> %A) {
+; CHECK-LABEL: test_int_x86_avx10_vcvtps2bf8_512:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vcvtps2bf8 %zmm0, %xmm0 # encoding: [0x62,0xf5,0x7e,0x48,0x39,0xc0]
+; CHECK-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtps2bf8.512(<16 x float> %A, <16 x i8> zeroinitializer, i16 -1)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_mask_vcvtps2bf8_128(<4 x float> %A, <16 x i8> %B, i8 %C) {
+; X64-LABEL: test_int_x86_avx10_mask_vcvtps2bf8_128:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vcvtps2bf8 %xmm0, %xmm1 {%k1} # encoding: [0x62,0xf5,0x7e,0x09,0x39,0xc8]
+; X64-NEXT: vmovaps %xmm1, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc1]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_mask_vcvtps2bf8_128:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vcvtps2bf8 %xmm0, %xmm1 {%k1} # encoding: [0x62,0xf5,0x7e,0x09,0x39,0xc8]
+; X86-NEXT: vmovaps %xmm1, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc1]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtps2bf8.128(<4 x float> %A, <16 x i8> %B, i8 %C)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_mask_vcvtps2bf8_256(<8 x float> %A, <16 x i8> %B, i8 %C) {
+; X64-LABEL: test_int_x86_avx10_mask_vcvtps2bf8_256:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vcvtps2bf8 %ymm0, %xmm1 {%k1} # encoding: [0x62,0xf5,0x7e,0x29,0x39,0xc8]
+; X64-NEXT: vmovaps %xmm1, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc1]
+; X64-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_mask_vcvtps2bf8_256:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vcvtps2bf8 %ymm0, %xmm1 {%k1} # encoding: [0x62,0xf5,0x7e,0x29,0x39,0xc8]
+; X86-NEXT: vmovaps %xmm1, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc1]
+; X86-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtps2bf8.256(<8 x float> %A, <16 x i8> %B, i8 %C)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_mask_vcvtps2bf8_512(<16 x float> %A, <16 x i8> %B, i16 %C) {
+; X64-LABEL: test_int_x86_avx10_mask_vcvtps2bf8_512:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vcvtps2bf8 %zmm0, %xmm1 {%k1} # encoding: [0x62,0xf5,0x7e,0x49,0x39,0xc8]
+; X64-NEXT: vmovaps %xmm1, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc1]
+; X64-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_mask_vcvtps2bf8_512:
+; X86: # %bb.0:
+; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf8,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vcvtps2bf8 %zmm0, %xmm1 {%k1} # encoding: [0x62,0xf5,0x7e,0x49,0x39,0xc8]
+; X86-NEXT: vmovaps %xmm1, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc1]
+; X86-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtps2bf8.512(<16 x float> %A, <16 x i8> %B, i16 %C)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_maskz_vcvtps2bf8_128(<4 x float> %A, i8 %B) {
+; X64-LABEL: test_int_x86_avx10_maskz_vcvtps2bf8_128:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vcvtps2bf8 %xmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf5,0x7e,0x89,0x39,0xc0]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_maskz_vcvtps2bf8_128:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vcvtps2bf8 %xmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf5,0x7e,0x89,0x39,0xc0]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtps2bf8.128(<4 x float> %A, <16 x i8> zeroinitializer, i8 %B)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_maskz_vcvtps2bf8_256(<8 x float> %A, i8 %B) {
+; X64-LABEL: test_int_x86_avx10_maskz_vcvtps2bf8_256:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vcvtps2bf8 %ymm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf5,0x7e,0xa9,0x39,0xc0]
+; X64-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_maskz_vcvtps2bf8_256:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vcvtps2bf8 %ymm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf5,0x7e,0xa9,0x39,0xc0]
+; X86-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtps2bf8.256(<8 x float> %A, <16 x i8> zeroinitializer, i8 %B)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_maskz_vcvtps2bf8_512(<16 x float> %A, i16 %B) {
+; X64-LABEL: test_int_x86_avx10_maskz_vcvtps2bf8_512:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vcvtps2bf8 %zmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf5,0x7e,0xc9,0x39,0xc0]
+; X64-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_maskz_vcvtps2bf8_512:
+; X86: # %bb.0:
+; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf8,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vcvtps2bf8 %zmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf5,0x7e,0xc9,0x39,0xc0]
+; X86-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtps2bf8.512(<16 x float> %A, <16 x i8> zeroinitializer, i16 %B)
+ ret <16 x i8> %ret
+}
+
+declare <16 x i8> @llvm.x86.avx10.mask.vcvtps2bf8.128(<4 x float>, <16 x i8>, i8)
+declare <16 x i8> @llvm.x86.avx10.mask.vcvtps2bf8.256(<8 x float>, <16 x i8>, i8)
+declare <16 x i8> @llvm.x86.avx10.mask.vcvtps2bf8.512(<16 x float>, <16 x i8>, i16)
+
+; --- vcvtps2bf8s ---
+
+define <16 x i8> @test_int_x86_avx10_vcvtps2bf8s_128(<4 x float> %A) {
+; CHECK-LABEL: test_int_x86_avx10_vcvtps2bf8s_128:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vcvtps2bf8s %xmm0, %xmm0 # encoding: [0x62,0xf5,0x7e,0x08,0x3b,0xc0]
+; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtps2bf8s.128(<4 x float> %A, <16 x i8> zeroinitializer, i8 -1)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_vcvtps2bf8s_256(<8 x float> %A) {
+; CHECK-LABEL: test_int_x86_avx10_vcvtps2bf8s_256:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vcvtps2bf8s %ymm0, %xmm0 # encoding: [0x62,0xf5,0x7e,0x28,0x3b,0xc0]
+; CHECK-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtps2bf8s.256(<8 x float> %A, <16 x i8> zeroinitializer, i8 -1)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_vcvtps2bf8s_512(<16 x float> %A) {
+; CHECK-LABEL: test_int_x86_avx10_vcvtps2bf8s_512:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vcvtps2bf8s %zmm0, %xmm0 # encoding: [0x62,0xf5,0x7e,0x48,0x3b,0xc0]
+; CHECK-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtps2bf8s.512(<16 x float> %A, <16 x i8> zeroinitializer, i16 -1)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_mask_vcvtps2bf8s_128(<4 x float> %A, <16 x i8> %B, i8 %C) {
+; X64-LABEL: test_int_x86_avx10_mask_vcvtps2bf8s_128:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vcvtps2bf8s %xmm0, %xmm1 {%k1} # encoding: [0x62,0xf5,0x7e,0x09,0x3b,0xc8]
+; X64-NEXT: vmovaps %xmm1, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc1]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_mask_vcvtps2bf8s_128:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vcvtps2bf8s %xmm0, %xmm1 {%k1} # encoding: [0x62,0xf5,0x7e,0x09,0x3b,0xc8]
+; X86-NEXT: vmovaps %xmm1, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc1]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtps2bf8s.128(<4 x float> %A, <16 x i8> %B, i8 %C)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_mask_vcvtps2bf8s_256(<8 x float> %A, <16 x i8> %B, i8 %C) {
+; X64-LABEL: test_int_x86_avx10_mask_vcvtps2bf8s_256:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vcvtps2bf8s %ymm0, %xmm1 {%k1} # encoding: [0x62,0xf5,0x7e,0x29,0x3b,0xc8]
+; X64-NEXT: vmovaps %xmm1, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc1]
+; X64-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_mask_vcvtps2bf8s_256:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vcvtps2bf8s %ymm0, %xmm1 {%k1} # encoding: [0x62,0xf5,0x7e,0x29,0x3b,0xc8]
+; X86-NEXT: vmovaps %xmm1, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc1]
+; X86-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtps2bf8s.256(<8 x float> %A, <16 x i8> %B, i8 %C)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_mask_vcvtps2bf8s_512(<16 x float> %A, <16 x i8> %B, i16 %C) {
+; X64-LABEL: test_int_x86_avx10_mask_vcvtps2bf8s_512:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vcvtps2bf8s %zmm0, %xmm1 {%k1} # encoding: [0x62,0xf5,0x7e,0x49,0x3b,0xc8]
+; X64-NEXT: vmovaps %xmm1, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc1]
+; X64-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_mask_vcvtps2bf8s_512:
+; X86: # %bb.0:
+; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf8,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vcvtps2bf8s %zmm0, %xmm1 {%k1} # encoding: [0x62,0xf5,0x7e,0x49,0x3b,0xc8]
+; X86-NEXT: vmovaps %xmm1, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc1]
+; X86-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtps2bf8s.512(<16 x float> %A, <16 x i8> %B, i16 %C)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_maskz_vcvtps2bf8s_128(<4 x float> %A, i8 %B) {
+; X64-LABEL: test_int_x86_avx10_maskz_vcvtps2bf8s_128:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vcvtps2bf8s %xmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf5,0x7e,0x89,0x3b,0xc0]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_maskz_vcvtps2bf8s_128:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vcvtps2bf8s %xmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf5,0x7e,0x89,0x3b,0xc0]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtps2bf8s.128(<4 x float> %A, <16 x i8> zeroinitializer, i8 %B)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_maskz_vcvtps2bf8s_256(<8 x float> %A, i8 %B) {
+; X64-LABEL: test_int_x86_avx10_maskz_vcvtps2bf8s_256:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vcvtps2bf8s %ymm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf5,0x7e,0xa9,0x3b,0xc0]
+; X64-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_maskz_vcvtps2bf8s_256:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vcvtps2bf8s %ymm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf5,0x7e,0xa9,0x3b,0xc0]
+; X86-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtps2bf8s.256(<8 x float> %A, <16 x i8> zeroinitializer, i8 %B)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_maskz_vcvtps2bf8s_512(<16 x float> %A, i16 %B) {
+; X64-LABEL: test_int_x86_avx10_maskz_vcvtps2bf8s_512:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vcvtps2bf8s %zmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf5,0x7e,0xc9,0x3b,0xc0]
+; X64-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_maskz_vcvtps2bf8s_512:
+; X86: # %bb.0:
+; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf8,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vcvtps2bf8s %zmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf5,0x7e,0xc9,0x3b,0xc0]
+; X86-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtps2bf8s.512(<16 x float> %A, <16 x i8> zeroinitializer, i16 %B)
+ ret <16 x i8> %ret
+}
+
+declare <16 x i8> @llvm.x86.avx10.mask.vcvtps2bf8s.128(<4 x float>, <16 x i8>, i8)
+declare <16 x i8> @llvm.x86.avx10.mask.vcvtps2bf8s.256(<8 x float>, <16 x i8>, i8)
+declare <16 x i8> @llvm.x86.avx10.mask.vcvtps2bf8s.512(<16 x float>, <16 x i8>, i16)
+
+; --- vcvtps2hf8 ---
+
+define <16 x i8> @test_int_x86_avx10_vcvtps2hf8_128(<4 x float> %A) {
+; CHECK-LABEL: test_int_x86_avx10_vcvtps2hf8_128:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vcvtps2hf8 %xmm0, %xmm0 # encoding: [0x62,0xf5,0x7e,0x08,0x38,0xc0]
+; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtps2hf8.128(<4 x float> %A, <16 x i8> zeroinitializer, i8 -1)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_vcvtps2hf8_256(<8 x float> %A) {
+; CHECK-LABEL: test_int_x86_avx10_vcvtps2hf8_256:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vcvtps2hf8 %ymm0, %xmm0 # encoding: [0x62,0xf5,0x7e,0x28,0x38,0xc0]
+; CHECK-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtps2hf8.256(<8 x float> %A, <16 x i8> zeroinitializer, i8 -1)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_vcvtps2hf8_512(<16 x float> %A) {
+; CHECK-LABEL: test_int_x86_avx10_vcvtps2hf8_512:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vcvtps2hf8 %zmm0, %xmm0 # encoding: [0x62,0xf5,0x7e,0x48,0x38,0xc0]
+; CHECK-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtps2hf8.512(<16 x float> %A, <16 x i8> zeroinitializer, i16 -1)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_mask_vcvtps2hf8_128(<4 x float> %A, <16 x i8> %B, i8 %C) {
+; X64-LABEL: test_int_x86_avx10_mask_vcvtps2hf8_128:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vcvtps2hf8 %xmm0, %xmm1 {%k1} # encoding: [0x62,0xf5,0x7e,0x09,0x38,0xc8]
+; X64-NEXT: vmovaps %xmm1, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc1]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_mask_vcvtps2hf8_128:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vcvtps2hf8 %xmm0, %xmm1 {%k1} # encoding: [0x62,0xf5,0x7e,0x09,0x38,0xc8]
+; X86-NEXT: vmovaps %xmm1, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc1]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtps2hf8.128(<4 x float> %A, <16 x i8> %B, i8 %C)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_mask_vcvtps2hf8_256(<8 x float> %A, <16 x i8> %B, i8 %C) {
+; X64-LABEL: test_int_x86_avx10_mask_vcvtps2hf8_256:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vcvtps2hf8 %ymm0, %xmm1 {%k1} # encoding: [0x62,0xf5,0x7e,0x29,0x38,0xc8]
+; X64-NEXT: vmovaps %xmm1, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc1]
+; X64-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_mask_vcvtps2hf8_256:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vcvtps2hf8 %ymm0, %xmm1 {%k1} # encoding: [0x62,0xf5,0x7e,0x29,0x38,0xc8]
+; X86-NEXT: vmovaps %xmm1, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc1]
+; X86-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtps2hf8.256(<8 x float> %A, <16 x i8> %B, i8 %C)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_mask_vcvtps2hf8_512(<16 x float> %A, <16 x i8> %B, i16 %C) {
+; X64-LABEL: test_int_x86_avx10_mask_vcvtps2hf8_512:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vcvtps2hf8 %zmm0, %xmm1 {%k1} # encoding: [0x62,0xf5,0x7e,0x49,0x38,0xc8]
+; X64-NEXT: vmovaps %xmm1, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc1]
+; X64-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_mask_vcvtps2hf8_512:
+; X86: # %bb.0:
+; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf8,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vcvtps2hf8 %zmm0, %xmm1 {%k1} # encoding: [0x62,0xf5,0x7e,0x49,0x38,0xc8]
+; X86-NEXT: vmovaps %xmm1, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc1]
+; X86-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtps2hf8.512(<16 x float> %A, <16 x i8> %B, i16 %C)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_maskz_vcvtps2hf8_128(<4 x float> %A, i8 %B) {
+; X64-LABEL: test_int_x86_avx10_maskz_vcvtps2hf8_128:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vcvtps2hf8 %xmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf5,0x7e,0x89,0x38,0xc0]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_maskz_vcvtps2hf8_128:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vcvtps2hf8 %xmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf5,0x7e,0x89,0x38,0xc0]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtps2hf8.128(<4 x float> %A, <16 x i8> zeroinitializer, i8 %B)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_maskz_vcvtps2hf8_256(<8 x float> %A, i8 %B) {
+; X64-LABEL: test_int_x86_avx10_maskz_vcvtps2hf8_256:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vcvtps2hf8 %ymm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf5,0x7e,0xa9,0x38,0xc0]
+; X64-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_maskz_vcvtps2hf8_256:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vcvtps2hf8 %ymm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf5,0x7e,0xa9,0x38,0xc0]
+; X86-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtps2hf8.256(<8 x float> %A, <16 x i8> zeroinitializer, i8 %B)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_maskz_vcvtps2hf8_512(<16 x float> %A, i16 %B) {
+; X64-LABEL: test_int_x86_avx10_maskz_vcvtps2hf8_512:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vcvtps2hf8 %zmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf5,0x7e,0xc9,0x38,0xc0]
+; X64-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_maskz_vcvtps2hf8_512:
+; X86: # %bb.0:
+; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf8,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vcvtps2hf8 %zmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf5,0x7e,0xc9,0x38,0xc0]
+; X86-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtps2hf8.512(<16 x float> %A, <16 x i8> zeroinitializer, i16 %B)
+ ret <16 x i8> %ret
+}
+
+declare <16 x i8> @llvm.x86.avx10.mask.vcvtps2hf8.128(<4 x float>, <16 x i8>, i8)
+declare <16 x i8> @llvm.x86.avx10.mask.vcvtps2hf8.256(<8 x float>, <16 x i8>, i8)
+declare <16 x i8> @llvm.x86.avx10.mask.vcvtps2hf8.512(<16 x float>, <16 x i8>, i16)
+
+; --- vcvtps2hf8s ---
+
+define <16 x i8> @test_int_x86_avx10_vcvtps2hf8s_128(<4 x float> %A) {
+; CHECK-LABEL: test_int_x86_avx10_vcvtps2hf8s_128:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vcvtps2hf8s %xmm0, %xmm0 # encoding: [0x62,0xf5,0x7e,0x08,0x3a,0xc0]
+; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtps2hf8s.128(<4 x float> %A, <16 x i8> zeroinitializer, i8 -1)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_vcvtps2hf8s_256(<8 x float> %A) {
+; CHECK-LABEL: test_int_x86_avx10_vcvtps2hf8s_256:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vcvtps2hf8s %ymm0, %xmm0 # encoding: [0x62,0xf5,0x7e,0x28,0x3a,0xc0]
+; CHECK-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtps2hf8s.256(<8 x float> %A, <16 x i8> zeroinitializer, i8 -1)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_vcvtps2hf8s_512(<16 x float> %A) {
+; CHECK-LABEL: test_int_x86_avx10_vcvtps2hf8s_512:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vcvtps2hf8s %zmm0, %xmm0 # encoding: [0x62,0xf5,0x7e,0x48,0x3a,0xc0]
+; CHECK-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtps2hf8s.512(<16 x float> %A, <16 x i8> zeroinitializer, i16 -1)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_mask_vcvtps2hf8s_128(<4 x float> %A, <16 x i8> %B, i8 %C) {
+; X64-LABEL: test_int_x86_avx10_mask_vcvtps2hf8s_128:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vcvtps2hf8s %xmm0, %xmm1 {%k1} # encoding: [0x62,0xf5,0x7e,0x09,0x3a,0xc8]
+; X64-NEXT: vmovaps %xmm1, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc1]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_mask_vcvtps2hf8s_128:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vcvtps2hf8s %xmm0, %xmm1 {%k1} # encoding: [0x62,0xf5,0x7e,0x09,0x3a,0xc8]
+; X86-NEXT: vmovaps %xmm1, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc1]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtps2hf8s.128(<4 x float> %A, <16 x i8> %B, i8 %C)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_mask_vcvtps2hf8s_256(<8 x float> %A, <16 x i8> %B, i8 %C) {
+; X64-LABEL: test_int_x86_avx10_mask_vcvtps2hf8s_256:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vcvtps2hf8s %ymm0, %xmm1 {%k1} # encoding: [0x62,0xf5,0x7e,0x29,0x3a,0xc8]
+; X64-NEXT: vmovaps %xmm1, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc1]
+; X64-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_mask_vcvtps2hf8s_256:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vcvtps2hf8s %ymm0, %xmm1 {%k1} # encoding: [0x62,0xf5,0x7e,0x29,0x3a,0xc8]
+; X86-NEXT: vmovaps %xmm1, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc1]
+; X86-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtps2hf8s.256(<8 x float> %A, <16 x i8> %B, i8 %C)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_mask_vcvtps2hf8s_512(<16 x float> %A, <16 x i8> %B, i16 %C) {
+; X64-LABEL: test_int_x86_avx10_mask_vcvtps2hf8s_512:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vcvtps2hf8s %zmm0, %xmm1 {%k1} # encoding: [0x62,0xf5,0x7e,0x49,0x3a,0xc8]
+; X64-NEXT: vmovaps %xmm1, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc1]
+; X64-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_mask_vcvtps2hf8s_512:
+; X86: # %bb.0:
+; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf8,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vcvtps2hf8s %zmm0, %xmm1 {%k1} # encoding: [0x62,0xf5,0x7e,0x49,0x3a,0xc8]
+; X86-NEXT: vmovaps %xmm1, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc1]
+; X86-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtps2hf8s.512(<16 x float> %A, <16 x i8> %B, i16 %C)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_maskz_vcvtps2hf8s_128(<4 x float> %A, i8 %B) {
+; X64-LABEL: test_int_x86_avx10_maskz_vcvtps2hf8s_128:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vcvtps2hf8s %xmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf5,0x7e,0x89,0x3a,0xc0]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_maskz_vcvtps2hf8s_128:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vcvtps2hf8s %xmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf5,0x7e,0x89,0x3a,0xc0]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtps2hf8s.128(<4 x float> %A, <16 x i8> zeroinitializer, i8 %B)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_maskz_vcvtps2hf8s_256(<8 x float> %A, i8 %B) {
+; X64-LABEL: test_int_x86_avx10_maskz_vcvtps2hf8s_256:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vcvtps2hf8s %ymm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf5,0x7e,0xa9,0x3a,0xc0]
+; X64-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_maskz_vcvtps2hf8s_256:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vcvtps2hf8s %ymm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf5,0x7e,0xa9,0x3a,0xc0]
+; X86-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtps2hf8s.256(<8 x float> %A, <16 x i8> zeroinitializer, i8 %B)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_maskz_vcvtps2hf8s_512(<16 x float> %A, i16 %B) {
+; X64-LABEL: test_int_x86_avx10_maskz_vcvtps2hf8s_512:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vcvtps2hf8s %zmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf5,0x7e,0xc9,0x3a,0xc0]
+; X64-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_maskz_vcvtps2hf8s_512:
+; X86: # %bb.0:
+; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf8,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vcvtps2hf8s %zmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf5,0x7e,0xc9,0x3a,0xc0]
+; X86-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtps2hf8s.512(<16 x float> %A, <16 x i8> zeroinitializer, i16 %B)
+ ret <16 x i8> %ret
+}
+
+declare <16 x i8> @llvm.x86.avx10.mask.vcvtps2hf8s.128(<4 x float>, <16 x i8>, i8)
+declare <16 x i8> @llvm.x86.avx10.mask.vcvtps2hf8s.256(<8 x float>, <16 x i8>, i8)
+declare <16 x i8> @llvm.x86.avx10.mask.vcvtps2hf8s.512(<16 x float>, <16 x i8>, i16)
+
+; --- vcvtrops2hf8 ---
+
+define <16 x i8> @test_int_x86_avx10_vcvtrops2hf8_128(<4 x float> %A) {
+; CHECK-LABEL: test_int_x86_avx10_vcvtrops2hf8_128:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vcvtrops2hf8 %xmm0, %xmm0 # encoding: [0x62,0xf5,0x7d,0x08,0x38,0xc0]
+; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtrops2hf8.128(<4 x float> %A, <16 x i8> zeroinitializer, i8 -1)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_vcvtrops2hf8_256(<8 x float> %A) {
+; CHECK-LABEL: test_int_x86_avx10_vcvtrops2hf8_256:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vcvtrops2hf8 %ymm0, %xmm0 # encoding: [0x62,0xf5,0x7d,0x28,0x38,0xc0]
+; CHECK-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtrops2hf8.256(<8 x float> %A, <16 x i8> zeroinitializer, i8 -1)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_vcvtrops2hf8_512(<16 x float> %A) {
+; CHECK-LABEL: test_int_x86_avx10_vcvtrops2hf8_512:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vcvtrops2hf8 %zmm0, %xmm0 # encoding: [0x62,0xf5,0x7d,0x48,0x38,0xc0]
+; CHECK-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtrops2hf8.512(<16 x float> %A, <16 x i8> zeroinitializer, i16 -1)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_mask_vcvtrops2hf8_128(<4 x float> %A, <16 x i8> %B, i8 %C) {
+; X64-LABEL: test_int_x86_avx10_mask_vcvtrops2hf8_128:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vcvtrops2hf8 %xmm0, %xmm1 {%k1} # encoding: [0x62,0xf5,0x7d,0x09,0x38,0xc8]
+; X64-NEXT: vmovaps %xmm1, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc1]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_mask_vcvtrops2hf8_128:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vcvtrops2hf8 %xmm0, %xmm1 {%k1} # encoding: [0x62,0xf5,0x7d,0x09,0x38,0xc8]
+; X86-NEXT: vmovaps %xmm1, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc1]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtrops2hf8.128(<4 x float> %A, <16 x i8> %B, i8 %C)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_mask_vcvtrops2hf8_256(<8 x float> %A, <16 x i8> %B, i8 %C) {
+; X64-LABEL: test_int_x86_avx10_mask_vcvtrops2hf8_256:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vcvtrops2hf8 %ymm0, %xmm1 {%k1} # encoding: [0x62,0xf5,0x7d,0x29,0x38,0xc8]
+; X64-NEXT: vmovaps %xmm1, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc1]
+; X64-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_mask_vcvtrops2hf8_256:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vcvtrops2hf8 %ymm0, %xmm1 {%k1} # encoding: [0x62,0xf5,0x7d,0x29,0x38,0xc8]
+; X86-NEXT: vmovaps %xmm1, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc1]
+; X86-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtrops2hf8.256(<8 x float> %A, <16 x i8> %B, i8 %C)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_mask_vcvtrops2hf8_512(<16 x float> %A, <16 x i8> %B, i16 %C) {
+; X64-LABEL: test_int_x86_avx10_mask_vcvtrops2hf8_512:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vcvtrops2hf8 %zmm0, %xmm1 {%k1} # encoding: [0x62,0xf5,0x7d,0x49,0x38,0xc8]
+; X64-NEXT: vmovaps %xmm1, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc1]
+; X64-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_mask_vcvtrops2hf8_512:
+; X86: # %bb.0:
+; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf8,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vcvtrops2hf8 %zmm0, %xmm1 {%k1} # encoding: [0x62,0xf5,0x7d,0x49,0x38,0xc8]
+; X86-NEXT: vmovaps %xmm1, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc1]
+; X86-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtrops2hf8.512(<16 x float> %A, <16 x i8> %B, i16 %C)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_maskz_vcvtrops2hf8_128(<4 x float> %A, i8 %B) {
+; X64-LABEL: test_int_x86_avx10_maskz_vcvtrops2hf8_128:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vcvtrops2hf8 %xmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf5,0x7d,0x89,0x38,0xc0]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_maskz_vcvtrops2hf8_128:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vcvtrops2hf8 %xmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf5,0x7d,0x89,0x38,0xc0]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtrops2hf8.128(<4 x float> %A, <16 x i8> zeroinitializer, i8 %B)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_maskz_vcvtrops2hf8_256(<8 x float> %A, i8 %B) {
+; X64-LABEL: test_int_x86_avx10_maskz_vcvtrops2hf8_256:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vcvtrops2hf8 %ymm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf5,0x7d,0xa9,0x38,0xc0]
+; X64-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_maskz_vcvtrops2hf8_256:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vcvtrops2hf8 %ymm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf5,0x7d,0xa9,0x38,0xc0]
+; X86-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtrops2hf8.256(<8 x float> %A, <16 x i8> zeroinitializer, i8 %B)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_maskz_vcvtrops2hf8_512(<16 x float> %A, i16 %B) {
+; X64-LABEL: test_int_x86_avx10_maskz_vcvtrops2hf8_512:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vcvtrops2hf8 %zmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf5,0x7d,0xc9,0x38,0xc0]
+; X64-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_maskz_vcvtrops2hf8_512:
+; X86: # %bb.0:
+; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf8,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vcvtrops2hf8 %zmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf5,0x7d,0xc9,0x38,0xc0]
+; X86-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtrops2hf8.512(<16 x float> %A, <16 x i8> zeroinitializer, i16 %B)
+ ret <16 x i8> %ret
+}
+
+declare <16 x i8> @llvm.x86.avx10.mask.vcvtrops2hf8.128(<4 x float>, <16 x i8>, i8)
+declare <16 x i8> @llvm.x86.avx10.mask.vcvtrops2hf8.256(<8 x float>, <16 x i8>, i8)
+declare <16 x i8> @llvm.x86.avx10.mask.vcvtrops2hf8.512(<16 x float>, <16 x i8>, i16)
+
+; --- vcvtrops2hf8s ---
+
+define <16 x i8> @test_int_x86_avx10_vcvtrops2hf8s_128(<4 x float> %A) {
+; CHECK-LABEL: test_int_x86_avx10_vcvtrops2hf8s_128:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vcvtrops2hf8s %xmm0, %xmm0 # encoding: [0x62,0xf5,0x7d,0x08,0x3a,0xc0]
+; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtrops2hf8s.128(<4 x float> %A, <16 x i8> zeroinitializer, i8 -1)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_vcvtrops2hf8s_256(<8 x float> %A) {
+; CHECK-LABEL: test_int_x86_avx10_vcvtrops2hf8s_256:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vcvtrops2hf8s %ymm0, %xmm0 # encoding: [0x62,0xf5,0x7d,0x28,0x3a,0xc0]
+; CHECK-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtrops2hf8s.256(<8 x float> %A, <16 x i8> zeroinitializer, i8 -1)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_vcvtrops2hf8s_512(<16 x float> %A) {
+; CHECK-LABEL: test_int_x86_avx10_vcvtrops2hf8s_512:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vcvtrops2hf8s %zmm0, %xmm0 # encoding: [0x62,0xf5,0x7d,0x48,0x3a,0xc0]
+; CHECK-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtrops2hf8s.512(<16 x float> %A, <16 x i8> zeroinitializer, i16 -1)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_mask_vcvtrops2hf8s_128(<4 x float> %A, <16 x i8> %B, i8 %C) {
+; X64-LABEL: test_int_x86_avx10_mask_vcvtrops2hf8s_128:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vcvtrops2hf8s %xmm0, %xmm1 {%k1} # encoding: [0x62,0xf5,0x7d,0x09,0x3a,0xc8]
+; X64-NEXT: vmovaps %xmm1, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc1]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_mask_vcvtrops2hf8s_128:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vcvtrops2hf8s %xmm0, %xmm1 {%k1} # encoding: [0x62,0xf5,0x7d,0x09,0x3a,0xc8]
+; X86-NEXT: vmovaps %xmm1, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc1]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtrops2hf8s.128(<4 x float> %A, <16 x i8> %B, i8 %C)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_mask_vcvtrops2hf8s_256(<8 x float> %A, <16 x i8> %B, i8 %C) {
+; X64-LABEL: test_int_x86_avx10_mask_vcvtrops2hf8s_256:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vcvtrops2hf8s %ymm0, %xmm1 {%k1} # encoding: [0x62,0xf5,0x7d,0x29,0x3a,0xc8]
+; X64-NEXT: vmovaps %xmm1, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc1]
+; X64-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_mask_vcvtrops2hf8s_256:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vcvtrops2hf8s %ymm0, %xmm1 {%k1} # encoding: [0x62,0xf5,0x7d,0x29,0x3a,0xc8]
+; X86-NEXT: vmovaps %xmm1, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc1]
+; X86-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtrops2hf8s.256(<8 x float> %A, <16 x i8> %B, i8 %C)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_mask_vcvtrops2hf8s_512(<16 x float> %A, <16 x i8> %B, i16 %C) {
+; X64-LABEL: test_int_x86_avx10_mask_vcvtrops2hf8s_512:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vcvtrops2hf8s %zmm0, %xmm1 {%k1} # encoding: [0x62,0xf5,0x7d,0x49,0x3a,0xc8]
+; X64-NEXT: vmovaps %xmm1, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc1]
+; X64-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_mask_vcvtrops2hf8s_512:
+; X86: # %bb.0:
+; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf8,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vcvtrops2hf8s %zmm0, %xmm1 {%k1} # encoding: [0x62,0xf5,0x7d,0x49,0x3a,0xc8]
+; X86-NEXT: vmovaps %xmm1, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc1]
+; X86-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtrops2hf8s.512(<16 x float> %A, <16 x i8> %B, i16 %C)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_maskz_vcvtrops2hf8s_128(<4 x float> %A, i8 %B) {
+; X64-LABEL: test_int_x86_avx10_maskz_vcvtrops2hf8s_128:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vcvtrops2hf8s %xmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf5,0x7d,0x89,0x3a,0xc0]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_maskz_vcvtrops2hf8s_128:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vcvtrops2hf8s %xmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf5,0x7d,0x89,0x3a,0xc0]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtrops2hf8s.128(<4 x float> %A, <16 x i8> zeroinitializer, i8 %B)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_maskz_vcvtrops2hf8s_256(<8 x float> %A, i8 %B) {
+; X64-LABEL: test_int_x86_avx10_maskz_vcvtrops2hf8s_256:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vcvtrops2hf8s %ymm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf5,0x7d,0xa9,0x3a,0xc0]
+; X64-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_maskz_vcvtrops2hf8s_256:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vcvtrops2hf8s %ymm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf5,0x7d,0xa9,0x3a,0xc0]
+; X86-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtrops2hf8s.256(<8 x float> %A, <16 x i8> zeroinitializer, i8 %B)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_maskz_vcvtrops2hf8s_512(<16 x float> %A, i16 %B) {
+; X64-LABEL: test_int_x86_avx10_maskz_vcvtrops2hf8s_512:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vcvtrops2hf8s %zmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf5,0x7d,0xc9,0x3a,0xc0]
+; X64-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_maskz_vcvtrops2hf8s_512:
+; X86: # %bb.0:
+; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf8,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vcvtrops2hf8s %zmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf5,0x7d,0xc9,0x3a,0xc0]
+; X86-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtrops2hf8s.512(<16 x float> %A, <16 x i8> zeroinitializer, i16 %B)
+ ret <16 x i8> %ret
+}
+
+declare <16 x i8> @llvm.x86.avx10.mask.vcvtrops2hf8s.128(<4 x float>, <16 x i8>, i8)
+declare <16 x i8> @llvm.x86.avx10.mask.vcvtrops2hf8s.256(<8 x float>, <16 x i8>, i8)
+declare <16 x i8> @llvm.x86.avx10.mask.vcvtrops2hf8s.512(<16 x float>, <16 x i8>, i16)
+
+; ===== Group B: 3-operand bias conversions (bias+PS->i8) =====
+
+; --- vcvtbiasps2bf8 ---
+
+define <16 x i8> @test_int_x86_avx10_vcvtbiasps2bf8_128(<16 x i8> %A, <4 x float> %B) {
+; CHECK-LABEL: test_int_x86_avx10_vcvtbiasps2bf8_128:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vcvtbiasps2bf8 %xmm1, %xmm0, %xmm0 # encoding: [0x62,0xf5,0x7c,0x08,0x39,0xc1]
+; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2bf8.128(<16 x i8> %A, <4 x float> %B, <16 x i8> zeroinitializer, i8 -1)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_vcvtbiasps2bf8_256(<32 x i8> %A, <8 x float> %B) {
+; CHECK-LABEL: test_int_x86_avx10_vcvtbiasps2bf8_256:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vcvtbiasps2bf8 %ymm1, %ymm0, %xmm0 # encoding: [0x62,0xf5,0x7c,0x28,0x39,0xc1]
+; CHECK-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2bf8.256(<32 x i8> %A, <8 x float> %B, <16 x i8> zeroinitializer, i8 -1)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_vcvtbiasps2bf8_512(<64 x i8> %A, <16 x float> %B) {
+; CHECK-LABEL: test_int_x86_avx10_vcvtbiasps2bf8_512:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vcvtbiasps2bf8 %zmm1, %zmm0, %xmm0 # encoding: [0x62,0xf5,0x7c,0x48,0x39,0xc1]
+; CHECK-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2bf8.512(<64 x i8> %A, <16 x float> %B, <16 x i8> zeroinitializer, i16 -1)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_mask_vcvtbiasps2bf8_128(<16 x i8> %A, <4 x float> %B, <16 x i8> %C, i8 %D) {
+; X64-LABEL: test_int_x86_avx10_mask_vcvtbiasps2bf8_128:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vcvtbiasps2bf8 %xmm1, %xmm0, %xmm2 {%k1} # encoding: [0x62,0xf5,0x7c,0x09,0x39,0xd1]
+; X64-NEXT: vmovaps %xmm2, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc2]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_mask_vcvtbiasps2bf8_128:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vcvtbiasps2bf8 %xmm1, %xmm0, %xmm2 {%k1} # encoding: [0x62,0xf5,0x7c,0x09,0x39,0xd1]
+; X86-NEXT: vmovaps %xmm2, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc2]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2bf8.128(<16 x i8> %A, <4 x float> %B, <16 x i8> %C, i8 %D)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_mask_vcvtbiasps2bf8_256(<32 x i8> %A, <8 x float> %B, <16 x i8> %C, i8 %D) {
+; X64-LABEL: test_int_x86_avx10_mask_vcvtbiasps2bf8_256:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vcvtbiasps2bf8 %ymm1, %ymm0, %xmm2 {%k1} # encoding: [0x62,0xf5,0x7c,0x29,0x39,0xd1]
+; X64-NEXT: vmovaps %xmm2, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc2]
+; X64-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_mask_vcvtbiasps2bf8_256:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vcvtbiasps2bf8 %ymm1, %ymm0, %xmm2 {%k1} # encoding: [0x62,0xf5,0x7c,0x29,0x39,0xd1]
+; X86-NEXT: vmovaps %xmm2, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc2]
+; X86-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2bf8.256(<32 x i8> %A, <8 x float> %B, <16 x i8> %C, i8 %D)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_mask_vcvtbiasps2bf8_512(<64 x i8> %A, <16 x float> %B, <16 x i8> %C, i16 %D) {
+; X64-LABEL: test_int_x86_avx10_mask_vcvtbiasps2bf8_512:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vcvtbiasps2bf8 %zmm1, %zmm0, %xmm2 {%k1} # encoding: [0x62,0xf5,0x7c,0x49,0x39,0xd1]
+; X64-NEXT: vmovaps %xmm2, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc2]
+; X64-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_mask_vcvtbiasps2bf8_512:
+; X86: # %bb.0:
+; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf8,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vcvtbiasps2bf8 %zmm1, %zmm0, %xmm2 {%k1} # encoding: [0x62,0xf5,0x7c,0x49,0x39,0xd1]
+; X86-NEXT: vmovaps %xmm2, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc2]
+; X86-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2bf8.512(<64 x i8> %A, <16 x float> %B, <16 x i8> %C, i16 %D)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_maskz_vcvtbiasps2bf8_128(<16 x i8> %A, <4 x float> %B, i8 %C) {
+; X64-LABEL: test_int_x86_avx10_maskz_vcvtbiasps2bf8_128:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vcvtbiasps2bf8 %xmm1, %xmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf5,0x7c,0x89,0x39,0xc1]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_maskz_vcvtbiasps2bf8_128:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vcvtbiasps2bf8 %xmm1, %xmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf5,0x7c,0x89,0x39,0xc1]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2bf8.128(<16 x i8> %A, <4 x float> %B, <16 x i8> zeroinitializer, i8 %C)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_maskz_vcvtbiasps2bf8_256(<32 x i8> %A, <8 x float> %B, i8 %C) {
+; X64-LABEL: test_int_x86_avx10_maskz_vcvtbiasps2bf8_256:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vcvtbiasps2bf8 %ymm1, %ymm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf5,0x7c,0xa9,0x39,0xc1]
+; X64-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_maskz_vcvtbiasps2bf8_256:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vcvtbiasps2bf8 %ymm1, %ymm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf5,0x7c,0xa9,0x39,0xc1]
+; X86-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2bf8.256(<32 x i8> %A, <8 x float> %B, <16 x i8> zeroinitializer, i8 %C)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_maskz_vcvtbiasps2bf8_512(<64 x i8> %A, <16 x float> %B, i16 %C) {
+; X64-LABEL: test_int_x86_avx10_maskz_vcvtbiasps2bf8_512:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vcvtbiasps2bf8 %zmm1, %zmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf5,0x7c,0xc9,0x39,0xc1]
+; X64-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_maskz_vcvtbiasps2bf8_512:
+; X86: # %bb.0:
+; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf8,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vcvtbiasps2bf8 %zmm1, %zmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf5,0x7c,0xc9,0x39,0xc1]
+; X86-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2bf8.512(<64 x i8> %A, <16 x float> %B, <16 x i8> zeroinitializer, i16 %C)
+ ret <16 x i8> %ret
+}
+
+declare <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2bf8.128(<16 x i8>, <4 x float>, <16 x i8>, i8)
+declare <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2bf8.256(<32 x i8>, <8 x float>, <16 x i8>, i8)
+declare <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2bf8.512(<64 x i8>, <16 x float>, <16 x i8>, i16)
+
+; --- vcvtbiasps2bf8s ---
+
+define <16 x i8> @test_int_x86_avx10_vcvtbiasps2bf8s_128(<16 x i8> %A, <4 x float> %B) {
+; CHECK-LABEL: test_int_x86_avx10_vcvtbiasps2bf8s_128:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vcvtbiasps2bf8s %xmm1, %xmm0, %xmm0 # encoding: [0x62,0xf5,0x7c,0x08,0x3b,0xc1]
+; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2bf8s.128(<16 x i8> %A, <4 x float> %B, <16 x i8> zeroinitializer, i8 -1)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_vcvtbiasps2bf8s_256(<32 x i8> %A, <8 x float> %B) {
+; CHECK-LABEL: test_int_x86_avx10_vcvtbiasps2bf8s_256:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vcvtbiasps2bf8s %ymm1, %ymm0, %xmm0 # encoding: [0x62,0xf5,0x7c,0x28,0x3b,0xc1]
+; CHECK-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2bf8s.256(<32 x i8> %A, <8 x float> %B, <16 x i8> zeroinitializer, i8 -1)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_vcvtbiasps2bf8s_512(<64 x i8> %A, <16 x float> %B) {
+; CHECK-LABEL: test_int_x86_avx10_vcvtbiasps2bf8s_512:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vcvtbiasps2bf8s %zmm1, %zmm0, %xmm0 # encoding: [0x62,0xf5,0x7c,0x48,0x3b,0xc1]
+; CHECK-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2bf8s.512(<64 x i8> %A, <16 x float> %B, <16 x i8> zeroinitializer, i16 -1)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_mask_vcvtbiasps2bf8s_128(<16 x i8> %A, <4 x float> %B, <16 x i8> %C, i8 %D) {
+; X64-LABEL: test_int_x86_avx10_mask_vcvtbiasps2bf8s_128:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vcvtbiasps2bf8s %xmm1, %xmm0, %xmm2 {%k1} # encoding: [0x62,0xf5,0x7c,0x09,0x3b,0xd1]
+; X64-NEXT: vmovaps %xmm2, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc2]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_mask_vcvtbiasps2bf8s_128:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vcvtbiasps2bf8s %xmm1, %xmm0, %xmm2 {%k1} # encoding: [0x62,0xf5,0x7c,0x09,0x3b,0xd1]
+; X86-NEXT: vmovaps %xmm2, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc2]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2bf8s.128(<16 x i8> %A, <4 x float> %B, <16 x i8> %C, i8 %D)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_mask_vcvtbiasps2bf8s_256(<32 x i8> %A, <8 x float> %B, <16 x i8> %C, i8 %D) {
+; X64-LABEL: test_int_x86_avx10_mask_vcvtbiasps2bf8s_256:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vcvtbiasps2bf8s %ymm1, %ymm0, %xmm2 {%k1} # encoding: [0x62,0xf5,0x7c,0x29,0x3b,0xd1]
+; X64-NEXT: vmovaps %xmm2, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc2]
+; X64-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_mask_vcvtbiasps2bf8s_256:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vcvtbiasps2bf8s %ymm1, %ymm0, %xmm2 {%k1} # encoding: [0x62,0xf5,0x7c,0x29,0x3b,0xd1]
+; X86-NEXT: vmovaps %xmm2, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc2]
+; X86-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2bf8s.256(<32 x i8> %A, <8 x float> %B, <16 x i8> %C, i8 %D)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_mask_vcvtbiasps2bf8s_512(<64 x i8> %A, <16 x float> %B, <16 x i8> %C, i16 %D) {
+; X64-LABEL: test_int_x86_avx10_mask_vcvtbiasps2bf8s_512:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vcvtbiasps2bf8s %zmm1, %zmm0, %xmm2 {%k1} # encoding: [0x62,0xf5,0x7c,0x49,0x3b,0xd1]
+; X64-NEXT: vmovaps %xmm2, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc2]
+; X64-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_mask_vcvtbiasps2bf8s_512:
+; X86: # %bb.0:
+; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf8,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vcvtbiasps2bf8s %zmm1, %zmm0, %xmm2 {%k1} # encoding: [0x62,0xf5,0x7c,0x49,0x3b,0xd1]
+; X86-NEXT: vmovaps %xmm2, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc2]
+; X86-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2bf8s.512(<64 x i8> %A, <16 x float> %B, <16 x i8> %C, i16 %D)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_maskz_vcvtbiasps2bf8s_128(<16 x i8> %A, <4 x float> %B, i8 %C) {
+; X64-LABEL: test_int_x86_avx10_maskz_vcvtbiasps2bf8s_128:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vcvtbiasps2bf8s %xmm1, %xmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf5,0x7c,0x89,0x3b,0xc1]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_maskz_vcvtbiasps2bf8s_128:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vcvtbiasps2bf8s %xmm1, %xmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf5,0x7c,0x89,0x3b,0xc1]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2bf8s.128(<16 x i8> %A, <4 x float> %B, <16 x i8> zeroinitializer, i8 %C)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_maskz_vcvtbiasps2bf8s_256(<32 x i8> %A, <8 x float> %B, i8 %C) {
+; X64-LABEL: test_int_x86_avx10_maskz_vcvtbiasps2bf8s_256:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vcvtbiasps2bf8s %ymm1, %ymm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf5,0x7c,0xa9,0x3b,0xc1]
+; X64-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_maskz_vcvtbiasps2bf8s_256:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vcvtbiasps2bf8s %ymm1, %ymm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf5,0x7c,0xa9,0x3b,0xc1]
+; X86-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2bf8s.256(<32 x i8> %A, <8 x float> %B, <16 x i8> zeroinitializer, i8 %C)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_maskz_vcvtbiasps2bf8s_512(<64 x i8> %A, <16 x float> %B, i16 %C) {
+; X64-LABEL: test_int_x86_avx10_maskz_vcvtbiasps2bf8s_512:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vcvtbiasps2bf8s %zmm1, %zmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf5,0x7c,0xc9,0x3b,0xc1]
+; X64-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_maskz_vcvtbiasps2bf8s_512:
+; X86: # %bb.0:
+; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf8,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vcvtbiasps2bf8s %zmm1, %zmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf5,0x7c,0xc9,0x3b,0xc1]
+; X86-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2bf8s.512(<64 x i8> %A, <16 x float> %B, <16 x i8> zeroinitializer, i16 %C)
+ ret <16 x i8> %ret
+}
+
+declare <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2bf8s.128(<16 x i8>, <4 x float>, <16 x i8>, i8)
+declare <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2bf8s.256(<32 x i8>, <8 x float>, <16 x i8>, i8)
+declare <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2bf8s.512(<64 x i8>, <16 x float>, <16 x i8>, i16)
+
+; --- vcvtbiasps2hf8 ---
+
+define <16 x i8> @test_int_x86_avx10_vcvtbiasps2hf8_128(<16 x i8> %A, <4 x float> %B) {
+; CHECK-LABEL: test_int_x86_avx10_vcvtbiasps2hf8_128:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vcvtbiasps2hf8 %xmm1, %xmm0, %xmm0 # encoding: [0x62,0xf5,0x7c,0x08,0x38,0xc1]
+; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2hf8.128(<16 x i8> %A, <4 x float> %B, <16 x i8> zeroinitializer, i8 -1)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_vcvtbiasps2hf8_256(<32 x i8> %A, <8 x float> %B) {
+; CHECK-LABEL: test_int_x86_avx10_vcvtbiasps2hf8_256:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vcvtbiasps2hf8 %ymm1, %ymm0, %xmm0 # encoding: [0x62,0xf5,0x7c,0x28,0x38,0xc1]
+; CHECK-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2hf8.256(<32 x i8> %A, <8 x float> %B, <16 x i8> zeroinitializer, i8 -1)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_vcvtbiasps2hf8_512(<64 x i8> %A, <16 x float> %B) {
+; CHECK-LABEL: test_int_x86_avx10_vcvtbiasps2hf8_512:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vcvtbiasps2hf8 %zmm1, %zmm0, %xmm0 # encoding: [0x62,0xf5,0x7c,0x48,0x38,0xc1]
+; CHECK-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2hf8.512(<64 x i8> %A, <16 x float> %B, <16 x i8> zeroinitializer, i16 -1)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_mask_vcvtbiasps2hf8_128(<16 x i8> %A, <4 x float> %B, <16 x i8> %C, i8 %D) {
+; X64-LABEL: test_int_x86_avx10_mask_vcvtbiasps2hf8_128:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vcvtbiasps2hf8 %xmm1, %xmm0, %xmm2 {%k1} # encoding: [0x62,0xf5,0x7c,0x09,0x38,0xd1]
+; X64-NEXT: vmovaps %xmm2, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc2]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_mask_vcvtbiasps2hf8_128:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vcvtbiasps2hf8 %xmm1, %xmm0, %xmm2 {%k1} # encoding: [0x62,0xf5,0x7c,0x09,0x38,0xd1]
+; X86-NEXT: vmovaps %xmm2, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc2]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2hf8.128(<16 x i8> %A, <4 x float> %B, <16 x i8> %C, i8 %D)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_mask_vcvtbiasps2hf8_256(<32 x i8> %A, <8 x float> %B, <16 x i8> %C, i8 %D) {
+; X64-LABEL: test_int_x86_avx10_mask_vcvtbiasps2hf8_256:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vcvtbiasps2hf8 %ymm1, %ymm0, %xmm2 {%k1} # encoding: [0x62,0xf5,0x7c,0x29,0x38,0xd1]
+; X64-NEXT: vmovaps %xmm2, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc2]
+; X64-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_mask_vcvtbiasps2hf8_256:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vcvtbiasps2hf8 %ymm1, %ymm0, %xmm2 {%k1} # encoding: [0x62,0xf5,0x7c,0x29,0x38,0xd1]
+; X86-NEXT: vmovaps %xmm2, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc2]
+; X86-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2hf8.256(<32 x i8> %A, <8 x float> %B, <16 x i8> %C, i8 %D)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_mask_vcvtbiasps2hf8_512(<64 x i8> %A, <16 x float> %B, <16 x i8> %C, i16 %D) {
+; X64-LABEL: test_int_x86_avx10_mask_vcvtbiasps2hf8_512:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vcvtbiasps2hf8 %zmm1, %zmm0, %xmm2 {%k1} # encoding: [0x62,0xf5,0x7c,0x49,0x38,0xd1]
+; X64-NEXT: vmovaps %xmm2, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc2]
+; X64-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_mask_vcvtbiasps2hf8_512:
+; X86: # %bb.0:
+; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf8,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vcvtbiasps2hf8 %zmm1, %zmm0, %xmm2 {%k1} # encoding: [0x62,0xf5,0x7c,0x49,0x38,0xd1]
+; X86-NEXT: vmovaps %xmm2, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc2]
+; X86-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2hf8.512(<64 x i8> %A, <16 x float> %B, <16 x i8> %C, i16 %D)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_maskz_vcvtbiasps2hf8_128(<16 x i8> %A, <4 x float> %B, i8 %C) {
+; X64-LABEL: test_int_x86_avx10_maskz_vcvtbiasps2hf8_128:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vcvtbiasps2hf8 %xmm1, %xmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf5,0x7c,0x89,0x38,0xc1]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_maskz_vcvtbiasps2hf8_128:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vcvtbiasps2hf8 %xmm1, %xmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf5,0x7c,0x89,0x38,0xc1]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2hf8.128(<16 x i8> %A, <4 x float> %B, <16 x i8> zeroinitializer, i8 %C)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_maskz_vcvtbiasps2hf8_256(<32 x i8> %A, <8 x float> %B, i8 %C) {
+; X64-LABEL: test_int_x86_avx10_maskz_vcvtbiasps2hf8_256:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vcvtbiasps2hf8 %ymm1, %ymm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf5,0x7c,0xa9,0x38,0xc1]
+; X64-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_maskz_vcvtbiasps2hf8_256:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vcvtbiasps2hf8 %ymm1, %ymm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf5,0x7c,0xa9,0x38,0xc1]
+; X86-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2hf8.256(<32 x i8> %A, <8 x float> %B, <16 x i8> zeroinitializer, i8 %C)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_maskz_vcvtbiasps2hf8_512(<64 x i8> %A, <16 x float> %B, i16 %C) {
+; X64-LABEL: test_int_x86_avx10_maskz_vcvtbiasps2hf8_512:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vcvtbiasps2hf8 %zmm1, %zmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf5,0x7c,0xc9,0x38,0xc1]
+; X64-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_maskz_vcvtbiasps2hf8_512:
+; X86: # %bb.0:
+; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf8,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vcvtbiasps2hf8 %zmm1, %zmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf5,0x7c,0xc9,0x38,0xc1]
+; X86-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2hf8.512(<64 x i8> %A, <16 x float> %B, <16 x i8> zeroinitializer, i16 %C)
+ ret <16 x i8> %ret
+}
+
+declare <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2hf8.128(<16 x i8>, <4 x float>, <16 x i8>, i8)
+declare <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2hf8.256(<32 x i8>, <8 x float>, <16 x i8>, i8)
+declare <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2hf8.512(<64 x i8>, <16 x float>, <16 x i8>, i16)
+
+; --- vcvtbiasps2hf8s ---
+
+define <16 x i8> @test_int_x86_avx10_vcvtbiasps2hf8s_128(<16 x i8> %A, <4 x float> %B) {
+; CHECK-LABEL: test_int_x86_avx10_vcvtbiasps2hf8s_128:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vcvtbiasps2hf8s %xmm1, %xmm0, %xmm0 # encoding: [0x62,0xf5,0x7c,0x08,0x3a,0xc1]
+; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2hf8s.128(<16 x i8> %A, <4 x float> %B, <16 x i8> zeroinitializer, i8 -1)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_vcvtbiasps2hf8s_256(<32 x i8> %A, <8 x float> %B) {
+; CHECK-LABEL: test_int_x86_avx10_vcvtbiasps2hf8s_256:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vcvtbiasps2hf8s %ymm1, %ymm0, %xmm0 # encoding: [0x62,0xf5,0x7c,0x28,0x3a,0xc1]
+; CHECK-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2hf8s.256(<32 x i8> %A, <8 x float> %B, <16 x i8> zeroinitializer, i8 -1)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_vcvtbiasps2hf8s_512(<64 x i8> %A, <16 x float> %B) {
+; CHECK-LABEL: test_int_x86_avx10_vcvtbiasps2hf8s_512:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vcvtbiasps2hf8s %zmm1, %zmm0, %xmm0 # encoding: [0x62,0xf5,0x7c,0x48,0x3a,0xc1]
+; CHECK-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2hf8s.512(<64 x i8> %A, <16 x float> %B, <16 x i8> zeroinitializer, i16 -1)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_mask_vcvtbiasps2hf8s_128(<16 x i8> %A, <4 x float> %B, <16 x i8> %C, i8 %D) {
+; X64-LABEL: test_int_x86_avx10_mask_vcvtbiasps2hf8s_128:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vcvtbiasps2hf8s %xmm1, %xmm0, %xmm2 {%k1} # encoding: [0x62,0xf5,0x7c,0x09,0x3a,0xd1]
+; X64-NEXT: vmovaps %xmm2, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc2]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_mask_vcvtbiasps2hf8s_128:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vcvtbiasps2hf8s %xmm1, %xmm0, %xmm2 {%k1} # encoding: [0x62,0xf5,0x7c,0x09,0x3a,0xd1]
+; X86-NEXT: vmovaps %xmm2, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc2]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2hf8s.128(<16 x i8> %A, <4 x float> %B, <16 x i8> %C, i8 %D)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_mask_vcvtbiasps2hf8s_256(<32 x i8> %A, <8 x float> %B, <16 x i8> %C, i8 %D) {
+; X64-LABEL: test_int_x86_avx10_mask_vcvtbiasps2hf8s_256:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vcvtbiasps2hf8s %ymm1, %ymm0, %xmm2 {%k1} # encoding: [0x62,0xf5,0x7c,0x29,0x3a,0xd1]
+; X64-NEXT: vmovaps %xmm2, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc2]
+; X64-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_mask_vcvtbiasps2hf8s_256:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vcvtbiasps2hf8s %ymm1, %ymm0, %xmm2 {%k1} # encoding: [0x62,0xf5,0x7c,0x29,0x3a,0xd1]
+; X86-NEXT: vmovaps %xmm2, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc2]
+; X86-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2hf8s.256(<32 x i8> %A, <8 x float> %B, <16 x i8> %C, i8 %D)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_mask_vcvtbiasps2hf8s_512(<64 x i8> %A, <16 x float> %B, <16 x i8> %C, i16 %D) {
+; X64-LABEL: test_int_x86_avx10_mask_vcvtbiasps2hf8s_512:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vcvtbiasps2hf8s %zmm1, %zmm0, %xmm2 {%k1} # encoding: [0x62,0xf5,0x7c,0x49,0x3a,0xd1]
+; X64-NEXT: vmovaps %xmm2, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc2]
+; X64-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_mask_vcvtbiasps2hf8s_512:
+; X86: # %bb.0:
+; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf8,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vcvtbiasps2hf8s %zmm1, %zmm0, %xmm2 {%k1} # encoding: [0x62,0xf5,0x7c,0x49,0x3a,0xd1]
+; X86-NEXT: vmovaps %xmm2, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc2]
+; X86-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2hf8s.512(<64 x i8> %A, <16 x float> %B, <16 x i8> %C, i16 %D)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_maskz_vcvtbiasps2hf8s_128(<16 x i8> %A, <4 x float> %B, i8 %C) {
+; X64-LABEL: test_int_x86_avx10_maskz_vcvtbiasps2hf8s_128:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vcvtbiasps2hf8s %xmm1, %xmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf5,0x7c,0x89,0x3a,0xc1]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_maskz_vcvtbiasps2hf8s_128:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vcvtbiasps2hf8s %xmm1, %xmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf5,0x7c,0x89,0x3a,0xc1]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2hf8s.128(<16 x i8> %A, <4 x float> %B, <16 x i8> zeroinitializer, i8 %C)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_maskz_vcvtbiasps2hf8s_256(<32 x i8> %A, <8 x float> %B, i8 %C) {
+; X64-LABEL: test_int_x86_avx10_maskz_vcvtbiasps2hf8s_256:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vcvtbiasps2hf8s %ymm1, %ymm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf5,0x7c,0xa9,0x3a,0xc1]
+; X64-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_maskz_vcvtbiasps2hf8s_256:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vcvtbiasps2hf8s %ymm1, %ymm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf5,0x7c,0xa9,0x3a,0xc1]
+; X86-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2hf8s.256(<32 x i8> %A, <8 x float> %B, <16 x i8> zeroinitializer, i8 %C)
+ ret <16 x i8> %ret
+}
+
+define <16 x i8> @test_int_x86_avx10_maskz_vcvtbiasps2hf8s_512(<64 x i8> %A, <16 x float> %B, i16 %C) {
+; X64-LABEL: test_int_x86_avx10_maskz_vcvtbiasps2hf8s_512:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vcvtbiasps2hf8s %zmm1, %zmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf5,0x7c,0xc9,0x3a,0xc1]
+; X64-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_maskz_vcvtbiasps2hf8s_512:
+; X86: # %bb.0:
+; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf8,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vcvtbiasps2hf8s %zmm1, %zmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf5,0x7c,0xc9,0x3a,0xc1]
+; X86-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2hf8s.512(<64 x i8> %A, <16 x float> %B, <16 x i8> zeroinitializer, i16 %C)
+ ret <16 x i8> %ret
+}
+
+declare <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2hf8s.128(<16 x i8>, <4 x float>, <16 x i8>, i8)
+declare <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2hf8s.256(<32 x i8>, <8 x float>, <16 x i8>, i8)
+declare <16 x i8> @llvm.x86.avx10.mask.vcvtbiasps2hf8s.512(<64 x i8>, <16 x float>, <16 x i8>, i16)
+
+; ===== Group C: 8bit->PS expanding conversions =====
+
+; --- vcvtbf82ps ---
+
+define <4 x float> @test_int_x86_avx10_vcvtbf82ps_128(<16 x i8> %A) {
+; CHECK-LABEL: test_int_x86_avx10_vcvtbf82ps_128:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vcvtbf82ps %xmm0, %xmm0 # encoding: [0x62,0xf5,0xfc,0x08,0x36,0xc0]
+; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
+ %ret = call <4 x float> @llvm.x86.avx10.mask.vcvtbf82ps.128(<16 x i8> %A, <4 x float> zeroinitializer, i8 -1)
+ ret <4 x float> %ret
+}
+
+define <8 x float> @test_int_x86_avx10_vcvtbf82ps_256(<16 x i8> %A) {
+; CHECK-LABEL: test_int_x86_avx10_vcvtbf82ps_256:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vcvtbf82ps %xmm0, %ymm0 # encoding: [0x62,0xf5,0xfc,0x28,0x36,0xc0]
+; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
+ %ret = call <8 x float> @llvm.x86.avx10.mask.vcvtbf82ps.256(<16 x i8> %A, <8 x float> zeroinitializer, i8 -1)
+ ret <8 x float> %ret
+}
+
+define <16 x float> @test_int_x86_avx10_vcvtbf82ps_512(<16 x i8> %A) {
+; CHECK-LABEL: test_int_x86_avx10_vcvtbf82ps_512:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vcvtbf82ps %xmm0, %zmm0 # encoding: [0x62,0xf5,0xfc,0x48,0x36,0xc0]
+; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
+ %ret = call <16 x float> @llvm.x86.avx10.mask.vcvtbf82ps.512(<16 x i8> %A, <16 x float> zeroinitializer, i16 -1)
+ ret <16 x float> %ret
+}
+
+define <4 x float> @test_int_x86_avx10_mask_vcvtbf82ps_128(<16 x i8> %A, <4 x float> %B, i8 %C) {
+; X64-LABEL: test_int_x86_avx10_mask_vcvtbf82ps_128:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vcvtbf82ps %xmm0, %xmm1 {%k1} # encoding: [0x62,0xf5,0xfc,0x09,0x36,0xc8]
+; X64-NEXT: vmovaps %xmm1, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc1]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_mask_vcvtbf82ps_128:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vcvtbf82ps %xmm0, %xmm1 {%k1} # encoding: [0x62,0xf5,0xfc,0x09,0x36,0xc8]
+; X86-NEXT: vmovaps %xmm1, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc1]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <4 x float> @llvm.x86.avx10.mask.vcvtbf82ps.128(<16 x i8> %A, <4 x float> %B, i8 %C)
+ ret <4 x float> %ret
+}
+
+define <8 x float> @test_int_x86_avx10_mask_vcvtbf82ps_256(<16 x i8> %A, <8 x float> %B, i8 %C) {
+; X64-LABEL: test_int_x86_avx10_mask_vcvtbf82ps_256:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vcvtbf82ps %xmm0, %ymm1 {%k1} # encoding: [0x62,0xf5,0xfc,0x29,0x36,0xc8]
+; X64-NEXT: vmovaps %ymm1, %ymm0 # EVEX TO VEX Compression encoding: [0xc5,0xfc,0x28,0xc1]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_mask_vcvtbf82ps_256:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vcvtbf82ps %xmm0, %ymm1 {%k1} # encoding: [0x62,0xf5,0xfc,0x29,0x36,0xc8]
+; X86-NEXT: vmovaps %ymm1, %ymm0 # EVEX TO VEX Compression encoding: [0xc5,0xfc,0x28,0xc1]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <8 x float> @llvm.x86.avx10.mask.vcvtbf82ps.256(<16 x i8> %A, <8 x float> %B, i8 %C)
+ ret <8 x float> %ret
+}
+
+define <16 x float> @test_int_x86_avx10_mask_vcvtbf82ps_512(<16 x i8> %A, <16 x float> %B, i16 %C) {
+; X64-LABEL: test_int_x86_avx10_mask_vcvtbf82ps_512:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vcvtbf82ps %xmm0, %zmm1 {%k1} # encoding: [0x62,0xf5,0xfc,0x49,0x36,0xc8]
+; X64-NEXT: vmovaps %zmm1, %zmm0 # encoding: [0x62,0xf1,0x7c,0x48,0x28,0xc1]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_mask_vcvtbf82ps_512:
+; X86: # %bb.0:
+; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf8,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vcvtbf82ps %xmm0, %zmm1 {%k1} # encoding: [0x62,0xf5,0xfc,0x49,0x36,0xc8]
+; X86-NEXT: vmovaps %zmm1, %zmm0 # encoding: [0x62,0xf1,0x7c,0x48,0x28,0xc1]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <16 x float> @llvm.x86.avx10.mask.vcvtbf82ps.512(<16 x i8> %A, <16 x float> %B, i16 %C)
+ ret <16 x float> %ret
+}
+
+define <4 x float> @test_int_x86_avx10_maskz_vcvtbf82ps_128(<16 x i8> %A, i8 %B) {
+; X64-LABEL: test_int_x86_avx10_maskz_vcvtbf82ps_128:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vcvtbf82ps %xmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf5,0xfc,0x89,0x36,0xc0]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_maskz_vcvtbf82ps_128:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vcvtbf82ps %xmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf5,0xfc,0x89,0x36,0xc0]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <4 x float> @llvm.x86.avx10.mask.vcvtbf82ps.128(<16 x i8> %A, <4 x float> zeroinitializer, i8 %B)
+ ret <4 x float> %ret
+}
+
+define <8 x float> @test_int_x86_avx10_maskz_vcvtbf82ps_256(<16 x i8> %A, i8 %B) {
+; X64-LABEL: test_int_x86_avx10_maskz_vcvtbf82ps_256:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vcvtbf82ps %xmm0, %ymm0 {%k1} {z} # encoding: [0x62,0xf5,0xfc,0xa9,0x36,0xc0]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_maskz_vcvtbf82ps_256:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vcvtbf82ps %xmm0, %ymm0 {%k1} {z} # encoding: [0x62,0xf5,0xfc,0xa9,0x36,0xc0]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <8 x float> @llvm.x86.avx10.mask.vcvtbf82ps.256(<16 x i8> %A, <8 x float> zeroinitializer, i8 %B)
+ ret <8 x float> %ret
+}
+
+define <16 x float> @test_int_x86_avx10_maskz_vcvtbf82ps_512(<16 x i8> %A, i16 %B) {
+; X64-LABEL: test_int_x86_avx10_maskz_vcvtbf82ps_512:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vcvtbf82ps %xmm0, %zmm0 {%k1} {z} # encoding: [0x62,0xf5,0xfc,0xc9,0x36,0xc0]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_maskz_vcvtbf82ps_512:
+; X86: # %bb.0:
+; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf8,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vcvtbf82ps %xmm0, %zmm0 {%k1} {z} # encoding: [0x62,0xf5,0xfc,0xc9,0x36,0xc0]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <16 x float> @llvm.x86.avx10.mask.vcvtbf82ps.512(<16 x i8> %A, <16 x float> zeroinitializer, i16 %B)
+ ret <16 x float> %ret
+}
+
+declare <4 x float> @llvm.x86.avx10.mask.vcvtbf82ps.128(<16 x i8>, <4 x float>, i8)
+declare <8 x float> @llvm.x86.avx10.mask.vcvtbf82ps.256(<16 x i8>, <8 x float>, i8)
+declare <16 x float> @llvm.x86.avx10.mask.vcvtbf82ps.512(<16 x i8>, <16 x float>, i16)
+
+; --- vcvthf82ps ---
+
+define <4 x float> @test_int_x86_avx10_vcvthf82ps_128(<16 x i8> %A) {
+; CHECK-LABEL: test_int_x86_avx10_vcvthf82ps_128:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vcvthf82ps %xmm0, %xmm0 # encoding: [0x62,0xf5,0x7c,0x08,0x36,0xc0]
+; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
+ %ret = call <4 x float> @llvm.x86.avx10.mask.vcvthf82ps.128(<16 x i8> %A, <4 x float> zeroinitializer, i8 -1)
+ ret <4 x float> %ret
+}
+
+define <8 x float> @test_int_x86_avx10_vcvthf82ps_256(<16 x i8> %A) {
+; CHECK-LABEL: test_int_x86_avx10_vcvthf82ps_256:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vcvthf82ps %xmm0, %ymm0 # encoding: [0x62,0xf5,0x7c,0x28,0x36,0xc0]
+; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
+ %ret = call <8 x float> @llvm.x86.avx10.mask.vcvthf82ps.256(<16 x i8> %A, <8 x float> zeroinitializer, i8 -1)
+ ret <8 x float> %ret
+}
+
+define <16 x float> @test_int_x86_avx10_vcvthf82ps_512(<16 x i8> %A) {
+; CHECK-LABEL: test_int_x86_avx10_vcvthf82ps_512:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vcvthf82ps %xmm0, %zmm0 # encoding: [0x62,0xf5,0x7c,0x48,0x36,0xc0]
+; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
+ %ret = call <16 x float> @llvm.x86.avx10.mask.vcvthf82ps.512(<16 x i8> %A, <16 x float> zeroinitializer, i16 -1)
+ ret <16 x float> %ret
+}
+
+define <4 x float> @test_int_x86_avx10_mask_vcvthf82ps_128(<16 x i8> %A, <4 x float> %B, i8 %C) {
+; X64-LABEL: test_int_x86_avx10_mask_vcvthf82ps_128:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vcvthf82ps %xmm0, %xmm1 {%k1} # encoding: [0x62,0xf5,0x7c,0x09,0x36,0xc8]
+; X64-NEXT: vmovaps %xmm1, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc1]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_mask_vcvthf82ps_128:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vcvthf82ps %xmm0, %xmm1 {%k1} # encoding: [0x62,0xf5,0x7c,0x09,0x36,0xc8]
+; X86-NEXT: vmovaps %xmm1, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc1]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <4 x float> @llvm.x86.avx10.mask.vcvthf82ps.128(<16 x i8> %A, <4 x float> %B, i8 %C)
+ ret <4 x float> %ret
+}
+
+define <8 x float> @test_int_x86_avx10_mask_vcvthf82ps_256(<16 x i8> %A, <8 x float> %B, i8 %C) {
+; X64-LABEL: test_int_x86_avx10_mask_vcvthf82ps_256:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vcvthf82ps %xmm0, %ymm1 {%k1} # encoding: [0x62,0xf5,0x7c,0x29,0x36,0xc8]
+; X64-NEXT: vmovaps %ymm1, %ymm0 # EVEX TO VEX Compression encoding: [0xc5,0xfc,0x28,0xc1]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_mask_vcvthf82ps_256:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vcvthf82ps %xmm0, %ymm1 {%k1} # encoding: [0x62,0xf5,0x7c,0x29,0x36,0xc8]
+; X86-NEXT: vmovaps %ymm1, %ymm0 # EVEX TO VEX Compression encoding: [0xc5,0xfc,0x28,0xc1]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <8 x float> @llvm.x86.avx10.mask.vcvthf82ps.256(<16 x i8> %A, <8 x float> %B, i8 %C)
+ ret <8 x float> %ret
+}
+
+define <16 x float> @test_int_x86_avx10_mask_vcvthf82ps_512(<16 x i8> %A, <16 x float> %B, i16 %C) {
+; X64-LABEL: test_int_x86_avx10_mask_vcvthf82ps_512:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vcvthf82ps %xmm0, %zmm1 {%k1} # encoding: [0x62,0xf5,0x7c,0x49,0x36,0xc8]
+; X64-NEXT: vmovaps %zmm1, %zmm0 # encoding: [0x62,0xf1,0x7c,0x48,0x28,0xc1]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_mask_vcvthf82ps_512:
+; X86: # %bb.0:
+; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf8,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vcvthf82ps %xmm0, %zmm1 {%k1} # encoding: [0x62,0xf5,0x7c,0x49,0x36,0xc8]
+; X86-NEXT: vmovaps %zmm1, %zmm0 # encoding: [0x62,0xf1,0x7c,0x48,0x28,0xc1]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <16 x float> @llvm.x86.avx10.mask.vcvthf82ps.512(<16 x i8> %A, <16 x float> %B, i16 %C)
+ ret <16 x float> %ret
+}
+
+define <4 x float> @test_int_x86_avx10_maskz_vcvthf82ps_128(<16 x i8> %A, i8 %B) {
+; X64-LABEL: test_int_x86_avx10_maskz_vcvthf82ps_128:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vcvthf82ps %xmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf5,0x7c,0x89,0x36,0xc0]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_maskz_vcvthf82ps_128:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vcvthf82ps %xmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf5,0x7c,0x89,0x36,0xc0]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <4 x float> @llvm.x86.avx10.mask.vcvthf82ps.128(<16 x i8> %A, <4 x float> zeroinitializer, i8 %B)
+ ret <4 x float> %ret
+}
+
+define <8 x float> @test_int_x86_avx10_maskz_vcvthf82ps_256(<16 x i8> %A, i8 %B) {
+; X64-LABEL: test_int_x86_avx10_maskz_vcvthf82ps_256:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vcvthf82ps %xmm0, %ymm0 {%k1} {z} # encoding: [0x62,0xf5,0x7c,0xa9,0x36,0xc0]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_maskz_vcvthf82ps_256:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vcvthf82ps %xmm0, %ymm0 {%k1} {z} # encoding: [0x62,0xf5,0x7c,0xa9,0x36,0xc0]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <8 x float> @llvm.x86.avx10.mask.vcvthf82ps.256(<16 x i8> %A, <8 x float> zeroinitializer, i8 %B)
+ ret <8 x float> %ret
+}
+
+define <16 x float> @test_int_x86_avx10_maskz_vcvthf82ps_512(<16 x i8> %A, i16 %B) {
+; X64-LABEL: test_int_x86_avx10_maskz_vcvthf82ps_512:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vcvthf82ps %xmm0, %zmm0 {%k1} {z} # encoding: [0x62,0xf5,0x7c,0xc9,0x36,0xc0]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_maskz_vcvthf82ps_512:
+; X86: # %bb.0:
+; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf8,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vcvthf82ps %xmm0, %zmm0 {%k1} {z} # encoding: [0x62,0xf5,0x7c,0xc9,0x36,0xc0]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <16 x float> @llvm.x86.avx10.mask.vcvthf82ps.512(<16 x i8> %A, <16 x float> zeroinitializer, i16 %B)
+ ret <16 x float> %ret
+}
+
+declare <4 x float> @llvm.x86.avx10.mask.vcvthf82ps.128(<16 x i8>, <4 x float>, i8)
+declare <8 x float> @llvm.x86.avx10.mask.vcvthf82ps.256(<16 x i8>, <8 x float>, i8)
+declare <16 x float> @llvm.x86.avx10.mask.vcvthf82ps.512(<16 x i8>, <16 x float>, i16)
+
+; ===== Group E: Same-size reg-only conversions =====
+
+; --- vcvtbf82bf6s ---
+
+define <16 x i8> @test_int_x86_avx10_vcvtbf82bf6s_128(<16 x i8> %A) {
+; CHECK-LABEL: test_int_x86_avx10_vcvtbf82bf6s_128:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vcvtbf82bf6s %xmm0, %xmm0 # encoding: [0x62,0xf5,0xfe,0x08,0x3e,0xc0]
+; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.vcvtbf82bf6s.128(<16 x i8> %A)
+ ret <16 x i8> %ret
+}
+
+define <32 x i8> @test_int_x86_avx10_vcvtbf82bf6s_256(<32 x i8> %A) {
+; CHECK-LABEL: test_int_x86_avx10_vcvtbf82bf6s_256:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vcvtbf82bf6s %ymm0, %ymm0 # encoding: [0x62,0xf5,0xfe,0x28,0x3e,0xc0]
+; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
+ %ret = call <32 x i8> @llvm.x86.avx10.vcvtbf82bf6s.256(<32 x i8> %A)
+ ret <32 x i8> %ret
+}
+
+define <64 x i8> @test_int_x86_avx10_vcvtbf82bf6s_512(<64 x i8> %A) {
+; CHECK-LABEL: test_int_x86_avx10_vcvtbf82bf6s_512:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vcvtbf82bf6s %zmm0, %zmm0 # encoding: [0x62,0xf5,0xfe,0x48,0x3e,0xc0]
+; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
+ %ret = call <64 x i8> @llvm.x86.avx10.vcvtbf82bf6s.512(<64 x i8> %A)
+ ret <64 x i8> %ret
+}
+
+declare <16 x i8> @llvm.x86.avx10.vcvtbf82bf6s.128(<16 x i8>)
+declare <32 x i8> @llvm.x86.avx10.vcvtbf82bf6s.256(<32 x i8>)
+declare <64 x i8> @llvm.x86.avx10.vcvtbf82bf6s.512(<64 x i8>)
+
+; --- vcvthf82hf6s ---
+
+define <16 x i8> @test_int_x86_avx10_vcvthf82hf6s_128(<16 x i8> %A) {
+; CHECK-LABEL: test_int_x86_avx10_vcvthf82hf6s_128:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vcvthf82hf6s %xmm0, %xmm0 # encoding: [0x62,0xf5,0x7e,0x08,0x3c,0xc0]
+; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.vcvthf82hf6s.128(<16 x i8> %A)
+ ret <16 x i8> %ret
+}
+
+define <32 x i8> @test_int_x86_avx10_vcvthf82hf6s_256(<32 x i8> %A) {
+; CHECK-LABEL: test_int_x86_avx10_vcvthf82hf6s_256:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vcvthf82hf6s %ymm0, %ymm0 # encoding: [0x62,0xf5,0x7e,0x28,0x3c,0xc0]
+; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
+ %ret = call <32 x i8> @llvm.x86.avx10.vcvthf82hf6s.256(<32 x i8> %A)
+ ret <32 x i8> %ret
+}
+
+define <64 x i8> @test_int_x86_avx10_vcvthf82hf6s_512(<64 x i8> %A) {
+; CHECK-LABEL: test_int_x86_avx10_vcvthf82hf6s_512:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vcvthf82hf6s %zmm0, %zmm0 # encoding: [0x62,0xf5,0x7e,0x48,0x3c,0xc0]
+; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
+ %ret = call <64 x i8> @llvm.x86.avx10.vcvthf82hf6s.512(<64 x i8> %A)
+ ret <64 x i8> %ret
+}
+
+declare <16 x i8> @llvm.x86.avx10.vcvthf82hf6s.128(<16 x i8>)
+declare <32 x i8> @llvm.x86.avx10.vcvthf82hf6s.256(<32 x i8>)
+declare <64 x i8> @llvm.x86.avx10.vcvthf82hf6s.512(<64 x i8>)
+
+; ===== Group F: Expanding/same-size conversions =====
+
+; --- vcvtbf42hf8 ---
+
+define <16 x i8> @test_int_x86_avx10_vcvtbf42hf8_128(<16 x i8> %A) {
+; CHECK-LABEL: test_int_x86_avx10_vcvtbf42hf8_128:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vcvtbf42hf8 %xmm0, %xmm0 # encoding: [0x62,0xf5,0x7c,0x08,0x37,0xc0]
+; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.vcvtbf42hf8.128(<16 x i8> %A)
+ ret <16 x i8> %ret
+}
+
+define <32 x i8> @test_int_x86_avx10_vcvtbf42hf8_256(<16 x i8> %A) {
+; CHECK-LABEL: test_int_x86_avx10_vcvtbf42hf8_256:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vcvtbf42hf8 %xmm0, %ymm0 # encoding: [0x62,0xf5,0x7c,0x28,0x37,0xc0]
+; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
+ %ret = call <32 x i8> @llvm.x86.avx10.vcvtbf42hf8.256(<16 x i8> %A)
+ ret <32 x i8> %ret
+}
+
+define <64 x i8> @test_int_x86_avx10_vcvtbf42hf8_512(<32 x i8> %A) {
+; CHECK-LABEL: test_int_x86_avx10_vcvtbf42hf8_512:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vcvtbf42hf8 %ymm0, %zmm0 # encoding: [0x62,0xf5,0x7c,0x48,0x37,0xc0]
+; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
+ %ret = call <64 x i8> @llvm.x86.avx10.vcvtbf42hf8.512(<32 x i8> %A)
+ ret <64 x i8> %ret
+}
+
+declare <16 x i8> @llvm.x86.avx10.vcvtbf42hf8.128(<16 x i8>)
+declare <32 x i8> @llvm.x86.avx10.vcvtbf42hf8.256(<16 x i8>)
+declare <64 x i8> @llvm.x86.avx10.vcvtbf42hf8.512(<32 x i8>)
+
+; --- vcvtbf62hf8 ---
+
+define <16 x i8> @test_int_x86_avx10_vcvtbf62hf8_128(<16 x i8> %A) {
+; CHECK-LABEL: test_int_x86_avx10_vcvtbf62hf8_128:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vcvtbf62hf8 %xmm0, %xmm0 # encoding: [0x62,0xf5,0xfd,0x08,0x37,0xc0]
+; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.vcvtbf62hf8.128(<16 x i8> %A)
+ ret <16 x i8> %ret
+}
+
+define <32 x i8> @test_int_x86_avx10_vcvtbf62hf8_256(<32 x i8> %A) {
+; CHECK-LABEL: test_int_x86_avx10_vcvtbf62hf8_256:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vcvtbf62hf8 %ymm0, %ymm0 # encoding: [0x62,0xf5,0xfd,0x28,0x37,0xc0]
+; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
+ %ret = call <32 x i8> @llvm.x86.avx10.vcvtbf62hf8.256(<32 x i8> %A)
+ ret <32 x i8> %ret
+}
+
+define <64 x i8> @test_int_x86_avx10_vcvtbf62hf8_512(<64 x i8> %A) {
+; CHECK-LABEL: test_int_x86_avx10_vcvtbf62hf8_512:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vcvtbf62hf8 %zmm0, %zmm0 # encoding: [0x62,0xf5,0xfd,0x48,0x37,0xc0]
+; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
+ %ret = call <64 x i8> @llvm.x86.avx10.vcvtbf62hf8.512(<64 x i8> %A)
+ ret <64 x i8> %ret
+}
+
+declare <16 x i8> @llvm.x86.avx10.vcvtbf62hf8.128(<16 x i8>)
+declare <32 x i8> @llvm.x86.avx10.vcvtbf62hf8.256(<32 x i8>)
+declare <64 x i8> @llvm.x86.avx10.vcvtbf62hf8.512(<64 x i8>)
+
+; --- vcvthf62hf8 ---
+
+define <16 x i8> @test_int_x86_avx10_vcvthf62hf8_128(<16 x i8> %A) {
+; CHECK-LABEL: test_int_x86_avx10_vcvthf62hf8_128:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vcvthf62hf8 %xmm0, %xmm0 # encoding: [0x62,0xf5,0x7d,0x08,0x37,0xc0]
+; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.vcvthf62hf8.128(<16 x i8> %A)
+ ret <16 x i8> %ret
+}
+
+define <32 x i8> @test_int_x86_avx10_vcvthf62hf8_256(<32 x i8> %A) {
+; CHECK-LABEL: test_int_x86_avx10_vcvthf62hf8_256:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vcvthf62hf8 %ymm0, %ymm0 # encoding: [0x62,0xf5,0x7d,0x28,0x37,0xc0]
+; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
+ %ret = call <32 x i8> @llvm.x86.avx10.vcvthf62hf8.256(<32 x i8> %A)
+ ret <32 x i8> %ret
+}
+
+define <64 x i8> @test_int_x86_avx10_vcvthf62hf8_512(<64 x i8> %A) {
+; CHECK-LABEL: test_int_x86_avx10_vcvthf62hf8_512:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vcvthf62hf8 %zmm0, %zmm0 # encoding: [0x62,0xf5,0x7d,0x48,0x37,0xc0]
+; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
+ %ret = call <64 x i8> @llvm.x86.avx10.vcvthf62hf8.512(<64 x i8> %A)
+ ret <64 x i8> %ret
+}
+
+declare <16 x i8> @llvm.x86.avx10.vcvthf62hf8.128(<16 x i8>)
+declare <32 x i8> @llvm.x86.avx10.vcvthf62hf8.256(<32 x i8>)
+declare <64 x i8> @llvm.x86.avx10.vcvthf62hf8.512(<64 x i8>)
+
+; ===== Group H: VUNPACKB =====
+
+define <16 x i8> @test_int_x86_avx10_vunpackb_128(<16 x i8> %A) {
+; CHECK-LABEL: test_int_x86_avx10_vunpackb_128:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vunpackb $1, %xmm0, %xmm0 # encoding: [0x62,0xf3,0x7c,0x08,0x3d,0xc0,0x01]
+; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
+ %ret = call <16 x i8> @llvm.x86.avx10.vunpackb.128(<16 x i8> %A, i8 1)
+ ret <16 x i8> %ret
+}
+
+define <32 x i8> @test_int_x86_avx10_vunpackb_256(<32 x i8> %A) {
+; CHECK-LABEL: test_int_x86_avx10_vunpackb_256:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vunpackb $2, %ymm0, %ymm0 # encoding: [0x62,0xf3,0x7c,0x28,0x3d,0xc0,0x02]
+; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
+ %ret = call <32 x i8> @llvm.x86.avx10.vunpackb.256(<32 x i8> %A, i8 2)
+ ret <32 x i8> %ret
+}
+
+define <64 x i8> @test_int_x86_avx10_vunpackb_512(<64 x i8> %A) {
+; CHECK-LABEL: test_int_x86_avx10_vunpackb_512:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vunpackb $3, %zmm0, %zmm0 # encoding: [0x62,0xf3,0x7c,0x48,0x3d,0xc0,0x03]
+; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
+ %ret = call <64 x i8> @llvm.x86.avx10.vunpackb.512(<64 x i8> %A, i8 3)
+ ret <64 x i8> %ret
+}
+
+declare <16 x i8> @llvm.x86.avx10.vunpackb.128(<16 x i8>, i8)
+declare <32 x i8> @llvm.x86.avx10.vunpackb.256(<32 x i8>, i8)
+declare <64 x i8> @llvm.x86.avx10.vunpackb.512(<64 x i8>, i8)
diff --git a/llvm/test/MC/Disassembler/X86/avx10_v2_aux-32.txt b/llvm/test/MC/Disassembler/X86/avx10_v2_aux-32.txt
new file mode 100644
index 0000000000000..2f301e02e1d4f
--- /dev/null
+++ b/llvm/test/MC/Disassembler/X86/avx10_v2_aux-32.txt
@@ -0,0 +1,460 @@
+# RUN: llvm-mc --disassemble %s -triple=i386 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=i386 --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+#
+# Group A: PS->8bit truncating conversions
+#
+
+# vcvtps2bf8
+
+# ATT: vcvtps2bf8 %zmm1, %xmm0
+# INTEL: vcvtps2bf8 xmm0, zmm1
+0x62,0xf5,0x7e,0x48,0x39,0xc1
+
+# ATT: vcvtps2bf8 %ymm1, %xmm0
+# INTEL: vcvtps2bf8 xmm0, ymm1
+0x62,0xf5,0x7e,0x28,0x39,0xc1
+
+# ATT: vcvtps2bf8 %xmm1, %xmm0
+# INTEL: vcvtps2bf8 xmm0, xmm1
+0x62,0xf5,0x7e,0x08,0x39,0xc1
+
+# ATT: vcvtps2bf8 %zmm1, %xmm0 {%k1}
+# INTEL: vcvtps2bf8 xmm0 {k1}, zmm1
+0x62,0xf5,0x7e,0x49,0x39,0xc1
+
+# ATT: vcvtps2bf8 %zmm1, %xmm0 {%k1} {z}
+# INTEL: vcvtps2bf8 xmm0 {k1} {z}, zmm1
+0x62,0xf5,0x7e,0xc9,0x39,0xc1
+
+# vcvtps2bf8s
+
+# ATT: vcvtps2bf8s %zmm1, %xmm0
+# INTEL: vcvtps2bf8s xmm0, zmm1
+0x62,0xf5,0x7e,0x48,0x3b,0xc1
+
+# ATT: vcvtps2bf8s %ymm1, %xmm0
+# INTEL: vcvtps2bf8s xmm0, ymm1
+0x62,0xf5,0x7e,0x28,0x3b,0xc1
+
+# ATT: vcvtps2bf8s %xmm1, %xmm0
+# INTEL: vcvtps2bf8s xmm0, xmm1
+0x62,0xf5,0x7e,0x08,0x3b,0xc1
+
+# ATT: vcvtps2bf8s %zmm1, %xmm0 {%k1}
+# INTEL: vcvtps2bf8s xmm0 {k1}, zmm1
+0x62,0xf5,0x7e,0x49,0x3b,0xc1
+
+# ATT: vcvtps2bf8s %zmm1, %xmm0 {%k1} {z}
+# INTEL: vcvtps2bf8s xmm0 {k1} {z}, zmm1
+0x62,0xf5,0x7e,0xc9,0x3b,0xc1
+
+# vcvtps2hf8
+
+# ATT: vcvtps2hf8 %zmm1, %xmm0
+# INTEL: vcvtps2hf8 xmm0, zmm1
+0x62,0xf5,0x7e,0x48,0x38,0xc1
+
+# ATT: vcvtps2hf8 %ymm1, %xmm0
+# INTEL: vcvtps2hf8 xmm0, ymm1
+0x62,0xf5,0x7e,0x28,0x38,0xc1
+
+# ATT: vcvtps2hf8 %xmm1, %xmm0
+# INTEL: vcvtps2hf8 xmm0, xmm1
+0x62,0xf5,0x7e,0x08,0x38,0xc1
+
+# ATT: vcvtps2hf8 %zmm1, %xmm0 {%k1}
+# INTEL: vcvtps2hf8 xmm0 {k1}, zmm1
+0x62,0xf5,0x7e,0x49,0x38,0xc1
+
+# ATT: vcvtps2hf8 %zmm1, %xmm0 {%k1} {z}
+# INTEL: vcvtps2hf8 xmm0 {k1} {z}, zmm1
+0x62,0xf5,0x7e,0xc9,0x38,0xc1
+
+# vcvtps2hf8s
+
+# ATT: vcvtps2hf8s %zmm1, %xmm0
+# INTEL: vcvtps2hf8s xmm0, zmm1
+0x62,0xf5,0x7e,0x48,0x3a,0xc1
+
+# ATT: vcvtps2hf8s %ymm1, %xmm0
+# INTEL: vcvtps2hf8s xmm0, ymm1
+0x62,0xf5,0x7e,0x28,0x3a,0xc1
+
+# ATT: vcvtps2hf8s %xmm1, %xmm0
+# INTEL: vcvtps2hf8s xmm0, xmm1
+0x62,0xf5,0x7e,0x08,0x3a,0xc1
+
+# ATT: vcvtps2hf8s %zmm1, %xmm0 {%k1}
+# INTEL: vcvtps2hf8s xmm0 {k1}, zmm1
+0x62,0xf5,0x7e,0x49,0x3a,0xc1
+
+# ATT: vcvtps2hf8s %zmm1, %xmm0 {%k1} {z}
+# INTEL: vcvtps2hf8s xmm0 {k1} {z}, zmm1
+0x62,0xf5,0x7e,0xc9,0x3a,0xc1
+
+# vcvtrops2hf8
+
+# ATT: vcvtrops2hf8 %zmm1, %xmm0
+# INTEL: vcvtrops2hf8 xmm0, zmm1
+0x62,0xf5,0x7d,0x48,0x38,0xc1
+
+# ATT: vcvtrops2hf8 %ymm1, %xmm0
+# INTEL: vcvtrops2hf8 xmm0, ymm1
+0x62,0xf5,0x7d,0x28,0x38,0xc1
+
+# ATT: vcvtrops2hf8 %xmm1, %xmm0
+# INTEL: vcvtrops2hf8 xmm0, xmm1
+0x62,0xf5,0x7d,0x08,0x38,0xc1
+
+# ATT: vcvtrops2hf8 %zmm1, %xmm0 {%k1}
+# INTEL: vcvtrops2hf8 xmm0 {k1}, zmm1
+0x62,0xf5,0x7d,0x49,0x38,0xc1
+
+# ATT: vcvtrops2hf8 %zmm1, %xmm0 {%k1} {z}
+# INTEL: vcvtrops2hf8 xmm0 {k1} {z}, zmm1
+0x62,0xf5,0x7d,0xc9,0x38,0xc1
+
+# vcvtrops2hf8s
+
+# ATT: vcvtrops2hf8s %zmm1, %xmm0
+# INTEL: vcvtrops2hf8s xmm0, zmm1
+0x62,0xf5,0x7d,0x48,0x3a,0xc1
+
+# ATT: vcvtrops2hf8s %ymm1, %xmm0
+# INTEL: vcvtrops2hf8s xmm0, ymm1
+0x62,0xf5,0x7d,0x28,0x3a,0xc1
+
+# ATT: vcvtrops2hf8s %xmm1, %xmm0
+# INTEL: vcvtrops2hf8s xmm0, xmm1
+0x62,0xf5,0x7d,0x08,0x3a,0xc1
+
+# ATT: vcvtrops2hf8s %zmm1, %xmm0 {%k1}
+# INTEL: vcvtrops2hf8s xmm0 {k1}, zmm1
+0x62,0xf5,0x7d,0x49,0x3a,0xc1
+
+# ATT: vcvtrops2hf8s %zmm1, %xmm0 {%k1} {z}
+# INTEL: vcvtrops2hf8s xmm0 {k1} {z}, zmm1
+0x62,0xf5,0x7d,0xc9,0x3a,0xc1
+
+#
+# Group B: Bias PS->8bit conversions (3-operand)
+#
+
+# vcvtbiasps2bf8
+
+# ATT: vcvtbiasps2bf8 %zmm2, %zmm1, %xmm0
+# INTEL: vcvtbiasps2bf8 xmm0, zmm1, zmm2
+0x62,0xf5,0x74,0x48,0x39,0xc2
+
+# ATT: vcvtbiasps2bf8 %ymm2, %ymm1, %xmm0
+# INTEL: vcvtbiasps2bf8 xmm0, ymm1, ymm2
+0x62,0xf5,0x74,0x28,0x39,0xc2
+
+# ATT: vcvtbiasps2bf8 %xmm2, %xmm1, %xmm0
+# INTEL: vcvtbiasps2bf8 xmm0, xmm1, xmm2
+0x62,0xf5,0x74,0x08,0x39,0xc2
+
+# ATT: vcvtbiasps2bf8 %zmm2, %zmm1, %xmm0 {%k1}
+# INTEL: vcvtbiasps2bf8 xmm0 {k1}, zmm1, zmm2
+0x62,0xf5,0x74,0x49,0x39,0xc2
+
+# ATT: vcvtbiasps2bf8 %zmm2, %zmm1, %xmm0 {%k1} {z}
+# INTEL: vcvtbiasps2bf8 xmm0 {k1} {z}, zmm1, zmm2
+0x62,0xf5,0x74,0xc9,0x39,0xc2
+
+# vcvtbiasps2bf8s
+
+# ATT: vcvtbiasps2bf8s %zmm2, %zmm1, %xmm0
+# INTEL: vcvtbiasps2bf8s xmm0, zmm1, zmm2
+0x62,0xf5,0x74,0x48,0x3b,0xc2
+
+# ATT: vcvtbiasps2bf8s %ymm2, %ymm1, %xmm0
+# INTEL: vcvtbiasps2bf8s xmm0, ymm1, ymm2
+0x62,0xf5,0x74,0x28,0x3b,0xc2
+
+# ATT: vcvtbiasps2bf8s %xmm2, %xmm1, %xmm0
+# INTEL: vcvtbiasps2bf8s xmm0, xmm1, xmm2
+0x62,0xf5,0x74,0x08,0x3b,0xc2
+
+# ATT: vcvtbiasps2bf8s %zmm2, %zmm1, %xmm0 {%k1}
+# INTEL: vcvtbiasps2bf8s xmm0 {k1}, zmm1, zmm2
+0x62,0xf5,0x74,0x49,0x3b,0xc2
+
+# ATT: vcvtbiasps2bf8s %zmm2, %zmm1, %xmm0 {%k1} {z}
+# INTEL: vcvtbiasps2bf8s xmm0 {k1} {z}, zmm1, zmm2
+0x62,0xf5,0x74,0xc9,0x3b,0xc2
+
+# vcvtbiasps2hf8
+
+# ATT: vcvtbiasps2hf8 %zmm2, %zmm1, %xmm0
+# INTEL: vcvtbiasps2hf8 xmm0, zmm1, zmm2
+0x62,0xf5,0x74,0x48,0x38,0xc2
+
+# ATT: vcvtbiasps2hf8 %ymm2, %ymm1, %xmm0
+# INTEL: vcvtbiasps2hf8 xmm0, ymm1, ymm2
+0x62,0xf5,0x74,0x28,0x38,0xc2
+
+# ATT: vcvtbiasps2hf8 %xmm2, %xmm1, %xmm0
+# INTEL: vcvtbiasps2hf8 xmm0, xmm1, xmm2
+0x62,0xf5,0x74,0x08,0x38,0xc2
+
+# ATT: vcvtbiasps2hf8 %zmm2, %zmm1, %xmm0 {%k1}
+# INTEL: vcvtbiasps2hf8 xmm0 {k1}, zmm1, zmm2
+0x62,0xf5,0x74,0x49,0x38,0xc2
+
+# ATT: vcvtbiasps2hf8 %zmm2, %zmm1, %xmm0 {%k1} {z}
+# INTEL: vcvtbiasps2hf8 xmm0 {k1} {z}, zmm1, zmm2
+0x62,0xf5,0x74,0xc9,0x38,0xc2
+
+# vcvtbiasps2hf8s
+
+# ATT: vcvtbiasps2hf8s %zmm2, %zmm1, %xmm0
+# INTEL: vcvtbiasps2hf8s xmm0, zmm1, zmm2
+0x62,0xf5,0x74,0x48,0x3a,0xc2
+
+# ATT: vcvtbiasps2hf8s %ymm2, %ymm1, %xmm0
+# INTEL: vcvtbiasps2hf8s xmm0, ymm1, ymm2
+0x62,0xf5,0x74,0x28,0x3a,0xc2
+
+# ATT: vcvtbiasps2hf8s %xmm2, %xmm1, %xmm0
+# INTEL: vcvtbiasps2hf8s xmm0, xmm1, xmm2
+0x62,0xf5,0x74,0x08,0x3a,0xc2
+
+# ATT: vcvtbiasps2hf8s %zmm2, %zmm1, %xmm0 {%k1}
+# INTEL: vcvtbiasps2hf8s xmm0 {k1}, zmm1, zmm2
+0x62,0xf5,0x74,0x49,0x3a,0xc2
+
+# ATT: vcvtbiasps2hf8s %zmm2, %zmm1, %xmm0 {%k1} {z}
+# INTEL: vcvtbiasps2hf8s xmm0 {k1} {z}, zmm1, zmm2
+0x62,0xf5,0x74,0xc9,0x3a,0xc2
+
+#
+# Group C: 8bit->PS expanding conversions
+#
+
+# vcvtbf82ps
+
+# ATT: vcvtbf82ps %xmm1, %zmm0
+# INTEL: vcvtbf82ps zmm0, xmm1
+0x62,0xf5,0xfc,0x48,0x36,0xc1
+
+# ATT: vcvtbf82ps %xmm1, %ymm0
+# INTEL: vcvtbf82ps ymm0, xmm1
+0x62,0xf5,0xfc,0x28,0x36,0xc1
+
+# ATT: vcvtbf82ps %xmm1, %xmm0
+# INTEL: vcvtbf82ps xmm0, xmm1
+0x62,0xf5,0xfc,0x08,0x36,0xc1
+
+# ATT: vcvtbf82ps %xmm1, %zmm0 {%k1}
+# INTEL: vcvtbf82ps zmm0 {k1}, xmm1
+0x62,0xf5,0xfc,0x49,0x36,0xc1
+
+# ATT: vcvtbf82ps %xmm1, %zmm0 {%k1} {z}
+# INTEL: vcvtbf82ps zmm0 {k1} {z}, xmm1
+0x62,0xf5,0xfc,0xc9,0x36,0xc1
+
+# vcvthf82ps
+
+# ATT: vcvthf82ps %xmm1, %zmm0
+# INTEL: vcvthf82ps zmm0, xmm1
+0x62,0xf5,0x7c,0x48,0x36,0xc1
+
+# ATT: vcvthf82ps %xmm1, %ymm0
+# INTEL: vcvthf82ps ymm0, xmm1
+0x62,0xf5,0x7c,0x28,0x36,0xc1
+
+# ATT: vcvthf82ps %xmm1, %xmm0
+# INTEL: vcvthf82ps xmm0, xmm1
+0x62,0xf5,0x7c,0x08,0x36,0xc1
+
+# ATT: vcvthf82ps %xmm1, %zmm0 {%k1}
+# INTEL: vcvthf82ps zmm0 {k1}, xmm1
+0x62,0xf5,0x7c,0x49,0x36,0xc1
+
+# ATT: vcvthf82ps %xmm1, %zmm0 {%k1} {z}
+# INTEL: vcvthf82ps zmm0 {k1} {z}, xmm1
+0x62,0xf5,0x7c,0xc9,0x36,0xc1
+
+#
+# Group D: BF8/HF8->BF4S truncations
+#
+
+# vcvtbf82bf4s
+
+# ATT: vcvtbf82bf4s %zmm1, %ymm0
+# INTEL: vcvtbf82bf4s ymm0, zmm1
+0x62,0xf5,0xfe,0x48,0x3d,0xc8
+
+# ATT: vcvtbf82bf4s %ymm1, %xmm0
+# INTEL: vcvtbf82bf4s xmm0, ymm1
+0x62,0xf5,0xfe,0x28,0x3d,0xc8
+
+# ATT: vcvtbf82bf4s %xmm1, %xmm0
+# INTEL: vcvtbf82bf4s xmm0, xmm1
+0x62,0xf5,0xfe,0x08,0x3d,0xc8
+
+# vcvthf82bf4s
+
+# ATT: vcvthf82bf4s %zmm1, %ymm0
+# INTEL: vcvthf82bf4s ymm0, zmm1
+0x62,0xf5,0x7e,0x48,0x3d,0xc8
+
+# ATT: vcvthf82bf4s %ymm1, %xmm0
+# INTEL: vcvthf82bf4s xmm0, ymm1
+0x62,0xf5,0x7e,0x28,0x3d,0xc8
+
+# ATT: vcvthf82bf4s %xmm1, %xmm0
+# INTEL: vcvthf82bf4s xmm0, xmm1
+0x62,0xf5,0x7e,0x08,0x3d,0xc8
+
+#
+# Group E: Same-size reg-only conversions (no masking)
+#
+
+# vcvtbf82bf6s
+
+# ATT: vcvtbf82bf6s %zmm1, %zmm0
+# INTEL: vcvtbf82bf6s zmm0, zmm1
+0x62,0xf5,0xfe,0x48,0x3e,0xc1
+
+# ATT: vcvtbf82bf6s %ymm1, %ymm0
+# INTEL: vcvtbf82bf6s ymm0, ymm1
+0x62,0xf5,0xfe,0x28,0x3e,0xc1
+
+# ATT: vcvtbf82bf6s %xmm1, %xmm0
+# INTEL: vcvtbf82bf6s xmm0, xmm1
+0x62,0xf5,0xfe,0x08,0x3e,0xc1
+
+# vcvthf82hf6s
+
+# ATT: vcvthf82hf6s %zmm1, %zmm0
+# INTEL: vcvthf82hf6s zmm0, zmm1
+0x62,0xf5,0x7e,0x48,0x3c,0xc1
+
+# ATT: vcvthf82hf6s %ymm1, %ymm0
+# INTEL: vcvthf82hf6s ymm0, ymm1
+0x62,0xf5,0x7e,0x28,0x3c,0xc1
+
+# ATT: vcvthf82hf6s %xmm1, %xmm0
+# INTEL: vcvthf82hf6s xmm0, xmm1
+0x62,0xf5,0x7e,0x08,0x3c,0xc1
+
+#
+# Group F: Expanding/same-size conversions with masking
+#
+
+# vcvtbf42hf8
+
+# ATT: vcvtbf42hf8 %ymm1, %zmm0
+# INTEL: vcvtbf42hf8 zmm0, ymm1
+0x62,0xf5,0x7c,0x48,0x37,0xc1
+
+# ATT: vcvtbf42hf8 %xmm1, %ymm0
+# INTEL: vcvtbf42hf8 ymm0, xmm1
+0x62,0xf5,0x7c,0x28,0x37,0xc1
+
+# ATT: vcvtbf42hf8 %xmm1, %xmm0
+# INTEL: vcvtbf42hf8 xmm0, xmm1
+0x62,0xf5,0x7c,0x08,0x37,0xc1
+
+# ATT: vcvtbf42hf8 %ymm1, %zmm0 {%k1}
+# INTEL: vcvtbf42hf8 zmm0 {k1}, ymm1
+0x62,0xf5,0x7c,0x49,0x37,0xc1
+
+# ATT: vcvtbf42hf8 %ymm1, %zmm0 {%k1} {z}
+# INTEL: vcvtbf42hf8 zmm0 {k1} {z}, ymm1
+0x62,0xf5,0x7c,0xc9,0x37,0xc1
+
+# vcvtbf62hf8
+
+# ATT: vcvtbf62hf8 %zmm1, %zmm0
+# INTEL: vcvtbf62hf8 zmm0, zmm1
+0x62,0xf5,0xfd,0x48,0x37,0xc1
+
+# ATT: vcvtbf62hf8 %ymm1, %ymm0
+# INTEL: vcvtbf62hf8 ymm0, ymm1
+0x62,0xf5,0xfd,0x28,0x37,0xc1
+
+# ATT: vcvtbf62hf8 %xmm1, %xmm0
+# INTEL: vcvtbf62hf8 xmm0, xmm1
+0x62,0xf5,0xfd,0x08,0x37,0xc1
+
+# ATT: vcvtbf62hf8 %zmm1, %zmm0 {%k1}
+# INTEL: vcvtbf62hf8 zmm0 {k1}, zmm1
+0x62,0xf5,0xfd,0x49,0x37,0xc1
+
+# ATT: vcvtbf62hf8 %zmm1, %zmm0 {%k1} {z}
+# INTEL: vcvtbf62hf8 zmm0 {k1} {z}, zmm1
+0x62,0xf5,0xfd,0xc9,0x37,0xc1
+
+# vcvthf62hf8
+
+# ATT: vcvthf62hf8 %zmm1, %zmm0
+# INTEL: vcvthf62hf8 zmm0, zmm1
+0x62,0xf5,0x7d,0x48,0x37,0xc1
+
+# ATT: vcvthf62hf8 %ymm1, %ymm0
+# INTEL: vcvthf62hf8 ymm0, ymm1
+0x62,0xf5,0x7d,0x28,0x37,0xc1
+
+# ATT: vcvthf62hf8 %xmm1, %xmm0
+# INTEL: vcvthf62hf8 xmm0, xmm1
+0x62,0xf5,0x7d,0x08,0x37,0xc1
+
+# ATT: vcvthf62hf8 %zmm1, %zmm0 {%k1}
+# INTEL: vcvthf62hf8 zmm0 {k1}, zmm1
+0x62,0xf5,0x7d,0x49,0x37,0xc1
+
+# ATT: vcvthf62hf8 %zmm1, %zmm0 {%k1} {z}
+# INTEL: vcvthf62hf8 zmm0 {k1} {z}, zmm1
+0x62,0xf5,0x7d,0xc9,0x37,0xc1
+
+#
+# Group G: VPMOVSSDB - Integer DWord->Byte signed saturation
+#
+
+# ATT: vpmovssdb %zmm1, %xmm0
+# INTEL: vpmovssdb xmm0, zmm1
+0x62,0xf2,0x7e,0x48,0x41,0xc8
+
+# ATT: vpmovssdb %ymm1, %xmm0
+# INTEL: vpmovssdb xmm0, ymm1
+0x62,0xf2,0x7e,0x28,0x41,0xc8
+
+# ATT: vpmovssdb %xmm1, %xmm0
+# INTEL: vpmovssdb xmm0, xmm1
+0x62,0xf2,0x7e,0x08,0x41,0xc8
+
+# ATT: vpmovssdb %zmm1, %xmm0 {%k1}
+# INTEL: vpmovssdb xmm0 {k1}, zmm1
+0x62,0xf2,0x7e,0x49,0x41,0xc8
+
+# ATT: vpmovssdb %zmm1, %xmm0 {%k1} {z}
+# INTEL: vpmovssdb xmm0 {k1} {z}, zmm1
+0x62,0xf2,0x7e,0xc9,0x41,0xc8
+
+#
+# Group H: VUNPACKB - Byte unpack with immediate
+#
+
+# ATT: vunpackb $1, %zmm1, %zmm0
+# INTEL: vunpackb zmm0, zmm1, 1
+0x62,0xf3,0x7c,0x48,0x3d,0xc1,0x01
+
+# ATT: vunpackb $1, %ymm1, %ymm0
+# INTEL: vunpackb ymm0, ymm1, 1
+0x62,0xf3,0x7c,0x28,0x3d,0xc1,0x01
+
+# ATT: vunpackb $1, %xmm1, %xmm0
+# INTEL: vunpackb xmm0, xmm1, 1
+0x62,0xf3,0x7c,0x08,0x3d,0xc1,0x01
+
+# ATT: vunpackb $1, %zmm1, %zmm0 {%k1}
+# INTEL: vunpackb zmm0 {k1}, zmm1, 1
+0x62,0xf3,0x7c,0x49,0x3d,0xc1,0x01
+
+# ATT: vunpackb $1, %zmm1, %zmm0 {%k1} {z}
+# INTEL: vunpackb zmm0 {k1} {z}, zmm1, 1
+0x62,0xf3,0x7c,0xc9,0x3d,0xc1,0x01
diff --git a/llvm/test/MC/Disassembler/X86/avx10_v2_aux-64.txt b/llvm/test/MC/Disassembler/X86/avx10_v2_aux-64.txt
new file mode 100644
index 0000000000000..40a7a366e34f9
--- /dev/null
+++ b/llvm/test/MC/Disassembler/X86/avx10_v2_aux-64.txt
@@ -0,0 +1,460 @@
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+#
+# Group A: PS->8bit truncating conversions
+#
+
+# vcvtps2bf8
+
+# ATT: vcvtps2bf8 %zmm1, %xmm0
+# INTEL: vcvtps2bf8 xmm0, zmm1
+0x62,0xf5,0x7e,0x48,0x39,0xc1
+
+# ATT: vcvtps2bf8 %ymm1, %xmm0
+# INTEL: vcvtps2bf8 xmm0, ymm1
+0x62,0xf5,0x7e,0x28,0x39,0xc1
+
+# ATT: vcvtps2bf8 %xmm1, %xmm0
+# INTEL: vcvtps2bf8 xmm0, xmm1
+0x62,0xf5,0x7e,0x08,0x39,0xc1
+
+# ATT: vcvtps2bf8 %zmm1, %xmm0 {%k1}
+# INTEL: vcvtps2bf8 xmm0 {k1}, zmm1
+0x62,0xf5,0x7e,0x49,0x39,0xc1
+
+# ATT: vcvtps2bf8 %zmm1, %xmm0 {%k1} {z}
+# INTEL: vcvtps2bf8 xmm0 {k1} {z}, zmm1
+0x62,0xf5,0x7e,0xc9,0x39,0xc1
+
+# vcvtps2bf8s
+
+# ATT: vcvtps2bf8s %zmm1, %xmm0
+# INTEL: vcvtps2bf8s xmm0, zmm1
+0x62,0xf5,0x7e,0x48,0x3b,0xc1
+
+# ATT: vcvtps2bf8s %ymm1, %xmm0
+# INTEL: vcvtps2bf8s xmm0, ymm1
+0x62,0xf5,0x7e,0x28,0x3b,0xc1
+
+# ATT: vcvtps2bf8s %xmm1, %xmm0
+# INTEL: vcvtps2bf8s xmm0, xmm1
+0x62,0xf5,0x7e,0x08,0x3b,0xc1
+
+# ATT: vcvtps2bf8s %zmm1, %xmm0 {%k1}
+# INTEL: vcvtps2bf8s xmm0 {k1}, zmm1
+0x62,0xf5,0x7e,0x49,0x3b,0xc1
+
+# ATT: vcvtps2bf8s %zmm1, %xmm0 {%k1} {z}
+# INTEL: vcvtps2bf8s xmm0 {k1} {z}, zmm1
+0x62,0xf5,0x7e,0xc9,0x3b,0xc1
+
+# vcvtps2hf8
+
+# ATT: vcvtps2hf8 %zmm1, %xmm0
+# INTEL: vcvtps2hf8 xmm0, zmm1
+0x62,0xf5,0x7e,0x48,0x38,0xc1
+
+# ATT: vcvtps2hf8 %ymm1, %xmm0
+# INTEL: vcvtps2hf8 xmm0, ymm1
+0x62,0xf5,0x7e,0x28,0x38,0xc1
+
+# ATT: vcvtps2hf8 %xmm1, %xmm0
+# INTEL: vcvtps2hf8 xmm0, xmm1
+0x62,0xf5,0x7e,0x08,0x38,0xc1
+
+# ATT: vcvtps2hf8 %zmm1, %xmm0 {%k1}
+# INTEL: vcvtps2hf8 xmm0 {k1}, zmm1
+0x62,0xf5,0x7e,0x49,0x38,0xc1
+
+# ATT: vcvtps2hf8 %zmm1, %xmm0 {%k1} {z}
+# INTEL: vcvtps2hf8 xmm0 {k1} {z}, zmm1
+0x62,0xf5,0x7e,0xc9,0x38,0xc1
+
+# vcvtps2hf8s
+
+# ATT: vcvtps2hf8s %zmm1, %xmm0
+# INTEL: vcvtps2hf8s xmm0, zmm1
+0x62,0xf5,0x7e,0x48,0x3a,0xc1
+
+# ATT: vcvtps2hf8s %ymm1, %xmm0
+# INTEL: vcvtps2hf8s xmm0, ymm1
+0x62,0xf5,0x7e,0x28,0x3a,0xc1
+
+# ATT: vcvtps2hf8s %xmm1, %xmm0
+# INTEL: vcvtps2hf8s xmm0, xmm1
+0x62,0xf5,0x7e,0x08,0x3a,0xc1
+
+# ATT: vcvtps2hf8s %zmm1, %xmm0 {%k1}
+# INTEL: vcvtps2hf8s xmm0 {k1}, zmm1
+0x62,0xf5,0x7e,0x49,0x3a,0xc1
+
+# ATT: vcvtps2hf8s %zmm1, %xmm0 {%k1} {z}
+# INTEL: vcvtps2hf8s xmm0 {k1} {z}, zmm1
+0x62,0xf5,0x7e,0xc9,0x3a,0xc1
+
+# vcvtrops2hf8
+
+# ATT: vcvtrops2hf8 %zmm1, %xmm0
+# INTEL: vcvtrops2hf8 xmm0, zmm1
+0x62,0xf5,0x7d,0x48,0x38,0xc1
+
+# ATT: vcvtrops2hf8 %ymm1, %xmm0
+# INTEL: vcvtrops2hf8 xmm0, ymm1
+0x62,0xf5,0x7d,0x28,0x38,0xc1
+
+# ATT: vcvtrops2hf8 %xmm1, %xmm0
+# INTEL: vcvtrops2hf8 xmm0, xmm1
+0x62,0xf5,0x7d,0x08,0x38,0xc1
+
+# ATT: vcvtrops2hf8 %zmm1, %xmm0 {%k1}
+# INTEL: vcvtrops2hf8 xmm0 {k1}, zmm1
+0x62,0xf5,0x7d,0x49,0x38,0xc1
+
+# ATT: vcvtrops2hf8 %zmm1, %xmm0 {%k1} {z}
+# INTEL: vcvtrops2hf8 xmm0 {k1} {z}, zmm1
+0x62,0xf5,0x7d,0xc9,0x38,0xc1
+
+# vcvtrops2hf8s
+
+# ATT: vcvtrops2hf8s %zmm1, %xmm0
+# INTEL: vcvtrops2hf8s xmm0, zmm1
+0x62,0xf5,0x7d,0x48,0x3a,0xc1
+
+# ATT: vcvtrops2hf8s %ymm1, %xmm0
+# INTEL: vcvtrops2hf8s xmm0, ymm1
+0x62,0xf5,0x7d,0x28,0x3a,0xc1
+
+# ATT: vcvtrops2hf8s %xmm1, %xmm0
+# INTEL: vcvtrops2hf8s xmm0, xmm1
+0x62,0xf5,0x7d,0x08,0x3a,0xc1
+
+# ATT: vcvtrops2hf8s %zmm1, %xmm0 {%k1}
+# INTEL: vcvtrops2hf8s xmm0 {k1}, zmm1
+0x62,0xf5,0x7d,0x49,0x3a,0xc1
+
+# ATT: vcvtrops2hf8s %zmm1, %xmm0 {%k1} {z}
+# INTEL: vcvtrops2hf8s xmm0 {k1} {z}, zmm1
+0x62,0xf5,0x7d,0xc9,0x3a,0xc1
+
+#
+# Group B: Bias PS->8bit conversions (3-operand)
+#
+
+# vcvtbiasps2bf8
+
+# ATT: vcvtbiasps2bf8 %zmm2, %zmm1, %xmm0
+# INTEL: vcvtbiasps2bf8 xmm0, zmm1, zmm2
+0x62,0xf5,0x74,0x48,0x39,0xc2
+
+# ATT: vcvtbiasps2bf8 %ymm2, %ymm1, %xmm0
+# INTEL: vcvtbiasps2bf8 xmm0, ymm1, ymm2
+0x62,0xf5,0x74,0x28,0x39,0xc2
+
+# ATT: vcvtbiasps2bf8 %xmm2, %xmm1, %xmm0
+# INTEL: vcvtbiasps2bf8 xmm0, xmm1, xmm2
+0x62,0xf5,0x74,0x08,0x39,0xc2
+
+# ATT: vcvtbiasps2bf8 %zmm2, %zmm1, %xmm0 {%k1}
+# INTEL: vcvtbiasps2bf8 xmm0 {k1}, zmm1, zmm2
+0x62,0xf5,0x74,0x49,0x39,0xc2
+
+# ATT: vcvtbiasps2bf8 %zmm2, %zmm1, %xmm0 {%k1} {z}
+# INTEL: vcvtbiasps2bf8 xmm0 {k1} {z}, zmm1, zmm2
+0x62,0xf5,0x74,0xc9,0x39,0xc2
+
+# vcvtbiasps2bf8s
+
+# ATT: vcvtbiasps2bf8s %zmm2, %zmm1, %xmm0
+# INTEL: vcvtbiasps2bf8s xmm0, zmm1, zmm2
+0x62,0xf5,0x74,0x48,0x3b,0xc2
+
+# ATT: vcvtbiasps2bf8s %ymm2, %ymm1, %xmm0
+# INTEL: vcvtbiasps2bf8s xmm0, ymm1, ymm2
+0x62,0xf5,0x74,0x28,0x3b,0xc2
+
+# ATT: vcvtbiasps2bf8s %xmm2, %xmm1, %xmm0
+# INTEL: vcvtbiasps2bf8s xmm0, xmm1, xmm2
+0x62,0xf5,0x74,0x08,0x3b,0xc2
+
+# ATT: vcvtbiasps2bf8s %zmm2, %zmm1, %xmm0 {%k1}
+# INTEL: vcvtbiasps2bf8s xmm0 {k1}, zmm1, zmm2
+0x62,0xf5,0x74,0x49,0x3b,0xc2
+
+# ATT: vcvtbiasps2bf8s %zmm2, %zmm1, %xmm0 {%k1} {z}
+# INTEL: vcvtbiasps2bf8s xmm0 {k1} {z}, zmm1, zmm2
+0x62,0xf5,0x74,0xc9,0x3b,0xc2
+
+# vcvtbiasps2hf8
+
+# ATT: vcvtbiasps2hf8 %zmm2, %zmm1, %xmm0
+# INTEL: vcvtbiasps2hf8 xmm0, zmm1, zmm2
+0x62,0xf5,0x74,0x48,0x38,0xc2
+
+# ATT: vcvtbiasps2hf8 %ymm2, %ymm1, %xmm0
+# INTEL: vcvtbiasps2hf8 xmm0, ymm1, ymm2
+0x62,0xf5,0x74,0x28,0x38,0xc2
+
+# ATT: vcvtbiasps2hf8 %xmm2, %xmm1, %xmm0
+# INTEL: vcvtbiasps2hf8 xmm0, xmm1, xmm2
+0x62,0xf5,0x74,0x08,0x38,0xc2
+
+# ATT: vcvtbiasps2hf8 %zmm2, %zmm1, %xmm0 {%k1}
+# INTEL: vcvtbiasps2hf8 xmm0 {k1}, zmm1, zmm2
+0x62,0xf5,0x74,0x49,0x38,0xc2
+
+# ATT: vcvtbiasps2hf8 %zmm2, %zmm1, %xmm0 {%k1} {z}
+# INTEL: vcvtbiasps2hf8 xmm0 {k1} {z}, zmm1, zmm2
+0x62,0xf5,0x74,0xc9,0x38,0xc2
+
+# vcvtbiasps2hf8s
+
+# ATT: vcvtbiasps2hf8s %zmm2, %zmm1, %xmm0
+# INTEL: vcvtbiasps2hf8s xmm0, zmm1, zmm2
+0x62,0xf5,0x74,0x48,0x3a,0xc2
+
+# ATT: vcvtbiasps2hf8s %ymm2, %ymm1, %xmm0
+# INTEL: vcvtbiasps2hf8s xmm0, ymm1, ymm2
+0x62,0xf5,0x74,0x28,0x3a,0xc2
+
+# ATT: vcvtbiasps2hf8s %xmm2, %xmm1, %xmm0
+# INTEL: vcvtbiasps2hf8s xmm0, xmm1, xmm2
+0x62,0xf5,0x74,0x08,0x3a,0xc2
+
+# ATT: vcvtbiasps2hf8s %zmm2, %zmm1, %xmm0 {%k1}
+# INTEL: vcvtbiasps2hf8s xmm0 {k1}, zmm1, zmm2
+0x62,0xf5,0x74,0x49,0x3a,0xc2
+
+# ATT: vcvtbiasps2hf8s %zmm2, %zmm1, %xmm0 {%k1} {z}
+# INTEL: vcvtbiasps2hf8s xmm0 {k1} {z}, zmm1, zmm2
+0x62,0xf5,0x74,0xc9,0x3a,0xc2
+
+#
+# Group C: 8bit->PS expanding conversions
+#
+
+# vcvtbf82ps
+
+# ATT: vcvtbf82ps %xmm1, %zmm0
+# INTEL: vcvtbf82ps zmm0, xmm1
+0x62,0xf5,0xfc,0x48,0x36,0xc1
+
+# ATT: vcvtbf82ps %xmm1, %ymm0
+# INTEL: vcvtbf82ps ymm0, xmm1
+0x62,0xf5,0xfc,0x28,0x36,0xc1
+
+# ATT: vcvtbf82ps %xmm1, %xmm0
+# INTEL: vcvtbf82ps xmm0, xmm1
+0x62,0xf5,0xfc,0x08,0x36,0xc1
+
+# ATT: vcvtbf82ps %xmm1, %zmm0 {%k1}
+# INTEL: vcvtbf82ps zmm0 {k1}, xmm1
+0x62,0xf5,0xfc,0x49,0x36,0xc1
+
+# ATT: vcvtbf82ps %xmm1, %zmm0 {%k1} {z}
+# INTEL: vcvtbf82ps zmm0 {k1} {z}, xmm1
+0x62,0xf5,0xfc,0xc9,0x36,0xc1
+
+# vcvthf82ps
+
+# ATT: vcvthf82ps %xmm1, %zmm0
+# INTEL: vcvthf82ps zmm0, xmm1
+0x62,0xf5,0x7c,0x48,0x36,0xc1
+
+# ATT: vcvthf82ps %xmm1, %ymm0
+# INTEL: vcvthf82ps ymm0, xmm1
+0x62,0xf5,0x7c,0x28,0x36,0xc1
+
+# ATT: vcvthf82ps %xmm1, %xmm0
+# INTEL: vcvthf82ps xmm0, xmm1
+0x62,0xf5,0x7c,0x08,0x36,0xc1
+
+# ATT: vcvthf82ps %xmm1, %zmm0 {%k1}
+# INTEL: vcvthf82ps zmm0 {k1}, xmm1
+0x62,0xf5,0x7c,0x49,0x36,0xc1
+
+# ATT: vcvthf82ps %xmm1, %zmm0 {%k1} {z}
+# INTEL: vcvthf82ps zmm0 {k1} {z}, xmm1
+0x62,0xf5,0x7c,0xc9,0x36,0xc1
+
+#
+# Group D: BF8/HF8->BF4S truncations
+#
+
+# vcvtbf82bf4s
+
+# ATT: vcvtbf82bf4s %zmm1, %ymm0
+# INTEL: vcvtbf82bf4s ymm0, zmm1
+0x62,0xf5,0xfe,0x48,0x3d,0xc8
+
+# ATT: vcvtbf82bf4s %ymm1, %xmm0
+# INTEL: vcvtbf82bf4s xmm0, ymm1
+0x62,0xf5,0xfe,0x28,0x3d,0xc8
+
+# ATT: vcvtbf82bf4s %xmm1, %xmm0
+# INTEL: vcvtbf82bf4s xmm0, xmm1
+0x62,0xf5,0xfe,0x08,0x3d,0xc8
+
+# vcvthf82bf4s
+
+# ATT: vcvthf82bf4s %zmm1, %ymm0
+# INTEL: vcvthf82bf4s ymm0, zmm1
+0x62,0xf5,0x7e,0x48,0x3d,0xc8
+
+# ATT: vcvthf82bf4s %ymm1, %xmm0
+# INTEL: vcvthf82bf4s xmm0, ymm1
+0x62,0xf5,0x7e,0x28,0x3d,0xc8
+
+# ATT: vcvthf82bf4s %xmm1, %xmm0
+# INTEL: vcvthf82bf4s xmm0, xmm1
+0x62,0xf5,0x7e,0x08,0x3d,0xc8
+
+#
+# Group E: Same-size reg-only conversions (no masking)
+#
+
+# vcvtbf82bf6s
+
+# ATT: vcvtbf82bf6s %zmm1, %zmm0
+# INTEL: vcvtbf82bf6s zmm0, zmm1
+0x62,0xf5,0xfe,0x48,0x3e,0xc1
+
+# ATT: vcvtbf82bf6s %ymm1, %ymm0
+# INTEL: vcvtbf82bf6s ymm0, ymm1
+0x62,0xf5,0xfe,0x28,0x3e,0xc1
+
+# ATT: vcvtbf82bf6s %xmm1, %xmm0
+# INTEL: vcvtbf82bf6s xmm0, xmm1
+0x62,0xf5,0xfe,0x08,0x3e,0xc1
+
+# vcvthf82hf6s
+
+# ATT: vcvthf82hf6s %zmm1, %zmm0
+# INTEL: vcvthf82hf6s zmm0, zmm1
+0x62,0xf5,0x7e,0x48,0x3c,0xc1
+
+# ATT: vcvthf82hf6s %ymm1, %ymm0
+# INTEL: vcvthf82hf6s ymm0, ymm1
+0x62,0xf5,0x7e,0x28,0x3c,0xc1
+
+# ATT: vcvthf82hf6s %xmm1, %xmm0
+# INTEL: vcvthf82hf6s xmm0, xmm1
+0x62,0xf5,0x7e,0x08,0x3c,0xc1
+
+#
+# Group F: Expanding/same-size conversions with masking
+#
+
+# vcvtbf42hf8
+
+# ATT: vcvtbf42hf8 %ymm1, %zmm0
+# INTEL: vcvtbf42hf8 zmm0, ymm1
+0x62,0xf5,0x7c,0x48,0x37,0xc1
+
+# ATT: vcvtbf42hf8 %xmm1, %ymm0
+# INTEL: vcvtbf42hf8 ymm0, xmm1
+0x62,0xf5,0x7c,0x28,0x37,0xc1
+
+# ATT: vcvtbf42hf8 %xmm1, %xmm0
+# INTEL: vcvtbf42hf8 xmm0, xmm1
+0x62,0xf5,0x7c,0x08,0x37,0xc1
+
+# ATT: vcvtbf42hf8 %ymm1, %zmm0 {%k1}
+# INTEL: vcvtbf42hf8 zmm0 {k1}, ymm1
+0x62,0xf5,0x7c,0x49,0x37,0xc1
+
+# ATT: vcvtbf42hf8 %ymm1, %zmm0 {%k1} {z}
+# INTEL: vcvtbf42hf8 zmm0 {k1} {z}, ymm1
+0x62,0xf5,0x7c,0xc9,0x37,0xc1
+
+# vcvtbf62hf8
+
+# ATT: vcvtbf62hf8 %zmm1, %zmm0
+# INTEL: vcvtbf62hf8 zmm0, zmm1
+0x62,0xf5,0xfd,0x48,0x37,0xc1
+
+# ATT: vcvtbf62hf8 %ymm1, %ymm0
+# INTEL: vcvtbf62hf8 ymm0, ymm1
+0x62,0xf5,0xfd,0x28,0x37,0xc1
+
+# ATT: vcvtbf62hf8 %xmm1, %xmm0
+# INTEL: vcvtbf62hf8 xmm0, xmm1
+0x62,0xf5,0xfd,0x08,0x37,0xc1
+
+# ATT: vcvtbf62hf8 %zmm1, %zmm0 {%k1}
+# INTEL: vcvtbf62hf8 zmm0 {k1}, zmm1
+0x62,0xf5,0xfd,0x49,0x37,0xc1
+
+# ATT: vcvtbf62hf8 %zmm1, %zmm0 {%k1} {z}
+# INTEL: vcvtbf62hf8 zmm0 {k1} {z}, zmm1
+0x62,0xf5,0xfd,0xc9,0x37,0xc1
+
+# vcvthf62hf8
+
+# ATT: vcvthf62hf8 %zmm1, %zmm0
+# INTEL: vcvthf62hf8 zmm0, zmm1
+0x62,0xf5,0x7d,0x48,0x37,0xc1
+
+# ATT: vcvthf62hf8 %ymm1, %ymm0
+# INTEL: vcvthf62hf8 ymm0, ymm1
+0x62,0xf5,0x7d,0x28,0x37,0xc1
+
+# ATT: vcvthf62hf8 %xmm1, %xmm0
+# INTEL: vcvthf62hf8 xmm0, xmm1
+0x62,0xf5,0x7d,0x08,0x37,0xc1
+
+# ATT: vcvthf62hf8 %zmm1, %zmm0 {%k1}
+# INTEL: vcvthf62hf8 zmm0 {k1}, zmm1
+0x62,0xf5,0x7d,0x49,0x37,0xc1
+
+# ATT: vcvthf62hf8 %zmm1, %zmm0 {%k1} {z}
+# INTEL: vcvthf62hf8 zmm0 {k1} {z}, zmm1
+0x62,0xf5,0x7d,0xc9,0x37,0xc1
+
+#
+# Group G: VPMOVSSDB - Integer DWord->Byte signed saturation
+#
+
+# ATT: vpmovssdb %zmm1, %xmm0
+# INTEL: vpmovssdb xmm0, zmm1
+0x62,0xf2,0x7e,0x48,0x41,0xc8
+
+# ATT: vpmovssdb %ymm1, %xmm0
+# INTEL: vpmovssdb xmm0, ymm1
+0x62,0xf2,0x7e,0x28,0x41,0xc8
+
+# ATT: vpmovssdb %xmm1, %xmm0
+# INTEL: vpmovssdb xmm0, xmm1
+0x62,0xf2,0x7e,0x08,0x41,0xc8
+
+# ATT: vpmovssdb %zmm1, %xmm0 {%k1}
+# INTEL: vpmovssdb xmm0 {k1}, zmm1
+0x62,0xf2,0x7e,0x49,0x41,0xc8
+
+# ATT: vpmovssdb %zmm1, %xmm0 {%k1} {z}
+# INTEL: vpmovssdb xmm0 {k1} {z}, zmm1
+0x62,0xf2,0x7e,0xc9,0x41,0xc8
+
+#
+# Group H: VUNPACKB - Byte unpack with immediate
+#
+
+# ATT: vunpackb $1, %zmm1, %zmm0
+# INTEL: vunpackb zmm0, zmm1, 1
+0x62,0xf3,0x7c,0x48,0x3d,0xc1,0x01
+
+# ATT: vunpackb $1, %ymm1, %ymm0
+# INTEL: vunpackb ymm0, ymm1, 1
+0x62,0xf3,0x7c,0x28,0x3d,0xc1,0x01
+
+# ATT: vunpackb $1, %xmm1, %xmm0
+# INTEL: vunpackb xmm0, xmm1, 1
+0x62,0xf3,0x7c,0x08,0x3d,0xc1,0x01
+
+# ATT: vunpackb $1, %zmm1, %zmm0 {%k1}
+# INTEL: vunpackb zmm0 {k1}, zmm1, 1
+0x62,0xf3,0x7c,0x49,0x3d,0xc1,0x01
+
+# ATT: vunpackb $1, %zmm1, %zmm0 {%k1} {z}
+# INTEL: vunpackb zmm0 {k1} {z}, zmm1, 1
+0x62,0xf3,0x7c,0xc9,0x3d,0xc1,0x01
diff --git a/llvm/test/MC/X86/avx10_v2_aux-att-32.s b/llvm/test/MC/X86/avx10_v2_aux-att-32.s
new file mode 100644
index 0000000000000..10c4ed5bd3259
--- /dev/null
+++ b/llvm/test/MC/X86/avx10_v2_aux-att-32.s
@@ -0,0 +1,463 @@
+// RUN: llvm-mc -triple i386 --show-encoding -mattr=+avx10-v2-aux,+avx512vl %s | FileCheck %s
+
+//
+// Group A: PS->8bit truncating conversions
+//
+
+// vcvtps2bf8
+
+// CHECK: vcvtps2bf8 %zmm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x7e,0x48,0x39,0xc1]
+ vcvtps2bf8 %zmm1, %xmm0
+
+// CHECK: vcvtps2bf8 %ymm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x7e,0x28,0x39,0xc1]
+ vcvtps2bf8 %ymm1, %xmm0
+
+// CHECK: vcvtps2bf8 %xmm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x7e,0x08,0x39,0xc1]
+ vcvtps2bf8 %xmm1, %xmm0
+
+// CHECK: vcvtps2bf8 (%edi), %xmm0
+// CHECK: encoding: [0x62,0xf5,0x7e,0x48,0x39,0x07]
+ vcvtps2bf8 (%edi), %xmm0
+
+// CHECK: vcvtps2bf8 %zmm1, %xmm0 {%k1}
+// CHECK: encoding: [0x62,0xf5,0x7e,0x49,0x39,0xc1]
+ vcvtps2bf8 %zmm1, %xmm0 {%k1}
+
+// CHECK: vcvtps2bf8 %zmm1, %xmm0 {%k1} {z}
+// CHECK: encoding: [0x62,0xf5,0x7e,0xc9,0x39,0xc1]
+ vcvtps2bf8 %zmm1, %xmm0 {%k1} {z}
+
+// vcvtps2bf8s
+
+// CHECK: vcvtps2bf8s %zmm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x7e,0x48,0x3b,0xc1]
+ vcvtps2bf8s %zmm1, %xmm0
+
+// CHECK: vcvtps2bf8s %ymm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x7e,0x28,0x3b,0xc1]
+ vcvtps2bf8s %ymm1, %xmm0
+
+// CHECK: vcvtps2bf8s %xmm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x7e,0x08,0x3b,0xc1]
+ vcvtps2bf8s %xmm1, %xmm0
+
+// CHECK: vcvtps2bf8s %zmm1, %xmm0 {%k1}
+// CHECK: encoding: [0x62,0xf5,0x7e,0x49,0x3b,0xc1]
+ vcvtps2bf8s %zmm1, %xmm0 {%k1}
+
+// CHECK: vcvtps2bf8s %zmm1, %xmm0 {%k1} {z}
+// CHECK: encoding: [0x62,0xf5,0x7e,0xc9,0x3b,0xc1]
+ vcvtps2bf8s %zmm1, %xmm0 {%k1} {z}
+
+// vcvtps2hf8
+
+// CHECK: vcvtps2hf8 %zmm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x7e,0x48,0x38,0xc1]
+ vcvtps2hf8 %zmm1, %xmm0
+
+// CHECK: vcvtps2hf8 %ymm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x7e,0x28,0x38,0xc1]
+ vcvtps2hf8 %ymm1, %xmm0
+
+// CHECK: vcvtps2hf8 %xmm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x7e,0x08,0x38,0xc1]
+ vcvtps2hf8 %xmm1, %xmm0
+
+// CHECK: vcvtps2hf8 %zmm1, %xmm0 {%k1}
+// CHECK: encoding: [0x62,0xf5,0x7e,0x49,0x38,0xc1]
+ vcvtps2hf8 %zmm1, %xmm0 {%k1}
+
+// CHECK: vcvtps2hf8 %zmm1, %xmm0 {%k1} {z}
+// CHECK: encoding: [0x62,0xf5,0x7e,0xc9,0x38,0xc1]
+ vcvtps2hf8 %zmm1, %xmm0 {%k1} {z}
+
+// vcvtps2hf8s
+
+// CHECK: vcvtps2hf8s %zmm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x7e,0x48,0x3a,0xc1]
+ vcvtps2hf8s %zmm1, %xmm0
+
+// CHECK: vcvtps2hf8s %ymm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x7e,0x28,0x3a,0xc1]
+ vcvtps2hf8s %ymm1, %xmm0
+
+// CHECK: vcvtps2hf8s %xmm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x7e,0x08,0x3a,0xc1]
+ vcvtps2hf8s %xmm1, %xmm0
+
+// CHECK: vcvtps2hf8s %zmm1, %xmm0 {%k1}
+// CHECK: encoding: [0x62,0xf5,0x7e,0x49,0x3a,0xc1]
+ vcvtps2hf8s %zmm1, %xmm0 {%k1}
+
+// CHECK: vcvtps2hf8s %zmm1, %xmm0 {%k1} {z}
+// CHECK: encoding: [0x62,0xf5,0x7e,0xc9,0x3a,0xc1]
+ vcvtps2hf8s %zmm1, %xmm0 {%k1} {z}
+
+// vcvtrops2hf8
+
+// CHECK: vcvtrops2hf8 %zmm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x7d,0x48,0x38,0xc1]
+ vcvtrops2hf8 %zmm1, %xmm0
+
+// CHECK: vcvtrops2hf8 %ymm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x7d,0x28,0x38,0xc1]
+ vcvtrops2hf8 %ymm1, %xmm0
+
+// CHECK: vcvtrops2hf8 %xmm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x7d,0x08,0x38,0xc1]
+ vcvtrops2hf8 %xmm1, %xmm0
+
+// CHECK: vcvtrops2hf8 %zmm1, %xmm0 {%k1}
+// CHECK: encoding: [0x62,0xf5,0x7d,0x49,0x38,0xc1]
+ vcvtrops2hf8 %zmm1, %xmm0 {%k1}
+
+// CHECK: vcvtrops2hf8 %zmm1, %xmm0 {%k1} {z}
+// CHECK: encoding: [0x62,0xf5,0x7d,0xc9,0x38,0xc1]
+ vcvtrops2hf8 %zmm1, %xmm0 {%k1} {z}
+
+// vcvtrops2hf8s
+
+// CHECK: vcvtrops2hf8s %zmm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x7d,0x48,0x3a,0xc1]
+ vcvtrops2hf8s %zmm1, %xmm0
+
+// CHECK: vcvtrops2hf8s %ymm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x7d,0x28,0x3a,0xc1]
+ vcvtrops2hf8s %ymm1, %xmm0
+
+// CHECK: vcvtrops2hf8s %xmm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x7d,0x08,0x3a,0xc1]
+ vcvtrops2hf8s %xmm1, %xmm0
+
+// CHECK: vcvtrops2hf8s %zmm1, %xmm0 {%k1}
+// CHECK: encoding: [0x62,0xf5,0x7d,0x49,0x3a,0xc1]
+ vcvtrops2hf8s %zmm1, %xmm0 {%k1}
+
+// CHECK: vcvtrops2hf8s %zmm1, %xmm0 {%k1} {z}
+// CHECK: encoding: [0x62,0xf5,0x7d,0xc9,0x3a,0xc1]
+ vcvtrops2hf8s %zmm1, %xmm0 {%k1} {z}
+
+//
+// Group B: Bias PS->8bit conversions (3-operand)
+//
+
+// vcvtbiasps2bf8
+
+// CHECK: vcvtbiasps2bf8 %zmm2, %zmm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x74,0x48,0x39,0xc2]
+ vcvtbiasps2bf8 %zmm2, %zmm1, %xmm0
+
+// CHECK: vcvtbiasps2bf8 %ymm2, %ymm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x74,0x28,0x39,0xc2]
+ vcvtbiasps2bf8 %ymm2, %ymm1, %xmm0
+
+// CHECK: vcvtbiasps2bf8 %xmm2, %xmm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x74,0x08,0x39,0xc2]
+ vcvtbiasps2bf8 %xmm2, %xmm1, %xmm0
+
+// CHECK: vcvtbiasps2bf8 %zmm2, %zmm1, %xmm0 {%k1}
+// CHECK: encoding: [0x62,0xf5,0x74,0x49,0x39,0xc2]
+ vcvtbiasps2bf8 %zmm2, %zmm1, %xmm0 {%k1}
+
+// CHECK: vcvtbiasps2bf8 %zmm2, %zmm1, %xmm0 {%k1} {z}
+// CHECK: encoding: [0x62,0xf5,0x74,0xc9,0x39,0xc2]
+ vcvtbiasps2bf8 %zmm2, %zmm1, %xmm0 {%k1} {z}
+
+// vcvtbiasps2bf8s
+
+// CHECK: vcvtbiasps2bf8s %zmm2, %zmm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x74,0x48,0x3b,0xc2]
+ vcvtbiasps2bf8s %zmm2, %zmm1, %xmm0
+
+// CHECK: vcvtbiasps2bf8s %ymm2, %ymm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x74,0x28,0x3b,0xc2]
+ vcvtbiasps2bf8s %ymm2, %ymm1, %xmm0
+
+// CHECK: vcvtbiasps2bf8s %xmm2, %xmm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x74,0x08,0x3b,0xc2]
+ vcvtbiasps2bf8s %xmm2, %xmm1, %xmm0
+
+// CHECK: vcvtbiasps2bf8s %zmm2, %zmm1, %xmm0 {%k1}
+// CHECK: encoding: [0x62,0xf5,0x74,0x49,0x3b,0xc2]
+ vcvtbiasps2bf8s %zmm2, %zmm1, %xmm0 {%k1}
+
+// CHECK: vcvtbiasps2bf8s %zmm2, %zmm1, %xmm0 {%k1} {z}
+// CHECK: encoding: [0x62,0xf5,0x74,0xc9,0x3b,0xc2]
+ vcvtbiasps2bf8s %zmm2, %zmm1, %xmm0 {%k1} {z}
+
+// vcvtbiasps2hf8
+
+// CHECK: vcvtbiasps2hf8 %zmm2, %zmm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x74,0x48,0x38,0xc2]
+ vcvtbiasps2hf8 %zmm2, %zmm1, %xmm0
+
+// CHECK: vcvtbiasps2hf8 %ymm2, %ymm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x74,0x28,0x38,0xc2]
+ vcvtbiasps2hf8 %ymm2, %ymm1, %xmm0
+
+// CHECK: vcvtbiasps2hf8 %xmm2, %xmm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x74,0x08,0x38,0xc2]
+ vcvtbiasps2hf8 %xmm2, %xmm1, %xmm0
+
+// CHECK: vcvtbiasps2hf8 %zmm2, %zmm1, %xmm0 {%k1}
+// CHECK: encoding: [0x62,0xf5,0x74,0x49,0x38,0xc2]
+ vcvtbiasps2hf8 %zmm2, %zmm1, %xmm0 {%k1}
+
+// CHECK: vcvtbiasps2hf8 %zmm2, %zmm1, %xmm0 {%k1} {z}
+// CHECK: encoding: [0x62,0xf5,0x74,0xc9,0x38,0xc2]
+ vcvtbiasps2hf8 %zmm2, %zmm1, %xmm0 {%k1} {z}
+
+// vcvtbiasps2hf8s
+
+// CHECK: vcvtbiasps2hf8s %zmm2, %zmm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x74,0x48,0x3a,0xc2]
+ vcvtbiasps2hf8s %zmm2, %zmm1, %xmm0
+
+// CHECK: vcvtbiasps2hf8s %ymm2, %ymm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x74,0x28,0x3a,0xc2]
+ vcvtbiasps2hf8s %ymm2, %ymm1, %xmm0
+
+// CHECK: vcvtbiasps2hf8s %xmm2, %xmm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x74,0x08,0x3a,0xc2]
+ vcvtbiasps2hf8s %xmm2, %xmm1, %xmm0
+
+// CHECK: vcvtbiasps2hf8s %zmm2, %zmm1, %xmm0 {%k1}
+// CHECK: encoding: [0x62,0xf5,0x74,0x49,0x3a,0xc2]
+ vcvtbiasps2hf8s %zmm2, %zmm1, %xmm0 {%k1}
+
+// CHECK: vcvtbiasps2hf8s %zmm2, %zmm1, %xmm0 {%k1} {z}
+// CHECK: encoding: [0x62,0xf5,0x74,0xc9,0x3a,0xc2]
+ vcvtbiasps2hf8s %zmm2, %zmm1, %xmm0 {%k1} {z}
+
+//
+// Group C: 8bit->PS expanding conversions
+//
+
+// vcvtbf82ps
+
+// CHECK: vcvtbf82ps %xmm1, %zmm0
+// CHECK: encoding: [0x62,0xf5,0xfc,0x48,0x36,0xc1]
+ vcvtbf82ps %xmm1, %zmm0
+
+// CHECK: vcvtbf82ps %xmm1, %ymm0
+// CHECK: encoding: [0x62,0xf5,0xfc,0x28,0x36,0xc1]
+ vcvtbf82ps %xmm1, %ymm0
+
+// CHECK: vcvtbf82ps %xmm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0xfc,0x08,0x36,0xc1]
+ vcvtbf82ps %xmm1, %xmm0
+
+// CHECK: vcvtbf82ps %xmm1, %zmm0 {%k1}
+// CHECK: encoding: [0x62,0xf5,0xfc,0x49,0x36,0xc1]
+ vcvtbf82ps %xmm1, %zmm0 {%k1}
+
+// CHECK: vcvtbf82ps %xmm1, %zmm0 {%k1} {z}
+// CHECK: encoding: [0x62,0xf5,0xfc,0xc9,0x36,0xc1]
+ vcvtbf82ps %xmm1, %zmm0 {%k1} {z}
+
+// vcvthf82ps
+
+// CHECK: vcvthf82ps %xmm1, %zmm0
+// CHECK: encoding: [0x62,0xf5,0x7c,0x48,0x36,0xc1]
+ vcvthf82ps %xmm1, %zmm0
+
+// CHECK: vcvthf82ps %xmm1, %ymm0
+// CHECK: encoding: [0x62,0xf5,0x7c,0x28,0x36,0xc1]
+ vcvthf82ps %xmm1, %ymm0
+
+// CHECK: vcvthf82ps %xmm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x7c,0x08,0x36,0xc1]
+ vcvthf82ps %xmm1, %xmm0
+
+// CHECK: vcvthf82ps %xmm1, %zmm0 {%k1}
+// CHECK: encoding: [0x62,0xf5,0x7c,0x49,0x36,0xc1]
+ vcvthf82ps %xmm1, %zmm0 {%k1}
+
+// CHECK: vcvthf82ps %xmm1, %zmm0 {%k1} {z}
+// CHECK: encoding: [0x62,0xf5,0x7c,0xc9,0x36,0xc1]
+ vcvthf82ps %xmm1, %zmm0 {%k1} {z}
+
+//
+// Group D: BF8/HF8->BF4S truncations
+//
+
+// vcvtbf82bf4s
+
+// CHECK: vcvtbf82bf4s %zmm1, %ymm0
+// CHECK: encoding: [0x62,0xf5,0xfe,0x48,0x3d,0xc8]
+ vcvtbf82bf4s %zmm1, %ymm0
+
+// CHECK: vcvtbf82bf4s %ymm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0xfe,0x28,0x3d,0xc8]
+ vcvtbf82bf4s %ymm1, %xmm0
+
+// CHECK: vcvtbf82bf4s %xmm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0xfe,0x08,0x3d,0xc8]
+ vcvtbf82bf4s %xmm1, %xmm0
+
+// vcvthf82bf4s
+
+// CHECK: vcvthf82bf4s %zmm1, %ymm0
+// CHECK: encoding: [0x62,0xf5,0x7e,0x48,0x3d,0xc8]
+ vcvthf82bf4s %zmm1, %ymm0
+
+// CHECK: vcvthf82bf4s %ymm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x7e,0x28,0x3d,0xc8]
+ vcvthf82bf4s %ymm1, %xmm0
+
+// CHECK: vcvthf82bf4s %xmm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x7e,0x08,0x3d,0xc8]
+ vcvthf82bf4s %xmm1, %xmm0
+
+//
+// Group E: Same-size reg-only conversions (no masking)
+//
+
+// vcvtbf82bf6s
+
+// CHECK: vcvtbf82bf6s %zmm1, %zmm0
+// CHECK: encoding: [0x62,0xf5,0xfe,0x48,0x3e,0xc1]
+ vcvtbf82bf6s %zmm1, %zmm0
+
+// CHECK: vcvtbf82bf6s %ymm1, %ymm0
+// CHECK: encoding: [0x62,0xf5,0xfe,0x28,0x3e,0xc1]
+ vcvtbf82bf6s %ymm1, %ymm0
+
+// CHECK: vcvtbf82bf6s %xmm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0xfe,0x08,0x3e,0xc1]
+ vcvtbf82bf6s %xmm1, %xmm0
+
+// vcvthf82hf6s
+
+// CHECK: vcvthf82hf6s %zmm1, %zmm0
+// CHECK: encoding: [0x62,0xf5,0x7e,0x48,0x3c,0xc1]
+ vcvthf82hf6s %zmm1, %zmm0
+
+// CHECK: vcvthf82hf6s %ymm1, %ymm0
+// CHECK: encoding: [0x62,0xf5,0x7e,0x28,0x3c,0xc1]
+ vcvthf82hf6s %ymm1, %ymm0
+
+// CHECK: vcvthf82hf6s %xmm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x7e,0x08,0x3c,0xc1]
+ vcvthf82hf6s %xmm1, %xmm0
+
+//
+// Group F: Expanding/same-size conversions with masking
+//
+
+// vcvtbf42hf8
+
+// CHECK: vcvtbf42hf8 %ymm1, %zmm0
+// CHECK: encoding: [0x62,0xf5,0x7c,0x48,0x37,0xc1]
+ vcvtbf42hf8 %ymm1, %zmm0
+
+// CHECK: vcvtbf42hf8 %xmm1, %ymm0
+// CHECK: encoding: [0x62,0xf5,0x7c,0x28,0x37,0xc1]
+ vcvtbf42hf8 %xmm1, %ymm0
+
+// CHECK: vcvtbf42hf8 %xmm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x7c,0x08,0x37,0xc1]
+ vcvtbf42hf8 %xmm1, %xmm0
+
+// CHECK: vcvtbf42hf8 %ymm1, %zmm0 {%k1}
+// CHECK: encoding: [0x62,0xf5,0x7c,0x49,0x37,0xc1]
+ vcvtbf42hf8 %ymm1, %zmm0 {%k1}
+
+// CHECK: vcvtbf42hf8 %ymm1, %zmm0 {%k1} {z}
+// CHECK: encoding: [0x62,0xf5,0x7c,0xc9,0x37,0xc1]
+ vcvtbf42hf8 %ymm1, %zmm0 {%k1} {z}
+
+// vcvtbf62hf8
+
+// CHECK: vcvtbf62hf8 %zmm1, %zmm0
+// CHECK: encoding: [0x62,0xf5,0xfd,0x48,0x37,0xc1]
+ vcvtbf62hf8 %zmm1, %zmm0
+
+// CHECK: vcvtbf62hf8 %ymm1, %ymm0
+// CHECK: encoding: [0x62,0xf5,0xfd,0x28,0x37,0xc1]
+ vcvtbf62hf8 %ymm1, %ymm0
+
+// CHECK: vcvtbf62hf8 %xmm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0xfd,0x08,0x37,0xc1]
+ vcvtbf62hf8 %xmm1, %xmm0
+
+// CHECK: vcvtbf62hf8 %zmm1, %zmm0 {%k1}
+// CHECK: encoding: [0x62,0xf5,0xfd,0x49,0x37,0xc1]
+ vcvtbf62hf8 %zmm1, %zmm0 {%k1}
+
+// CHECK: vcvtbf62hf8 %zmm1, %zmm0 {%k1} {z}
+// CHECK: encoding: [0x62,0xf5,0xfd,0xc9,0x37,0xc1]
+ vcvtbf62hf8 %zmm1, %zmm0 {%k1} {z}
+
+// vcvthf62hf8
+
+// CHECK: vcvthf62hf8 %zmm1, %zmm0
+// CHECK: encoding: [0x62,0xf5,0x7d,0x48,0x37,0xc1]
+ vcvthf62hf8 %zmm1, %zmm0
+
+// CHECK: vcvthf62hf8 %ymm1, %ymm0
+// CHECK: encoding: [0x62,0xf5,0x7d,0x28,0x37,0xc1]
+ vcvthf62hf8 %ymm1, %ymm0
+
+// CHECK: vcvthf62hf8 %xmm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x7d,0x08,0x37,0xc1]
+ vcvthf62hf8 %xmm1, %xmm0
+
+// CHECK: vcvthf62hf8 %zmm1, %zmm0 {%k1}
+// CHECK: encoding: [0x62,0xf5,0x7d,0x49,0x37,0xc1]
+ vcvthf62hf8 %zmm1, %zmm0 {%k1}
+
+// CHECK: vcvthf62hf8 %zmm1, %zmm0 {%k1} {z}
+// CHECK: encoding: [0x62,0xf5,0x7d,0xc9,0x37,0xc1]
+ vcvthf62hf8 %zmm1, %zmm0 {%k1} {z}
+
+//
+// Group G: VPMOVSSDB - Integer DWord->Byte signed saturation
+//
+
+// CHECK: vpmovssdb %zmm1, %xmm0
+// CHECK: encoding: [0x62,0xf2,0x7e,0x48,0x41,0xc8]
+ vpmovssdb %zmm1, %xmm0
+
+// CHECK: vpmovssdb %ymm1, %xmm0
+// CHECK: encoding: [0x62,0xf2,0x7e,0x28,0x41,0xc8]
+ vpmovssdb %ymm1, %xmm0
+
+// CHECK: vpmovssdb %xmm1, %xmm0
+// CHECK: encoding: [0x62,0xf2,0x7e,0x08,0x41,0xc8]
+ vpmovssdb %xmm1, %xmm0
+
+// CHECK: vpmovssdb %zmm1, %xmm0 {%k1}
+// CHECK: encoding: [0x62,0xf2,0x7e,0x49,0x41,0xc8]
+ vpmovssdb %zmm1, %xmm0 {%k1}
+
+// CHECK: vpmovssdb %zmm1, %xmm0 {%k1} {z}
+// CHECK: encoding: [0x62,0xf2,0x7e,0xc9,0x41,0xc8]
+ vpmovssdb %zmm1, %xmm0 {%k1} {z}
+
+//
+// Group H: VUNPACKB - Byte unpack with immediate
+//
+
+// CHECK: vunpackb $1, %zmm1, %zmm0
+// CHECK: encoding: [0x62,0xf3,0x7c,0x48,0x3d,0xc1,0x01]
+ vunpackb $1, %zmm1, %zmm0
+
+// CHECK: vunpackb $1, %ymm1, %ymm0
+// CHECK: encoding: [0x62,0xf3,0x7c,0x28,0x3d,0xc1,0x01]
+ vunpackb $1, %ymm1, %ymm0
+
+// CHECK: vunpackb $1, %xmm1, %xmm0
+// CHECK: encoding: [0x62,0xf3,0x7c,0x08,0x3d,0xc1,0x01]
+ vunpackb $1, %xmm1, %xmm0
+
+// CHECK: vunpackb $1, %zmm1, %zmm0 {%k1}
+// CHECK: encoding: [0x62,0xf3,0x7c,0x49,0x3d,0xc1,0x01]
+ vunpackb $1, %zmm1, %zmm0 {%k1}
+
+// CHECK: vunpackb $1, %zmm1, %zmm0 {%k1} {z}
+// CHECK: encoding: [0x62,0xf3,0x7c,0xc9,0x3d,0xc1,0x01]
+ vunpackb $1, %zmm1, %zmm0 {%k1} {z}
diff --git a/llvm/test/MC/X86/avx10_v2_aux-att-64.s b/llvm/test/MC/X86/avx10_v2_aux-att-64.s
new file mode 100644
index 0000000000000..81154f3d8b33c
--- /dev/null
+++ b/llvm/test/MC/X86/avx10_v2_aux-att-64.s
@@ -0,0 +1,687 @@
+// RUN: llvm-mc -triple x86_64 --show-encoding -mattr=+avx10-v2-aux,+avx512vl %s | FileCheck %s
+
+//
+// Group A: PS->8bit truncating conversions
+//
+
+// vcvtps2bf8
+
+// CHECK: vcvtps2bf8 %zmm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x7e,0x48,0x39,0xc1]
+ vcvtps2bf8 %zmm1, %xmm0
+
+// CHECK: vcvtps2bf8 %ymm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x7e,0x28,0x39,0xc1]
+ vcvtps2bf8 %ymm1, %xmm0
+
+// CHECK: vcvtps2bf8 %xmm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x7e,0x08,0x39,0xc1]
+ vcvtps2bf8 %xmm1, %xmm0
+
+// CHECK: vcvtps2bf8 (%rdi), %xmm0
+// CHECK: encoding: [0x62,0xf5,0x7e,0x48,0x39,0x07]
+ vcvtps2bf8 (%rdi), %xmm0
+
+// CHECK: vcvtps2bf8y (%rdi), %xmm0
+// CHECK: encoding: [0x62,0xf5,0x7e,0x28,0x39,0x07]
+ vcvtps2bf8y (%rdi), %xmm0
+
+// CHECK: vcvtps2bf8x (%rdi), %xmm0
+// CHECK: encoding: [0x62,0xf5,0x7e,0x08,0x39,0x07]
+ vcvtps2bf8x (%rdi), %xmm0
+
+// CHECK: vcvtps2bf8 %zmm1, %xmm0 {%k1}
+// CHECK: encoding: [0x62,0xf5,0x7e,0x49,0x39,0xc1]
+ vcvtps2bf8 %zmm1, %xmm0 {%k1}
+
+// CHECK: vcvtps2bf8 %zmm1, %xmm0 {%k1} {z}
+// CHECK: encoding: [0x62,0xf5,0x7e,0xc9,0x39,0xc1]
+ vcvtps2bf8 %zmm1, %xmm0 {%k1} {z}
+
+// CHECK: vcvtps2bf8 (%rdi){1to16}, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x7e,0x58,0x39,0x07]
+ vcvtps2bf8 (%rdi){1to16}, %xmm0
+
+// vcvtps2bf8s
+
+// CHECK: vcvtps2bf8s %zmm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x7e,0x48,0x3b,0xc1]
+ vcvtps2bf8s %zmm1, %xmm0
+
+// CHECK: vcvtps2bf8s %ymm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x7e,0x28,0x3b,0xc1]
+ vcvtps2bf8s %ymm1, %xmm0
+
+// CHECK: vcvtps2bf8s %xmm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x7e,0x08,0x3b,0xc1]
+ vcvtps2bf8s %xmm1, %xmm0
+
+// CHECK: vcvtps2bf8s (%rdi), %xmm0
+// CHECK: encoding: [0x62,0xf5,0x7e,0x48,0x3b,0x07]
+ vcvtps2bf8s (%rdi), %xmm0
+
+// CHECK: vcvtps2bf8sy (%rdi), %xmm0
+// CHECK: encoding: [0x62,0xf5,0x7e,0x28,0x3b,0x07]
+ vcvtps2bf8sy (%rdi), %xmm0
+
+// CHECK: vcvtps2bf8sx (%rdi), %xmm0
+// CHECK: encoding: [0x62,0xf5,0x7e,0x08,0x3b,0x07]
+ vcvtps2bf8sx (%rdi), %xmm0
+
+// CHECK: vcvtps2bf8s %zmm1, %xmm0 {%k1}
+// CHECK: encoding: [0x62,0xf5,0x7e,0x49,0x3b,0xc1]
+ vcvtps2bf8s %zmm1, %xmm0 {%k1}
+
+// CHECK: vcvtps2bf8s %zmm1, %xmm0 {%k1} {z}
+// CHECK: encoding: [0x62,0xf5,0x7e,0xc9,0x3b,0xc1]
+ vcvtps2bf8s %zmm1, %xmm0 {%k1} {z}
+
+// CHECK: vcvtps2bf8s (%rdi){1to16}, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x7e,0x58,0x3b,0x07]
+ vcvtps2bf8s (%rdi){1to16}, %xmm0
+
+// vcvtps2hf8
+
+// CHECK: vcvtps2hf8 %zmm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x7e,0x48,0x38,0xc1]
+ vcvtps2hf8 %zmm1, %xmm0
+
+// CHECK: vcvtps2hf8 %ymm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x7e,0x28,0x38,0xc1]
+ vcvtps2hf8 %ymm1, %xmm0
+
+// CHECK: vcvtps2hf8 %xmm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x7e,0x08,0x38,0xc1]
+ vcvtps2hf8 %xmm1, %xmm0
+
+// CHECK: vcvtps2hf8 (%rdi), %xmm0
+// CHECK: encoding: [0x62,0xf5,0x7e,0x48,0x38,0x07]
+ vcvtps2hf8 (%rdi), %xmm0
+
+// CHECK: vcvtps2hf8y (%rdi), %xmm0
+// CHECK: encoding: [0x62,0xf5,0x7e,0x28,0x38,0x07]
+ vcvtps2hf8y (%rdi), %xmm0
+
+// CHECK: vcvtps2hf8x (%rdi), %xmm0
+// CHECK: encoding: [0x62,0xf5,0x7e,0x08,0x38,0x07]
+ vcvtps2hf8x (%rdi), %xmm0
+
+// CHECK: vcvtps2hf8 %zmm1, %xmm0 {%k1}
+// CHECK: encoding: [0x62,0xf5,0x7e,0x49,0x38,0xc1]
+ vcvtps2hf8 %zmm1, %xmm0 {%k1}
+
+// CHECK: vcvtps2hf8 %zmm1, %xmm0 {%k1} {z}
+// CHECK: encoding: [0x62,0xf5,0x7e,0xc9,0x38,0xc1]
+ vcvtps2hf8 %zmm1, %xmm0 {%k1} {z}
+
+// CHECK: vcvtps2hf8 (%rdi){1to16}, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x7e,0x58,0x38,0x07]
+ vcvtps2hf8 (%rdi){1to16}, %xmm0
+
+// vcvtps2hf8s
+
+// CHECK: vcvtps2hf8s %zmm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x7e,0x48,0x3a,0xc1]
+ vcvtps2hf8s %zmm1, %xmm0
+
+// CHECK: vcvtps2hf8s %ymm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x7e,0x28,0x3a,0xc1]
+ vcvtps2hf8s %ymm1, %xmm0
+
+// CHECK: vcvtps2hf8s %xmm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x7e,0x08,0x3a,0xc1]
+ vcvtps2hf8s %xmm1, %xmm0
+
+// CHECK: vcvtps2hf8s (%rdi), %xmm0
+// CHECK: encoding: [0x62,0xf5,0x7e,0x48,0x3a,0x07]
+ vcvtps2hf8s (%rdi), %xmm0
+
+// CHECK: vcvtps2hf8sy (%rdi), %xmm0
+// CHECK: encoding: [0x62,0xf5,0x7e,0x28,0x3a,0x07]
+ vcvtps2hf8sy (%rdi), %xmm0
+
+// CHECK: vcvtps2hf8sx (%rdi), %xmm0
+// CHECK: encoding: [0x62,0xf5,0x7e,0x08,0x3a,0x07]
+ vcvtps2hf8sx (%rdi), %xmm0
+
+// CHECK: vcvtps2hf8s %zmm1, %xmm0 {%k1}
+// CHECK: encoding: [0x62,0xf5,0x7e,0x49,0x3a,0xc1]
+ vcvtps2hf8s %zmm1, %xmm0 {%k1}
+
+// CHECK: vcvtps2hf8s %zmm1, %xmm0 {%k1} {z}
+// CHECK: encoding: [0x62,0xf5,0x7e,0xc9,0x3a,0xc1]
+ vcvtps2hf8s %zmm1, %xmm0 {%k1} {z}
+
+// CHECK: vcvtps2hf8s (%rdi){1to16}, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x7e,0x58,0x3a,0x07]
+ vcvtps2hf8s (%rdi){1to16}, %xmm0
+
+// vcvtrops2hf8
+
+// CHECK: vcvtrops2hf8 %zmm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x7d,0x48,0x38,0xc1]
+ vcvtrops2hf8 %zmm1, %xmm0
+
+// CHECK: vcvtrops2hf8 %ymm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x7d,0x28,0x38,0xc1]
+ vcvtrops2hf8 %ymm1, %xmm0
+
+// CHECK: vcvtrops2hf8 %xmm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x7d,0x08,0x38,0xc1]
+ vcvtrops2hf8 %xmm1, %xmm0
+
+// CHECK: vcvtrops2hf8 (%rdi), %xmm0
+// CHECK: encoding: [0x62,0xf5,0x7d,0x48,0x38,0x07]
+ vcvtrops2hf8 (%rdi), %xmm0
+
+// CHECK: vcvtrops2hf8y (%rdi), %xmm0
+// CHECK: encoding: [0x62,0xf5,0x7d,0x28,0x38,0x07]
+ vcvtrops2hf8y (%rdi), %xmm0
+
+// CHECK: vcvtrops2hf8x (%rdi), %xmm0
+// CHECK: encoding: [0x62,0xf5,0x7d,0x08,0x38,0x07]
+ vcvtrops2hf8x (%rdi), %xmm0
+
+// CHECK: vcvtrops2hf8 %zmm1, %xmm0 {%k1}
+// CHECK: encoding: [0x62,0xf5,0x7d,0x49,0x38,0xc1]
+ vcvtrops2hf8 %zmm1, %xmm0 {%k1}
+
+// CHECK: vcvtrops2hf8 %zmm1, %xmm0 {%k1} {z}
+// CHECK: encoding: [0x62,0xf5,0x7d,0xc9,0x38,0xc1]
+ vcvtrops2hf8 %zmm1, %xmm0 {%k1} {z}
+
+// CHECK: vcvtrops2hf8 (%rdi){1to16}, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x7d,0x58,0x38,0x07]
+ vcvtrops2hf8 (%rdi){1to16}, %xmm0
+
+// vcvtrops2hf8s
+
+// CHECK: vcvtrops2hf8s %zmm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x7d,0x48,0x3a,0xc1]
+ vcvtrops2hf8s %zmm1, %xmm0
+
+// CHECK: vcvtrops2hf8s %ymm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x7d,0x28,0x3a,0xc1]
+ vcvtrops2hf8s %ymm1, %xmm0
+
+// CHECK: vcvtrops2hf8s %xmm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x7d,0x08,0x3a,0xc1]
+ vcvtrops2hf8s %xmm1, %xmm0
+
+// CHECK: vcvtrops2hf8s (%rdi), %xmm0
+// CHECK: encoding: [0x62,0xf5,0x7d,0x48,0x3a,0x07]
+ vcvtrops2hf8s (%rdi), %xmm0
+
+// CHECK: vcvtrops2hf8sy (%rdi), %xmm0
+// CHECK: encoding: [0x62,0xf5,0x7d,0x28,0x3a,0x07]
+ vcvtrops2hf8sy (%rdi), %xmm0
+
+// CHECK: vcvtrops2hf8sx (%rdi), %xmm0
+// CHECK: encoding: [0x62,0xf5,0x7d,0x08,0x3a,0x07]
+ vcvtrops2hf8sx (%rdi), %xmm0
+
+// CHECK: vcvtrops2hf8s %zmm1, %xmm0 {%k1}
+// CHECK: encoding: [0x62,0xf5,0x7d,0x49,0x3a,0xc1]
+ vcvtrops2hf8s %zmm1, %xmm0 {%k1}
+
+// CHECK: vcvtrops2hf8s %zmm1, %xmm0 {%k1} {z}
+// CHECK: encoding: [0x62,0xf5,0x7d,0xc9,0x3a,0xc1]
+ vcvtrops2hf8s %zmm1, %xmm0 {%k1} {z}
+
+// CHECK: vcvtrops2hf8s (%rdi){1to16}, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x7d,0x58,0x3a,0x07]
+ vcvtrops2hf8s (%rdi){1to16}, %xmm0
+
+//
+// Group B: Bias PS->8bit conversions (3-operand)
+//
+
+// vcvtbiasps2bf8
+
+// CHECK: vcvtbiasps2bf8 %zmm2, %zmm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x74,0x48,0x39,0xc2]
+ vcvtbiasps2bf8 %zmm2, %zmm1, %xmm0
+
+// CHECK: vcvtbiasps2bf8 %ymm2, %ymm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x74,0x28,0x39,0xc2]
+ vcvtbiasps2bf8 %ymm2, %ymm1, %xmm0
+
+// CHECK: vcvtbiasps2bf8 %xmm2, %xmm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x74,0x08,0x39,0xc2]
+ vcvtbiasps2bf8 %xmm2, %xmm1, %xmm0
+
+// CHECK: vcvtbiasps2bf8 (%rdi), %zmm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x74,0x48,0x39,0x07]
+ vcvtbiasps2bf8 (%rdi), %zmm1, %xmm0
+
+// CHECK: vcvtbiasps2bf8 (%rdi), %ymm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x74,0x28,0x39,0x07]
+ vcvtbiasps2bf8 (%rdi), %ymm1, %xmm0
+
+// CHECK: vcvtbiasps2bf8 (%rdi), %xmm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x74,0x08,0x39,0x07]
+ vcvtbiasps2bf8 (%rdi), %xmm1, %xmm0
+
+// CHECK: vcvtbiasps2bf8 %zmm2, %zmm1, %xmm0 {%k1}
+// CHECK: encoding: [0x62,0xf5,0x74,0x49,0x39,0xc2]
+ vcvtbiasps2bf8 %zmm2, %zmm1, %xmm0 {%k1}
+
+// CHECK: vcvtbiasps2bf8 %zmm2, %zmm1, %xmm0 {%k1} {z}
+// CHECK: encoding: [0x62,0xf5,0x74,0xc9,0x39,0xc2]
+ vcvtbiasps2bf8 %zmm2, %zmm1, %xmm0 {%k1} {z}
+
+// vcvtbiasps2bf8s
+
+// CHECK: vcvtbiasps2bf8s %zmm2, %zmm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x74,0x48,0x3b,0xc2]
+ vcvtbiasps2bf8s %zmm2, %zmm1, %xmm0
+
+// CHECK: vcvtbiasps2bf8s %ymm2, %ymm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x74,0x28,0x3b,0xc2]
+ vcvtbiasps2bf8s %ymm2, %ymm1, %xmm0
+
+// CHECK: vcvtbiasps2bf8s %xmm2, %xmm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x74,0x08,0x3b,0xc2]
+ vcvtbiasps2bf8s %xmm2, %xmm1, %xmm0
+
+// CHECK: vcvtbiasps2bf8s (%rdi), %zmm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x74,0x48,0x3b,0x07]
+ vcvtbiasps2bf8s (%rdi), %zmm1, %xmm0
+
+// CHECK: vcvtbiasps2bf8s (%rdi), %ymm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x74,0x28,0x3b,0x07]
+ vcvtbiasps2bf8s (%rdi), %ymm1, %xmm0
+
+// CHECK: vcvtbiasps2bf8s (%rdi), %xmm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x74,0x08,0x3b,0x07]
+ vcvtbiasps2bf8s (%rdi), %xmm1, %xmm0
+
+// CHECK: vcvtbiasps2bf8s %zmm2, %zmm1, %xmm0 {%k1}
+// CHECK: encoding: [0x62,0xf5,0x74,0x49,0x3b,0xc2]
+ vcvtbiasps2bf8s %zmm2, %zmm1, %xmm0 {%k1}
+
+// CHECK: vcvtbiasps2bf8s %zmm2, %zmm1, %xmm0 {%k1} {z}
+// CHECK: encoding: [0x62,0xf5,0x74,0xc9,0x3b,0xc2]
+ vcvtbiasps2bf8s %zmm2, %zmm1, %xmm0 {%k1} {z}
+
+// vcvtbiasps2hf8
+
+// CHECK: vcvtbiasps2hf8 %zmm2, %zmm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x74,0x48,0x38,0xc2]
+ vcvtbiasps2hf8 %zmm2, %zmm1, %xmm0
+
+// CHECK: vcvtbiasps2hf8 %ymm2, %ymm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x74,0x28,0x38,0xc2]
+ vcvtbiasps2hf8 %ymm2, %ymm1, %xmm0
+
+// CHECK: vcvtbiasps2hf8 %xmm2, %xmm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x74,0x08,0x38,0xc2]
+ vcvtbiasps2hf8 %xmm2, %xmm1, %xmm0
+
+// CHECK: vcvtbiasps2hf8 (%rdi), %zmm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x74,0x48,0x38,0x07]
+ vcvtbiasps2hf8 (%rdi), %zmm1, %xmm0
+
+// CHECK: vcvtbiasps2hf8 (%rdi), %ymm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x74,0x28,0x38,0x07]
+ vcvtbiasps2hf8 (%rdi), %ymm1, %xmm0
+
+// CHECK: vcvtbiasps2hf8 (%rdi), %xmm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x74,0x08,0x38,0x07]
+ vcvtbiasps2hf8 (%rdi), %xmm1, %xmm0
+
+// CHECK: vcvtbiasps2hf8 %zmm2, %zmm1, %xmm0 {%k1}
+// CHECK: encoding: [0x62,0xf5,0x74,0x49,0x38,0xc2]
+ vcvtbiasps2hf8 %zmm2, %zmm1, %xmm0 {%k1}
+
+// CHECK: vcvtbiasps2hf8 %zmm2, %zmm1, %xmm0 {%k1} {z}
+// CHECK: encoding: [0x62,0xf5,0x74,0xc9,0x38,0xc2]
+ vcvtbiasps2hf8 %zmm2, %zmm1, %xmm0 {%k1} {z}
+
+// vcvtbiasps2hf8s
+
+// CHECK: vcvtbiasps2hf8s %zmm2, %zmm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x74,0x48,0x3a,0xc2]
+ vcvtbiasps2hf8s %zmm2, %zmm1, %xmm0
+
+// CHECK: vcvtbiasps2hf8s %ymm2, %ymm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x74,0x28,0x3a,0xc2]
+ vcvtbiasps2hf8s %ymm2, %ymm1, %xmm0
+
+// CHECK: vcvtbiasps2hf8s %xmm2, %xmm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x74,0x08,0x3a,0xc2]
+ vcvtbiasps2hf8s %xmm2, %xmm1, %xmm0
+
+// CHECK: vcvtbiasps2hf8s (%rdi), %zmm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x74,0x48,0x3a,0x07]
+ vcvtbiasps2hf8s (%rdi), %zmm1, %xmm0
+
+// CHECK: vcvtbiasps2hf8s (%rdi), %ymm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x74,0x28,0x3a,0x07]
+ vcvtbiasps2hf8s (%rdi), %ymm1, %xmm0
+
+// CHECK: vcvtbiasps2hf8s (%rdi), %xmm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x74,0x08,0x3a,0x07]
+ vcvtbiasps2hf8s (%rdi), %xmm1, %xmm0
+
+// CHECK: vcvtbiasps2hf8s %zmm2, %zmm1, %xmm0 {%k1}
+// CHECK: encoding: [0x62,0xf5,0x74,0x49,0x3a,0xc2]
+ vcvtbiasps2hf8s %zmm2, %zmm1, %xmm0 {%k1}
+
+// CHECK: vcvtbiasps2hf8s %zmm2, %zmm1, %xmm0 {%k1} {z}
+// CHECK: encoding: [0x62,0xf5,0x74,0xc9,0x3a,0xc2]
+ vcvtbiasps2hf8s %zmm2, %zmm1, %xmm0 {%k1} {z}
+
+//
+// Group C: 8bit->PS expanding conversions
+//
+
+// vcvtbf82ps
+
+// CHECK: vcvtbf82ps %xmm1, %zmm0
+// CHECK: encoding: [0x62,0xf5,0xfc,0x48,0x36,0xc1]
+ vcvtbf82ps %xmm1, %zmm0
+
+// CHECK: vcvtbf82ps %xmm1, %ymm0
+// CHECK: encoding: [0x62,0xf5,0xfc,0x28,0x36,0xc1]
+ vcvtbf82ps %xmm1, %ymm0
+
+// CHECK: vcvtbf82ps %xmm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0xfc,0x08,0x36,0xc1]
+ vcvtbf82ps %xmm1, %xmm0
+
+// CHECK: vcvtbf82ps (%rdi), %zmm0
+// CHECK: encoding: [0x62,0xf5,0xfc,0x48,0x36,0x07]
+ vcvtbf82ps (%rdi), %zmm0
+
+// CHECK: vcvtbf82ps (%rdi), %ymm0
+// CHECK: encoding: [0x62,0xf5,0xfc,0x28,0x36,0x07]
+ vcvtbf82ps (%rdi), %ymm0
+
+// CHECK: vcvtbf82ps (%rdi), %xmm0
+// CHECK: encoding: [0x62,0xf5,0xfc,0x08,0x36,0x07]
+ vcvtbf82ps (%rdi), %xmm0
+
+// CHECK: vcvtbf82ps %xmm1, %zmm0 {%k1}
+// CHECK: encoding: [0x62,0xf5,0xfc,0x49,0x36,0xc1]
+ vcvtbf82ps %xmm1, %zmm0 {%k1}
+
+// CHECK: vcvtbf82ps %xmm1, %zmm0 {%k1} {z}
+// CHECK: encoding: [0x62,0xf5,0xfc,0xc9,0x36,0xc1]
+ vcvtbf82ps %xmm1, %zmm0 {%k1} {z}
+
+// vcvthf82ps
+
+// CHECK: vcvthf82ps %xmm1, %zmm0
+// CHECK: encoding: [0x62,0xf5,0x7c,0x48,0x36,0xc1]
+ vcvthf82ps %xmm1, %zmm0
+
+// CHECK: vcvthf82ps %xmm1, %ymm0
+// CHECK: encoding: [0x62,0xf5,0x7c,0x28,0x36,0xc1]
+ vcvthf82ps %xmm1, %ymm0
+
+// CHECK: vcvthf82ps %xmm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x7c,0x08,0x36,0xc1]
+ vcvthf82ps %xmm1, %xmm0
+
+// CHECK: vcvthf82ps (%rdi), %zmm0
+// CHECK: encoding: [0x62,0xf5,0x7c,0x48,0x36,0x07]
+ vcvthf82ps (%rdi), %zmm0
+
+// CHECK: vcvthf82ps (%rdi), %ymm0
+// CHECK: encoding: [0x62,0xf5,0x7c,0x28,0x36,0x07]
+ vcvthf82ps (%rdi), %ymm0
+
+// CHECK: vcvthf82ps (%rdi), %xmm0
+// CHECK: encoding: [0x62,0xf5,0x7c,0x08,0x36,0x07]
+ vcvthf82ps (%rdi), %xmm0
+
+// CHECK: vcvthf82ps %xmm1, %zmm0 {%k1}
+// CHECK: encoding: [0x62,0xf5,0x7c,0x49,0x36,0xc1]
+ vcvthf82ps %xmm1, %zmm0 {%k1}
+
+// CHECK: vcvthf82ps %xmm1, %zmm0 {%k1} {z}
+// CHECK: encoding: [0x62,0xf5,0x7c,0xc9,0x36,0xc1]
+ vcvthf82ps %xmm1, %zmm0 {%k1} {z}
+
+//
+// Group D: BF8/HF8->BF4S store-like truncations
+//
+
+// vcvtbf82bf4s
+
+// CHECK: vcvtbf82bf4s %zmm1, %ymm0
+// CHECK: encoding: [0x62,0xf5,0xfe,0x48,0x3d,0xc8]
+ vcvtbf82bf4s %zmm1, %ymm0
+
+// CHECK: vcvtbf82bf4s %ymm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0xfe,0x28,0x3d,0xc8]
+ vcvtbf82bf4s %ymm1, %xmm0
+
+// CHECK: vcvtbf82bf4s %xmm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0xfe,0x08,0x3d,0xc8]
+ vcvtbf82bf4s %xmm1, %xmm0
+
+// CHECK: vcvtbf82bf4s %zmm1, (%rdi)
+// CHECK: encoding: [0x62,0xf5,0xfe,0x48,0x3d,0x0f]
+ vcvtbf82bf4s %zmm1, (%rdi)
+
+// CHECK: vcvtbf82bf4s %ymm1, (%rdi)
+// CHECK: encoding: [0x62,0xf5,0xfe,0x28,0x3d,0x0f]
+ vcvtbf82bf4s %ymm1, (%rdi)
+
+// CHECK: vcvtbf82bf4s %xmm1, (%rdi)
+// CHECK: encoding: [0x62,0xf5,0xfe,0x08,0x3d,0x0f]
+ vcvtbf82bf4s %xmm1, (%rdi)
+
+// vcvthf82bf4s
+
+// CHECK: vcvthf82bf4s %zmm1, %ymm0
+// CHECK: encoding: [0x62,0xf5,0x7e,0x48,0x3d,0xc8]
+ vcvthf82bf4s %zmm1, %ymm0
+
+// CHECK: vcvthf82bf4s %ymm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x7e,0x28,0x3d,0xc8]
+ vcvthf82bf4s %ymm1, %xmm0
+
+// CHECK: vcvthf82bf4s %xmm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x7e,0x08,0x3d,0xc8]
+ vcvthf82bf4s %xmm1, %xmm0
+
+// CHECK: vcvthf82bf4s %zmm1, (%rdi)
+// CHECK: encoding: [0x62,0xf5,0x7e,0x48,0x3d,0x0f]
+ vcvthf82bf4s %zmm1, (%rdi)
+
+// CHECK: vcvthf82bf4s %ymm1, (%rdi)
+// CHECK: encoding: [0x62,0xf5,0x7e,0x28,0x3d,0x0f]
+ vcvthf82bf4s %ymm1, (%rdi)
+
+// CHECK: vcvthf82bf4s %xmm1, (%rdi)
+// CHECK: encoding: [0x62,0xf5,0x7e,0x08,0x3d,0x0f]
+ vcvthf82bf4s %xmm1, (%rdi)
+
+//
+// Group E: Same-size reg-only conversions (no masking)
+//
+
+// vcvtbf82bf6s
+
+// CHECK: vcvtbf82bf6s %zmm1, %zmm0
+// CHECK: encoding: [0x62,0xf5,0xfe,0x48,0x3e,0xc1]
+ vcvtbf82bf6s %zmm1, %zmm0
+
+// CHECK: vcvtbf82bf6s %ymm1, %ymm0
+// CHECK: encoding: [0x62,0xf5,0xfe,0x28,0x3e,0xc1]
+ vcvtbf82bf6s %ymm1, %ymm0
+
+// CHECK: vcvtbf82bf6s %xmm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0xfe,0x08,0x3e,0xc1]
+ vcvtbf82bf6s %xmm1, %xmm0
+
+// vcvthf82hf6s
+
+// CHECK: vcvthf82hf6s %zmm1, %zmm0
+// CHECK: encoding: [0x62,0xf5,0x7e,0x48,0x3c,0xc1]
+ vcvthf82hf6s %zmm1, %zmm0
+
+// CHECK: vcvthf82hf6s %ymm1, %ymm0
+// CHECK: encoding: [0x62,0xf5,0x7e,0x28,0x3c,0xc1]
+ vcvthf82hf6s %ymm1, %ymm0
+
+// CHECK: vcvthf82hf6s %xmm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x7e,0x08,0x3c,0xc1]
+ vcvthf82hf6s %xmm1, %xmm0
+
+//
+// Group F: Expanding/same-size conversions with masking
+//
+
+// vcvtbf42hf8
+
+// CHECK: vcvtbf42hf8 %ymm1, %zmm0
+// CHECK: encoding: [0x62,0xf5,0x7c,0x48,0x37,0xc1]
+ vcvtbf42hf8 %ymm1, %zmm0
+
+// CHECK: vcvtbf42hf8 %xmm1, %ymm0
+// CHECK: encoding: [0x62,0xf5,0x7c,0x28,0x37,0xc1]
+ vcvtbf42hf8 %xmm1, %ymm0
+
+// CHECK: vcvtbf42hf8 %xmm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x7c,0x08,0x37,0xc1]
+ vcvtbf42hf8 %xmm1, %xmm0
+
+// CHECK: vcvtbf42hf8 (%rdi), %zmm0
+// CHECK: encoding: [0x62,0xf5,0x7c,0x48,0x37,0x07]
+ vcvtbf42hf8 (%rdi), %zmm0
+
+// CHECK: vcvtbf42hf8 (%rdi), %ymm0
+// CHECK: encoding: [0x62,0xf5,0x7c,0x28,0x37,0x07]
+ vcvtbf42hf8 (%rdi), %ymm0
+
+// CHECK: vcvtbf42hf8 (%rdi), %xmm0
+// CHECK: encoding: [0x62,0xf5,0x7c,0x08,0x37,0x07]
+ vcvtbf42hf8 (%rdi), %xmm0
+
+// CHECK: vcvtbf42hf8 %ymm1, %zmm0 {%k1}
+// CHECK: encoding: [0x62,0xf5,0x7c,0x49,0x37,0xc1]
+ vcvtbf42hf8 %ymm1, %zmm0 {%k1}
+
+// CHECK: vcvtbf42hf8 %ymm1, %zmm0 {%k1} {z}
+// CHECK: encoding: [0x62,0xf5,0x7c,0xc9,0x37,0xc1]
+ vcvtbf42hf8 %ymm1, %zmm0 {%k1} {z}
+
+// vcvtbf62hf8
+
+// CHECK: vcvtbf62hf8 %zmm1, %zmm0
+// CHECK: encoding: [0x62,0xf5,0xfd,0x48,0x37,0xc1]
+ vcvtbf62hf8 %zmm1, %zmm0
+
+// CHECK: vcvtbf62hf8 %ymm1, %ymm0
+// CHECK: encoding: [0x62,0xf5,0xfd,0x28,0x37,0xc1]
+ vcvtbf62hf8 %ymm1, %ymm0
+
+// CHECK: vcvtbf62hf8 %xmm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0xfd,0x08,0x37,0xc1]
+ vcvtbf62hf8 %xmm1, %xmm0
+
+// CHECK: vcvtbf62hf8 %zmm1, %zmm0 {%k1}
+// CHECK: encoding: [0x62,0xf5,0xfd,0x49,0x37,0xc1]
+ vcvtbf62hf8 %zmm1, %zmm0 {%k1}
+
+// CHECK: vcvtbf62hf8 %zmm1, %zmm0 {%k1} {z}
+// CHECK: encoding: [0x62,0xf5,0xfd,0xc9,0x37,0xc1]
+ vcvtbf62hf8 %zmm1, %zmm0 {%k1} {z}
+
+// vcvthf62hf8
+
+// CHECK: vcvthf62hf8 %zmm1, %zmm0
+// CHECK: encoding: [0x62,0xf5,0x7d,0x48,0x37,0xc1]
+ vcvthf62hf8 %zmm1, %zmm0
+
+// CHECK: vcvthf62hf8 %ymm1, %ymm0
+// CHECK: encoding: [0x62,0xf5,0x7d,0x28,0x37,0xc1]
+ vcvthf62hf8 %ymm1, %ymm0
+
+// CHECK: vcvthf62hf8 %xmm1, %xmm0
+// CHECK: encoding: [0x62,0xf5,0x7d,0x08,0x37,0xc1]
+ vcvthf62hf8 %xmm1, %xmm0
+
+// CHECK: vcvthf62hf8 %zmm1, %zmm0 {%k1}
+// CHECK: encoding: [0x62,0xf5,0x7d,0x49,0x37,0xc1]
+ vcvthf62hf8 %zmm1, %zmm0 {%k1}
+
+// CHECK: vcvthf62hf8 %zmm1, %zmm0 {%k1} {z}
+// CHECK: encoding: [0x62,0xf5,0x7d,0xc9,0x37,0xc1]
+ vcvthf62hf8 %zmm1, %zmm0 {%k1} {z}
+
+//
+// Group G: VPMOVSSDB - Integer DWord->Byte signed saturation
+//
+
+// CHECK: vpmovssdb %zmm1, %xmm0
+// CHECK: encoding: [0x62,0xf2,0x7e,0x48,0x41,0xc8]
+ vpmovssdb %zmm1, %xmm0
+
+// CHECK: vpmovssdb %ymm1, %xmm0
+// CHECK: encoding: [0x62,0xf2,0x7e,0x28,0x41,0xc8]
+ vpmovssdb %ymm1, %xmm0
+
+// CHECK: vpmovssdb %xmm1, %xmm0
+// CHECK: encoding: [0x62,0xf2,0x7e,0x08,0x41,0xc8]
+ vpmovssdb %xmm1, %xmm0
+
+// CHECK: vpmovssdb %zmm1, (%rdi)
+// CHECK: encoding: [0x62,0xf2,0x7e,0x48,0x41,0x0f]
+ vpmovssdb %zmm1, (%rdi)
+
+// CHECK: vpmovssdb %ymm1, (%rdi)
+// CHECK: encoding: [0x62,0xf2,0x7e,0x28,0x41,0x0f]
+ vpmovssdb %ymm1, (%rdi)
+
+// CHECK: vpmovssdb %xmm1, (%rdi)
+// CHECK: encoding: [0x62,0xf2,0x7e,0x08,0x41,0x0f]
+ vpmovssdb %xmm1, (%rdi)
+
+// CHECK: vpmovssdb %zmm1, %xmm0 {%k1}
+// CHECK: encoding: [0x62,0xf2,0x7e,0x49,0x41,0xc8]
+ vpmovssdb %zmm1, %xmm0 {%k1}
+
+// CHECK: vpmovssdb %zmm1, %xmm0 {%k1} {z}
+// CHECK: encoding: [0x62,0xf2,0x7e,0xc9,0x41,0xc8]
+ vpmovssdb %zmm1, %xmm0 {%k1} {z}
+
+//
+// Group H: VUNPACKB - Byte unpack with immediate
+//
+
+// CHECK: vunpackb $1, %zmm1, %zmm0
+// CHECK: encoding: [0x62,0xf3,0x7c,0x48,0x3d,0xc1,0x01]
+ vunpackb $1, %zmm1, %zmm0
+
+// CHECK: vunpackb $1, %ymm1, %ymm0
+// CHECK: encoding: [0x62,0xf3,0x7c,0x28,0x3d,0xc1,0x01]
+ vunpackb $1, %ymm1, %ymm0
+
+// CHECK: vunpackb $1, %xmm1, %xmm0
+// CHECK: encoding: [0x62,0xf3,0x7c,0x08,0x3d,0xc1,0x01]
+ vunpackb $1, %xmm1, %xmm0
+
+// CHECK: vunpackb $1, (%rdi), %zmm0
+// CHECK: encoding: [0x62,0xf3,0x7c,0x48,0x3d,0x07,0x01]
+ vunpackb $1, (%rdi), %zmm0
+
+// CHECK: vunpackb $1, (%rdi), %ymm0
+// CHECK: encoding: [0x62,0xf3,0x7c,0x28,0x3d,0x07,0x01]
+ vunpackb $1, (%rdi), %ymm0
+
+// CHECK: vunpackb $1, (%rdi), %xmm0
+// CHECK: encoding: [0x62,0xf3,0x7c,0x08,0x3d,0x07,0x01]
+ vunpackb $1, (%rdi), %xmm0
+
+// CHECK: vunpackb $1, %zmm1, %zmm0 {%k1}
+// CHECK: encoding: [0x62,0xf3,0x7c,0x49,0x3d,0xc1,0x01]
+ vunpackb $1, %zmm1, %zmm0 {%k1}
+
+// CHECK: vunpackb $1, %zmm1, %zmm0 {%k1} {z}
+// CHECK: encoding: [0x62,0xf3,0x7c,0xc9,0x3d,0xc1,0x01]
+ vunpackb $1, %zmm1, %zmm0 {%k1} {z}
diff --git a/llvm/test/MC/X86/avx10_v2_aux-intel-32.s b/llvm/test/MC/X86/avx10_v2_aux-intel-32.s
new file mode 100644
index 0000000000000..7a06743ed04b8
--- /dev/null
+++ b/llvm/test/MC/X86/avx10_v2_aux-intel-32.s
@@ -0,0 +1,331 @@
+// RUN: llvm-mc -triple i386 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding -mattr=+avx10-v2-aux,+avx512vl %s | FileCheck %s
+
+//
+// Group A: PS->8bit truncating conversions
+//
+
+// vcvtps2bf8
+
+// CHECK: vcvtps2bf8 xmm0, zmm1
+// CHECK: encoding: [0x62,0xf5,0x7e,0x48,0x39,0xc1]
+ vcvtps2bf8 xmm0, zmm1
+
+// CHECK: vcvtps2bf8 xmm0, ymm1
+// CHECK: encoding: [0x62,0xf5,0x7e,0x28,0x39,0xc1]
+ vcvtps2bf8 xmm0, ymm1
+
+// CHECK: vcvtps2bf8 xmm0, xmm1
+// CHECK: encoding: [0x62,0xf5,0x7e,0x08,0x39,0xc1]
+ vcvtps2bf8 xmm0, xmm1
+
+// CHECK: vcvtps2bf8 xmm0 {k1}, zmm1
+// CHECK: encoding: [0x62,0xf5,0x7e,0x49,0x39,0xc1]
+ vcvtps2bf8 xmm0 {k1}, zmm1
+
+// CHECK: vcvtps2bf8 xmm0 {k1} {z}, zmm1
+// CHECK: encoding: [0x62,0xf5,0x7e,0xc9,0x39,0xc1]
+ vcvtps2bf8 xmm0 {k1} {z}, zmm1
+
+// vcvtps2bf8s
+
+// CHECK: vcvtps2bf8s xmm0, zmm1
+// CHECK: encoding: [0x62,0xf5,0x7e,0x48,0x3b,0xc1]
+ vcvtps2bf8s xmm0, zmm1
+
+// CHECK: vcvtps2bf8s xmm0, ymm1
+// CHECK: encoding: [0x62,0xf5,0x7e,0x28,0x3b,0xc1]
+ vcvtps2bf8s xmm0, ymm1
+
+// CHECK: vcvtps2bf8s xmm0, xmm1
+// CHECK: encoding: [0x62,0xf5,0x7e,0x08,0x3b,0xc1]
+ vcvtps2bf8s xmm0, xmm1
+
+// vcvtps2hf8
+
+// CHECK: vcvtps2hf8 xmm0, zmm1
+// CHECK: encoding: [0x62,0xf5,0x7e,0x48,0x38,0xc1]
+ vcvtps2hf8 xmm0, zmm1
+
+// CHECK: vcvtps2hf8 xmm0, ymm1
+// CHECK: encoding: [0x62,0xf5,0x7e,0x28,0x38,0xc1]
+ vcvtps2hf8 xmm0, ymm1
+
+// CHECK: vcvtps2hf8 xmm0, xmm1
+// CHECK: encoding: [0x62,0xf5,0x7e,0x08,0x38,0xc1]
+ vcvtps2hf8 xmm0, xmm1
+
+// vcvtps2hf8s
+
+// CHECK: vcvtps2hf8s xmm0, zmm1
+// CHECK: encoding: [0x62,0xf5,0x7e,0x48,0x3a,0xc1]
+ vcvtps2hf8s xmm0, zmm1
+
+// CHECK: vcvtps2hf8s xmm0, ymm1
+// CHECK: encoding: [0x62,0xf5,0x7e,0x28,0x3a,0xc1]
+ vcvtps2hf8s xmm0, ymm1
+
+// CHECK: vcvtps2hf8s xmm0, xmm1
+// CHECK: encoding: [0x62,0xf5,0x7e,0x08,0x3a,0xc1]
+ vcvtps2hf8s xmm0, xmm1
+
+// vcvtrops2hf8
+
+// CHECK: vcvtrops2hf8 xmm0, zmm1
+// CHECK: encoding: [0x62,0xf5,0x7d,0x48,0x38,0xc1]
+ vcvtrops2hf8 xmm0, zmm1
+
+// CHECK: vcvtrops2hf8 xmm0, ymm1
+// CHECK: encoding: [0x62,0xf5,0x7d,0x28,0x38,0xc1]
+ vcvtrops2hf8 xmm0, ymm1
+
+// CHECK: vcvtrops2hf8 xmm0, xmm1
+// CHECK: encoding: [0x62,0xf5,0x7d,0x08,0x38,0xc1]
+ vcvtrops2hf8 xmm0, xmm1
+
+// vcvtrops2hf8s
+
+// CHECK: vcvtrops2hf8s xmm0, zmm1
+// CHECK: encoding: [0x62,0xf5,0x7d,0x48,0x3a,0xc1]
+ vcvtrops2hf8s xmm0, zmm1
+
+// CHECK: vcvtrops2hf8s xmm0, ymm1
+// CHECK: encoding: [0x62,0xf5,0x7d,0x28,0x3a,0xc1]
+ vcvtrops2hf8s xmm0, ymm1
+
+// CHECK: vcvtrops2hf8s xmm0, xmm1
+// CHECK: encoding: [0x62,0xf5,0x7d,0x08,0x3a,0xc1]
+ vcvtrops2hf8s xmm0, xmm1
+
+//
+// Group B: Bias PS->8bit conversions (3-operand)
+//
+
+// vcvtbiasps2bf8
+
+// CHECK: vcvtbiasps2bf8 xmm0, zmm1, zmm2
+// CHECK: encoding: [0x62,0xf5,0x74,0x48,0x39,0xc2]
+ vcvtbiasps2bf8 xmm0, zmm1, zmm2
+
+// CHECK: vcvtbiasps2bf8 xmm0, ymm1, ymm2
+// CHECK: encoding: [0x62,0xf5,0x74,0x28,0x39,0xc2]
+ vcvtbiasps2bf8 xmm0, ymm1, ymm2
+
+// CHECK: vcvtbiasps2bf8 xmm0, xmm1, xmm2
+// CHECK: encoding: [0x62,0xf5,0x74,0x08,0x39,0xc2]
+ vcvtbiasps2bf8 xmm0, xmm1, xmm2
+
+// vcvtbiasps2bf8s
+
+// CHECK: vcvtbiasps2bf8s xmm0, zmm1, zmm2
+// CHECK: encoding: [0x62,0xf5,0x74,0x48,0x3b,0xc2]
+ vcvtbiasps2bf8s xmm0, zmm1, zmm2
+
+// CHECK: vcvtbiasps2bf8s xmm0, ymm1, ymm2
+// CHECK: encoding: [0x62,0xf5,0x74,0x28,0x3b,0xc2]
+ vcvtbiasps2bf8s xmm0, ymm1, ymm2
+
+// CHECK: vcvtbiasps2bf8s xmm0, xmm1, xmm2
+// CHECK: encoding: [0x62,0xf5,0x74,0x08,0x3b,0xc2]
+ vcvtbiasps2bf8s xmm0, xmm1, xmm2
+
+// vcvtbiasps2hf8
+
+// CHECK: vcvtbiasps2hf8 xmm0, zmm1, zmm2
+// CHECK: encoding: [0x62,0xf5,0x74,0x48,0x38,0xc2]
+ vcvtbiasps2hf8 xmm0, zmm1, zmm2
+
+// CHECK: vcvtbiasps2hf8 xmm0, ymm1, ymm2
+// CHECK: encoding: [0x62,0xf5,0x74,0x28,0x38,0xc2]
+ vcvtbiasps2hf8 xmm0, ymm1, ymm2
+
+// CHECK: vcvtbiasps2hf8 xmm0, xmm1, xmm2
+// CHECK: encoding: [0x62,0xf5,0x74,0x08,0x38,0xc2]
+ vcvtbiasps2hf8 xmm0, xmm1, xmm2
+
+// vcvtbiasps2hf8s
+
+// CHECK: vcvtbiasps2hf8s xmm0, zmm1, zmm2
+// CHECK: encoding: [0x62,0xf5,0x74,0x48,0x3a,0xc2]
+ vcvtbiasps2hf8s xmm0, zmm1, zmm2
+
+// CHECK: vcvtbiasps2hf8s xmm0, ymm1, ymm2
+// CHECK: encoding: [0x62,0xf5,0x74,0x28,0x3a,0xc2]
+ vcvtbiasps2hf8s xmm0, ymm1, ymm2
+
+// CHECK: vcvtbiasps2hf8s xmm0, xmm1, xmm2
+// CHECK: encoding: [0x62,0xf5,0x74,0x08,0x3a,0xc2]
+ vcvtbiasps2hf8s xmm0, xmm1, xmm2
+
+//
+// Group C: 8bit->PS expanding conversions
+//
+
+// vcvtbf82ps
+
+// CHECK: vcvtbf82ps zmm0, xmm1
+// CHECK: encoding: [0x62,0xf5,0xfc,0x48,0x36,0xc1]
+ vcvtbf82ps zmm0, xmm1
+
+// CHECK: vcvtbf82ps ymm0, xmm1
+// CHECK: encoding: [0x62,0xf5,0xfc,0x28,0x36,0xc1]
+ vcvtbf82ps ymm0, xmm1
+
+// CHECK: vcvtbf82ps xmm0, xmm1
+// CHECK: encoding: [0x62,0xf5,0xfc,0x08,0x36,0xc1]
+ vcvtbf82ps xmm0, xmm1
+
+// vcvthf82ps
+
+// CHECK: vcvthf82ps zmm0, xmm1
+// CHECK: encoding: [0x62,0xf5,0x7c,0x48,0x36,0xc1]
+ vcvthf82ps zmm0, xmm1
+
+// CHECK: vcvthf82ps ymm0, xmm1
+// CHECK: encoding: [0x62,0xf5,0x7c,0x28,0x36,0xc1]
+ vcvthf82ps ymm0, xmm1
+
+// CHECK: vcvthf82ps xmm0, xmm1
+// CHECK: encoding: [0x62,0xf5,0x7c,0x08,0x36,0xc1]
+ vcvthf82ps xmm0, xmm1
+
+//
+// Group D: BF8/HF8->BF4S truncations
+//
+
+// vcvtbf82bf4s
+
+// CHECK: vcvtbf82bf4s ymm0, zmm1
+// CHECK: encoding: [0x62,0xf5,0xfe,0x48,0x3d,0xc8]
+ vcvtbf82bf4s ymm0, zmm1
+
+// CHECK: vcvtbf82bf4s xmm0, ymm1
+// CHECK: encoding: [0x62,0xf5,0xfe,0x28,0x3d,0xc8]
+ vcvtbf82bf4s xmm0, ymm1
+
+// CHECK: vcvtbf82bf4s xmm0, xmm1
+// CHECK: encoding: [0x62,0xf5,0xfe,0x08,0x3d,0xc8]
+ vcvtbf82bf4s xmm0, xmm1
+
+// vcvthf82bf4s
+
+// CHECK: vcvthf82bf4s ymm0, zmm1
+// CHECK: encoding: [0x62,0xf5,0x7e,0x48,0x3d,0xc8]
+ vcvthf82bf4s ymm0, zmm1
+
+// CHECK: vcvthf82bf4s xmm0, ymm1
+// CHECK: encoding: [0x62,0xf5,0x7e,0x28,0x3d,0xc8]
+ vcvthf82bf4s xmm0, ymm1
+
+// CHECK: vcvthf82bf4s xmm0, xmm1
+// CHECK: encoding: [0x62,0xf5,0x7e,0x08,0x3d,0xc8]
+ vcvthf82bf4s xmm0, xmm1
+
+//
+// Group E: Same-size reg-only conversions (no masking)
+//
+
+// vcvtbf82bf6s
+
+// CHECK: vcvtbf82bf6s zmm0, zmm1
+// CHECK: encoding: [0x62,0xf5,0xfe,0x48,0x3e,0xc1]
+ vcvtbf82bf6s zmm0, zmm1
+
+// CHECK: vcvtbf82bf6s ymm0, ymm1
+// CHECK: encoding: [0x62,0xf5,0xfe,0x28,0x3e,0xc1]
+ vcvtbf82bf6s ymm0, ymm1
+
+// CHECK: vcvtbf82bf6s xmm0, xmm1
+// CHECK: encoding: [0x62,0xf5,0xfe,0x08,0x3e,0xc1]
+ vcvtbf82bf6s xmm0, xmm1
+
+// vcvthf82hf6s
+
+// CHECK: vcvthf82hf6s zmm0, zmm1
+// CHECK: encoding: [0x62,0xf5,0x7e,0x48,0x3c,0xc1]
+ vcvthf82hf6s zmm0, zmm1
+
+// CHECK: vcvthf82hf6s ymm0, ymm1
+// CHECK: encoding: [0x62,0xf5,0x7e,0x28,0x3c,0xc1]
+ vcvthf82hf6s ymm0, ymm1
+
+// CHECK: vcvthf82hf6s xmm0, xmm1
+// CHECK: encoding: [0x62,0xf5,0x7e,0x08,0x3c,0xc1]
+ vcvthf82hf6s xmm0, xmm1
+
+//
+// Group F: Expanding/same-size conversions with masking
+//
+
+// vcvtbf42hf8
+
+// CHECK: vcvtbf42hf8 zmm0, ymm1
+// CHECK: encoding: [0x62,0xf5,0x7c,0x48,0x37,0xc1]
+ vcvtbf42hf8 zmm0, ymm1
+
+// CHECK: vcvtbf42hf8 ymm0, xmm1
+// CHECK: encoding: [0x62,0xf5,0x7c,0x28,0x37,0xc1]
+ vcvtbf42hf8 ymm0, xmm1
+
+// CHECK: vcvtbf42hf8 xmm0, xmm1
+// CHECK: encoding: [0x62,0xf5,0x7c,0x08,0x37,0xc1]
+ vcvtbf42hf8 xmm0, xmm1
+
+// vcvtbf62hf8
+
+// CHECK: vcvtbf62hf8 zmm0, zmm1
+// CHECK: encoding: [0x62,0xf5,0xfd,0x48,0x37,0xc1]
+ vcvtbf62hf8 zmm0, zmm1
+
+// CHECK: vcvtbf62hf8 ymm0, ymm1
+// CHECK: encoding: [0x62,0xf5,0xfd,0x28,0x37,0xc1]
+ vcvtbf62hf8 ymm0, ymm1
+
+// CHECK: vcvtbf62hf8 xmm0, xmm1
+// CHECK: encoding: [0x62,0xf5,0xfd,0x08,0x37,0xc1]
+ vcvtbf62hf8 xmm0, xmm1
+
+// vcvthf62hf8
+
+// CHECK: vcvthf62hf8 zmm0, zmm1
+// CHECK: encoding: [0x62,0xf5,0x7d,0x48,0x37,0xc1]
+ vcvthf62hf8 zmm0, zmm1
+
+// CHECK: vcvthf62hf8 ymm0, ymm1
+// CHECK: encoding: [0x62,0xf5,0x7d,0x28,0x37,0xc1]
+ vcvthf62hf8 ymm0, ymm1
+
+// CHECK: vcvthf62hf8 xmm0, xmm1
+// CHECK: encoding: [0x62,0xf5,0x7d,0x08,0x37,0xc1]
+ vcvthf62hf8 xmm0, xmm1
+
+//
+// Group G: VPMOVSSDB - Integer DWord->Byte signed saturation
+//
+
+// CHECK: vpmovssdb xmm0, zmm1
+// CHECK: encoding: [0x62,0xf2,0x7e,0x48,0x41,0xc8]
+ vpmovssdb xmm0, zmm1
+
+// CHECK: vpmovssdb xmm0, ymm1
+// CHECK: encoding: [0x62,0xf2,0x7e,0x28,0x41,0xc8]
+ vpmovssdb xmm0, ymm1
+
+// CHECK: vpmovssdb xmm0, xmm1
+// CHECK: encoding: [0x62,0xf2,0x7e,0x08,0x41,0xc8]
+ vpmovssdb xmm0, xmm1
+
+//
+// Group H: VUNPACKB - Byte unpack with immediate
+//
+
+// CHECK: vunpackb zmm0, zmm1, 1
+// CHECK: encoding: [0x62,0xf3,0x7c,0x48,0x3d,0xc1,0x01]
+ vunpackb zmm0, zmm1, 1
+
+// CHECK: vunpackb ymm0, ymm1, 1
+// CHECK: encoding: [0x62,0xf3,0x7c,0x28,0x3d,0xc1,0x01]
+ vunpackb ymm0, ymm1, 1
+
+// CHECK: vunpackb xmm0, xmm1, 1
+// CHECK: encoding: [0x62,0xf3,0x7c,0x08,0x3d,0xc1,0x01]
+ vunpackb xmm0, xmm1, 1
diff --git a/llvm/test/MC/X86/avx10_v2_aux-intel-64.s b/llvm/test/MC/X86/avx10_v2_aux-intel-64.s
new file mode 100644
index 0000000000000..679a8ddc3afe5
--- /dev/null
+++ b/llvm/test/MC/X86/avx10_v2_aux-intel-64.s
@@ -0,0 +1,687 @@
+// RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding -mattr=+avx10-v2-aux,+avx512vl %s | FileCheck %s
+
+//
+// Group A: PS->8bit truncating conversions
+//
+
+// vcvtps2bf8
+
+// CHECK: vcvtps2bf8 xmm0, zmm1
+// CHECK: encoding: [0x62,0xf5,0x7e,0x48,0x39,0xc1]
+ vcvtps2bf8 xmm0, zmm1
+
+// CHECK: vcvtps2bf8 xmm0, ymm1
+// CHECK: encoding: [0x62,0xf5,0x7e,0x28,0x39,0xc1]
+ vcvtps2bf8 xmm0, ymm1
+
+// CHECK: vcvtps2bf8 xmm0, xmm1
+// CHECK: encoding: [0x62,0xf5,0x7e,0x08,0x39,0xc1]
+ vcvtps2bf8 xmm0, xmm1
+
+// CHECK: vcvtps2bf8 xmm0, zmmword ptr [rdi]
+// CHECK: encoding: [0x62,0xf5,0x7e,0x48,0x39,0x07]
+ vcvtps2bf8 xmm0, zmmword ptr [rdi]
+
+// CHECK: vcvtps2bf8 xmm0, ymmword ptr [rdi]
+// CHECK: encoding: [0x62,0xf5,0x7e,0x28,0x39,0x07]
+ vcvtps2bf8 xmm0, ymmword ptr [rdi]
+
+// CHECK: vcvtps2bf8 xmm0, xmmword ptr [rdi]
+// CHECK: encoding: [0x62,0xf5,0x7e,0x08,0x39,0x07]
+ vcvtps2bf8 xmm0, xmmword ptr [rdi]
+
+// CHECK: vcvtps2bf8 xmm0 {k1}, zmm1
+// CHECK: encoding: [0x62,0xf5,0x7e,0x49,0x39,0xc1]
+ vcvtps2bf8 xmm0 {k1}, zmm1
+
+// CHECK: vcvtps2bf8 xmm0 {k1} {z}, zmm1
+// CHECK: encoding: [0x62,0xf5,0x7e,0xc9,0x39,0xc1]
+ vcvtps2bf8 xmm0 {k1} {z}, zmm1
+
+// CHECK: vcvtps2bf8 xmm0, dword ptr [rdi]{1to16}
+// CHECK: encoding: [0x62,0xf5,0x7e,0x58,0x39,0x07]
+ vcvtps2bf8 xmm0, dword ptr [rdi]{1to16}
+
+// vcvtps2bf8s
+
+// CHECK: vcvtps2bf8s xmm0, zmm1
+// CHECK: encoding: [0x62,0xf5,0x7e,0x48,0x3b,0xc1]
+ vcvtps2bf8s xmm0, zmm1
+
+// CHECK: vcvtps2bf8s xmm0, ymm1
+// CHECK: encoding: [0x62,0xf5,0x7e,0x28,0x3b,0xc1]
+ vcvtps2bf8s xmm0, ymm1
+
+// CHECK: vcvtps2bf8s xmm0, xmm1
+// CHECK: encoding: [0x62,0xf5,0x7e,0x08,0x3b,0xc1]
+ vcvtps2bf8s xmm0, xmm1
+
+// CHECK: vcvtps2bf8s xmm0, zmmword ptr [rdi]
+// CHECK: encoding: [0x62,0xf5,0x7e,0x48,0x3b,0x07]
+ vcvtps2bf8s xmm0, zmmword ptr [rdi]
+
+// CHECK: vcvtps2bf8s xmm0, ymmword ptr [rdi]
+// CHECK: encoding: [0x62,0xf5,0x7e,0x28,0x3b,0x07]
+ vcvtps2bf8s xmm0, ymmword ptr [rdi]
+
+// CHECK: vcvtps2bf8s xmm0, xmmword ptr [rdi]
+// CHECK: encoding: [0x62,0xf5,0x7e,0x08,0x3b,0x07]
+ vcvtps2bf8s xmm0, xmmword ptr [rdi]
+
+// CHECK: vcvtps2bf8s xmm0 {k1}, zmm1
+// CHECK: encoding: [0x62,0xf5,0x7e,0x49,0x3b,0xc1]
+ vcvtps2bf8s xmm0 {k1}, zmm1
+
+// CHECK: vcvtps2bf8s xmm0 {k1} {z}, zmm1
+// CHECK: encoding: [0x62,0xf5,0x7e,0xc9,0x3b,0xc1]
+ vcvtps2bf8s xmm0 {k1} {z}, zmm1
+
+// CHECK: vcvtps2bf8s xmm0, dword ptr [rdi]{1to16}
+// CHECK: encoding: [0x62,0xf5,0x7e,0x58,0x3b,0x07]
+ vcvtps2bf8s xmm0, dword ptr [rdi]{1to16}
+
+// vcvtps2hf8
+
+// CHECK: vcvtps2hf8 xmm0, zmm1
+// CHECK: encoding: [0x62,0xf5,0x7e,0x48,0x38,0xc1]
+ vcvtps2hf8 xmm0, zmm1
+
+// CHECK: vcvtps2hf8 xmm0, ymm1
+// CHECK: encoding: [0x62,0xf5,0x7e,0x28,0x38,0xc1]
+ vcvtps2hf8 xmm0, ymm1
+
+// CHECK: vcvtps2hf8 xmm0, xmm1
+// CHECK: encoding: [0x62,0xf5,0x7e,0x08,0x38,0xc1]
+ vcvtps2hf8 xmm0, xmm1
+
+// CHECK: vcvtps2hf8 xmm0, zmmword ptr [rdi]
+// CHECK: encoding: [0x62,0xf5,0x7e,0x48,0x38,0x07]
+ vcvtps2hf8 xmm0, zmmword ptr [rdi]
+
+// CHECK: vcvtps2hf8 xmm0, ymmword ptr [rdi]
+// CHECK: encoding: [0x62,0xf5,0x7e,0x28,0x38,0x07]
+ vcvtps2hf8 xmm0, ymmword ptr [rdi]
+
+// CHECK: vcvtps2hf8 xmm0, xmmword ptr [rdi]
+// CHECK: encoding: [0x62,0xf5,0x7e,0x08,0x38,0x07]
+ vcvtps2hf8 xmm0, xmmword ptr [rdi]
+
+// CHECK: vcvtps2hf8 xmm0 {k1}, zmm1
+// CHECK: encoding: [0x62,0xf5,0x7e,0x49,0x38,0xc1]
+ vcvtps2hf8 xmm0 {k1}, zmm1
+
+// CHECK: vcvtps2hf8 xmm0 {k1} {z}, zmm1
+// CHECK: encoding: [0x62,0xf5,0x7e,0xc9,0x38,0xc1]
+ vcvtps2hf8 xmm0 {k1} {z}, zmm1
+
+// CHECK: vcvtps2hf8 xmm0, dword ptr [rdi]{1to16}
+// CHECK: encoding: [0x62,0xf5,0x7e,0x58,0x38,0x07]
+ vcvtps2hf8 xmm0, dword ptr [rdi]{1to16}
+
+// vcvtps2hf8s
+
+// CHECK: vcvtps2hf8s xmm0, zmm1
+// CHECK: encoding: [0x62,0xf5,0x7e,0x48,0x3a,0xc1]
+ vcvtps2hf8s xmm0, zmm1
+
+// CHECK: vcvtps2hf8s xmm0, ymm1
+// CHECK: encoding: [0x62,0xf5,0x7e,0x28,0x3a,0xc1]
+ vcvtps2hf8s xmm0, ymm1
+
+// CHECK: vcvtps2hf8s xmm0, xmm1
+// CHECK: encoding: [0x62,0xf5,0x7e,0x08,0x3a,0xc1]
+ vcvtps2hf8s xmm0, xmm1
+
+// CHECK: vcvtps2hf8s xmm0, zmmword ptr [rdi]
+// CHECK: encoding: [0x62,0xf5,0x7e,0x48,0x3a,0x07]
+ vcvtps2hf8s xmm0, zmmword ptr [rdi]
+
+// CHECK: vcvtps2hf8s xmm0, ymmword ptr [rdi]
+// CHECK: encoding: [0x62,0xf5,0x7e,0x28,0x3a,0x07]
+ vcvtps2hf8s xmm0, ymmword ptr [rdi]
+
+// CHECK: vcvtps2hf8s xmm0, xmmword ptr [rdi]
+// CHECK: encoding: [0x62,0xf5,0x7e,0x08,0x3a,0x07]
+ vcvtps2hf8s xmm0, xmmword ptr [rdi]
+
+// CHECK: vcvtps2hf8s xmm0 {k1}, zmm1
+// CHECK: encoding: [0x62,0xf5,0x7e,0x49,0x3a,0xc1]
+ vcvtps2hf8s xmm0 {k1}, zmm1
+
+// CHECK: vcvtps2hf8s xmm0 {k1} {z}, zmm1
+// CHECK: encoding: [0x62,0xf5,0x7e,0xc9,0x3a,0xc1]
+ vcvtps2hf8s xmm0 {k1} {z}, zmm1
+
+// CHECK: vcvtps2hf8s xmm0, dword ptr [rdi]{1to16}
+// CHECK: encoding: [0x62,0xf5,0x7e,0x58,0x3a,0x07]
+ vcvtps2hf8s xmm0, dword ptr [rdi]{1to16}
+
+// vcvtrops2hf8
+
+// CHECK: vcvtrops2hf8 xmm0, zmm1
+// CHECK: encoding: [0x62,0xf5,0x7d,0x48,0x38,0xc1]
+ vcvtrops2hf8 xmm0, zmm1
+
+// CHECK: vcvtrops2hf8 xmm0, ymm1
+// CHECK: encoding: [0x62,0xf5,0x7d,0x28,0x38,0xc1]
+ vcvtrops2hf8 xmm0, ymm1
+
+// CHECK: vcvtrops2hf8 xmm0, xmm1
+// CHECK: encoding: [0x62,0xf5,0x7d,0x08,0x38,0xc1]
+ vcvtrops2hf8 xmm0, xmm1
+
+// CHECK: vcvtrops2hf8 xmm0, zmmword ptr [rdi]
+// CHECK: encoding: [0x62,0xf5,0x7d,0x48,0x38,0x07]
+ vcvtrops2hf8 xmm0, zmmword ptr [rdi]
+
+// CHECK: vcvtrops2hf8 xmm0, ymmword ptr [rdi]
+// CHECK: encoding: [0x62,0xf5,0x7d,0x28,0x38,0x07]
+ vcvtrops2hf8 xmm0, ymmword ptr [rdi]
+
+// CHECK: vcvtrops2hf8 xmm0, xmmword ptr [rdi]
+// CHECK: encoding: [0x62,0xf5,0x7d,0x08,0x38,0x07]
+ vcvtrops2hf8 xmm0, xmmword ptr [rdi]
+
+// CHECK: vcvtrops2hf8 xmm0 {k1}, zmm1
+// CHECK: encoding: [0x62,0xf5,0x7d,0x49,0x38,0xc1]
+ vcvtrops2hf8 xmm0 {k1}, zmm1
+
+// CHECK: vcvtrops2hf8 xmm0 {k1} {z}, zmm1
+// CHECK: encoding: [0x62,0xf5,0x7d,0xc9,0x38,0xc1]
+ vcvtrops2hf8 xmm0 {k1} {z}, zmm1
+
+// CHECK: vcvtrops2hf8 xmm0, dword ptr [rdi]{1to16}
+// CHECK: encoding: [0x62,0xf5,0x7d,0x58,0x38,0x07]
+ vcvtrops2hf8 xmm0, dword ptr [rdi]{1to16}
+
+// vcvtrops2hf8s
+
+// CHECK: vcvtrops2hf8s xmm0, zmm1
+// CHECK: encoding: [0x62,0xf5,0x7d,0x48,0x3a,0xc1]
+ vcvtrops2hf8s xmm0, zmm1
+
+// CHECK: vcvtrops2hf8s xmm0, ymm1
+// CHECK: encoding: [0x62,0xf5,0x7d,0x28,0x3a,0xc1]
+ vcvtrops2hf8s xmm0, ymm1
+
+// CHECK: vcvtrops2hf8s xmm0, xmm1
+// CHECK: encoding: [0x62,0xf5,0x7d,0x08,0x3a,0xc1]
+ vcvtrops2hf8s xmm0, xmm1
+
+// CHECK: vcvtrops2hf8s xmm0, zmmword ptr [rdi]
+// CHECK: encoding: [0x62,0xf5,0x7d,0x48,0x3a,0x07]
+ vcvtrops2hf8s xmm0, zmmword ptr [rdi]
+
+// CHECK: vcvtrops2hf8s xmm0, ymmword ptr [rdi]
+// CHECK: encoding: [0x62,0xf5,0x7d,0x28,0x3a,0x07]
+ vcvtrops2hf8s xmm0, ymmword ptr [rdi]
+
+// CHECK: vcvtrops2hf8s xmm0, xmmword ptr [rdi]
+// CHECK: encoding: [0x62,0xf5,0x7d,0x08,0x3a,0x07]
+ vcvtrops2hf8s xmm0, xmmword ptr [rdi]
+
+// CHECK: vcvtrops2hf8s xmm0 {k1}, zmm1
+// CHECK: encoding: [0x62,0xf5,0x7d,0x49,0x3a,0xc1]
+ vcvtrops2hf8s xmm0 {k1}, zmm1
+
+// CHECK: vcvtrops2hf8s xmm0 {k1} {z}, zmm1
+// CHECK: encoding: [0x62,0xf5,0x7d,0xc9,0x3a,0xc1]
+ vcvtrops2hf8s xmm0 {k1} {z}, zmm1
+
+// CHECK: vcvtrops2hf8s xmm0, dword ptr [rdi]{1to16}
+// CHECK: encoding: [0x62,0xf5,0x7d,0x58,0x3a,0x07]
+ vcvtrops2hf8s xmm0, dword ptr [rdi]{1to16}
+
+//
+// Group B: Bias PS->8bit conversions (3-operand)
+//
+
+// vcvtbiasps2bf8
+
+// CHECK: vcvtbiasps2bf8 xmm0, zmm1, zmm2
+// CHECK: encoding: [0x62,0xf5,0x74,0x48,0x39,0xc2]
+ vcvtbiasps2bf8 xmm0, zmm1, zmm2
+
+// CHECK: vcvtbiasps2bf8 xmm0, ymm1, ymm2
+// CHECK: encoding: [0x62,0xf5,0x74,0x28,0x39,0xc2]
+ vcvtbiasps2bf8 xmm0, ymm1, ymm2
+
+// CHECK: vcvtbiasps2bf8 xmm0, xmm1, xmm2
+// CHECK: encoding: [0x62,0xf5,0x74,0x08,0x39,0xc2]
+ vcvtbiasps2bf8 xmm0, xmm1, xmm2
+
+// CHECK: vcvtbiasps2bf8 xmm0, zmm1, zmmword ptr [rdi]
+// CHECK: encoding: [0x62,0xf5,0x74,0x48,0x39,0x07]
+ vcvtbiasps2bf8 xmm0, zmm1, zmmword ptr [rdi]
+
+// CHECK: vcvtbiasps2bf8 xmm0, ymm1, ymmword ptr [rdi]
+// CHECK: encoding: [0x62,0xf5,0x74,0x28,0x39,0x07]
+ vcvtbiasps2bf8 xmm0, ymm1, ymmword ptr [rdi]
+
+// CHECK: vcvtbiasps2bf8 xmm0, xmm1, xmmword ptr [rdi]
+// CHECK: encoding: [0x62,0xf5,0x74,0x08,0x39,0x07]
+ vcvtbiasps2bf8 xmm0, xmm1, xmmword ptr [rdi]
+
+// CHECK: vcvtbiasps2bf8 xmm0 {k1}, zmm1, zmm2
+// CHECK: encoding: [0x62,0xf5,0x74,0x49,0x39,0xc2]
+ vcvtbiasps2bf8 xmm0 {k1}, zmm1, zmm2
+
+// CHECK: vcvtbiasps2bf8 xmm0 {k1} {z}, zmm1, zmm2
+// CHECK: encoding: [0x62,0xf5,0x74,0xc9,0x39,0xc2]
+ vcvtbiasps2bf8 xmm0 {k1} {z}, zmm1, zmm2
+
+// vcvtbiasps2bf8s
+
+// CHECK: vcvtbiasps2bf8s xmm0, zmm1, zmm2
+// CHECK: encoding: [0x62,0xf5,0x74,0x48,0x3b,0xc2]
+ vcvtbiasps2bf8s xmm0, zmm1, zmm2
+
+// CHECK: vcvtbiasps2bf8s xmm0, ymm1, ymm2
+// CHECK: encoding: [0x62,0xf5,0x74,0x28,0x3b,0xc2]
+ vcvtbiasps2bf8s xmm0, ymm1, ymm2
+
+// CHECK: vcvtbiasps2bf8s xmm0, xmm1, xmm2
+// CHECK: encoding: [0x62,0xf5,0x74,0x08,0x3b,0xc2]
+ vcvtbiasps2bf8s xmm0, xmm1, xmm2
+
+// CHECK: vcvtbiasps2bf8s xmm0, zmm1, zmmword ptr [rdi]
+// CHECK: encoding: [0x62,0xf5,0x74,0x48,0x3b,0x07]
+ vcvtbiasps2bf8s xmm0, zmm1, zmmword ptr [rdi]
+
+// CHECK: vcvtbiasps2bf8s xmm0, ymm1, ymmword ptr [rdi]
+// CHECK: encoding: [0x62,0xf5,0x74,0x28,0x3b,0x07]
+ vcvtbiasps2bf8s xmm0, ymm1, ymmword ptr [rdi]
+
+// CHECK: vcvtbiasps2bf8s xmm0, xmm1, xmmword ptr [rdi]
+// CHECK: encoding: [0x62,0xf5,0x74,0x08,0x3b,0x07]
+ vcvtbiasps2bf8s xmm0, xmm1, xmmword ptr [rdi]
+
+// CHECK: vcvtbiasps2bf8s xmm0 {k1}, zmm1, zmm2
+// CHECK: encoding: [0x62,0xf5,0x74,0x49,0x3b,0xc2]
+ vcvtbiasps2bf8s xmm0 {k1}, zmm1, zmm2
+
+// CHECK: vcvtbiasps2bf8s xmm0 {k1} {z}, zmm1, zmm2
+// CHECK: encoding: [0x62,0xf5,0x74,0xc9,0x3b,0xc2]
+ vcvtbiasps2bf8s xmm0 {k1} {z}, zmm1, zmm2
+
+// vcvtbiasps2hf8
+
+// CHECK: vcvtbiasps2hf8 xmm0, zmm1, zmm2
+// CHECK: encoding: [0x62,0xf5,0x74,0x48,0x38,0xc2]
+ vcvtbiasps2hf8 xmm0, zmm1, zmm2
+
+// CHECK: vcvtbiasps2hf8 xmm0, ymm1, ymm2
+// CHECK: encoding: [0x62,0xf5,0x74,0x28,0x38,0xc2]
+ vcvtbiasps2hf8 xmm0, ymm1, ymm2
+
+// CHECK: vcvtbiasps2hf8 xmm0, xmm1, xmm2
+// CHECK: encoding: [0x62,0xf5,0x74,0x08,0x38,0xc2]
+ vcvtbiasps2hf8 xmm0, xmm1, xmm2
+
+// CHECK: vcvtbiasps2hf8 xmm0, zmm1, zmmword ptr [rdi]
+// CHECK: encoding: [0x62,0xf5,0x74,0x48,0x38,0x07]
+ vcvtbiasps2hf8 xmm0, zmm1, zmmword ptr [rdi]
+
+// CHECK: vcvtbiasps2hf8 xmm0, ymm1, ymmword ptr [rdi]
+// CHECK: encoding: [0x62,0xf5,0x74,0x28,0x38,0x07]
+ vcvtbiasps2hf8 xmm0, ymm1, ymmword ptr [rdi]
+
+// CHECK: vcvtbiasps2hf8 xmm0, xmm1, xmmword ptr [rdi]
+// CHECK: encoding: [0x62,0xf5,0x74,0x08,0x38,0x07]
+ vcvtbiasps2hf8 xmm0, xmm1, xmmword ptr [rdi]
+
+// CHECK: vcvtbiasps2hf8 xmm0 {k1}, zmm1, zmm2
+// CHECK: encoding: [0x62,0xf5,0x74,0x49,0x38,0xc2]
+ vcvtbiasps2hf8 xmm0 {k1}, zmm1, zmm2
+
+// CHECK: vcvtbiasps2hf8 xmm0 {k1} {z}, zmm1, zmm2
+// CHECK: encoding: [0x62,0xf5,0x74,0xc9,0x38,0xc2]
+ vcvtbiasps2hf8 xmm0 {k1} {z}, zmm1, zmm2
+
+// vcvtbiasps2hf8s
+
+// CHECK: vcvtbiasps2hf8s xmm0, zmm1, zmm2
+// CHECK: encoding: [0x62,0xf5,0x74,0x48,0x3a,0xc2]
+ vcvtbiasps2hf8s xmm0, zmm1, zmm2
+
+// CHECK: vcvtbiasps2hf8s xmm0, ymm1, ymm2
+// CHECK: encoding: [0x62,0xf5,0x74,0x28,0x3a,0xc2]
+ vcvtbiasps2hf8s xmm0, ymm1, ymm2
+
+// CHECK: vcvtbiasps2hf8s xmm0, xmm1, xmm2
+// CHECK: encoding: [0x62,0xf5,0x74,0x08,0x3a,0xc2]
+ vcvtbiasps2hf8s xmm0, xmm1, xmm2
+
+// CHECK: vcvtbiasps2hf8s xmm0, zmm1, zmmword ptr [rdi]
+// CHECK: encoding: [0x62,0xf5,0x74,0x48,0x3a,0x07]
+ vcvtbiasps2hf8s xmm0, zmm1, zmmword ptr [rdi]
+
+// CHECK: vcvtbiasps2hf8s xmm0, ymm1, ymmword ptr [rdi]
+// CHECK: encoding: [0x62,0xf5,0x74,0x28,0x3a,0x07]
+ vcvtbiasps2hf8s xmm0, ymm1, ymmword ptr [rdi]
+
+// CHECK: vcvtbiasps2hf8s xmm0, xmm1, xmmword ptr [rdi]
+// CHECK: encoding: [0x62,0xf5,0x74,0x08,0x3a,0x07]
+ vcvtbiasps2hf8s xmm0, xmm1, xmmword ptr [rdi]
+
+// CHECK: vcvtbiasps2hf8s xmm0 {k1}, zmm1, zmm2
+// CHECK: encoding: [0x62,0xf5,0x74,0x49,0x3a,0xc2]
+ vcvtbiasps2hf8s xmm0 {k1}, zmm1, zmm2
+
+// CHECK: vcvtbiasps2hf8s xmm0 {k1} {z}, zmm1, zmm2
+// CHECK: encoding: [0x62,0xf5,0x74,0xc9,0x3a,0xc2]
+ vcvtbiasps2hf8s xmm0 {k1} {z}, zmm1, zmm2
+
+//
+// Group C: 8bit->PS expanding conversions
+//
+
+// vcvtbf82ps
+
+// CHECK: vcvtbf82ps zmm0, xmm1
+// CHECK: encoding: [0x62,0xf5,0xfc,0x48,0x36,0xc1]
+ vcvtbf82ps zmm0, xmm1
+
+// CHECK: vcvtbf82ps ymm0, xmm1
+// CHECK: encoding: [0x62,0xf5,0xfc,0x28,0x36,0xc1]
+ vcvtbf82ps ymm0, xmm1
+
+// CHECK: vcvtbf82ps xmm0, xmm1
+// CHECK: encoding: [0x62,0xf5,0xfc,0x08,0x36,0xc1]
+ vcvtbf82ps xmm0, xmm1
+
+// CHECK: vcvtbf82ps zmm0, xmmword ptr [rdi]
+// CHECK: encoding: [0x62,0xf5,0xfc,0x48,0x36,0x07]
+ vcvtbf82ps zmm0, xmmword ptr [rdi]
+
+// CHECK: vcvtbf82ps ymm0, qword ptr [rdi]
+// CHECK: encoding: [0x62,0xf5,0xfc,0x28,0x36,0x07]
+ vcvtbf82ps ymm0, qword ptr [rdi]
+
+// CHECK: vcvtbf82ps xmm0, dword ptr [rdi]
+// CHECK: encoding: [0x62,0xf5,0xfc,0x08,0x36,0x07]
+ vcvtbf82ps xmm0, dword ptr [rdi]
+
+// CHECK: vcvtbf82ps zmm0 {k1}, xmm1
+// CHECK: encoding: [0x62,0xf5,0xfc,0x49,0x36,0xc1]
+ vcvtbf82ps zmm0 {k1}, xmm1
+
+// CHECK: vcvtbf82ps zmm0 {k1} {z}, xmm1
+// CHECK: encoding: [0x62,0xf5,0xfc,0xc9,0x36,0xc1]
+ vcvtbf82ps zmm0 {k1} {z}, xmm1
+
+// vcvthf82ps
+
+// CHECK: vcvthf82ps zmm0, xmm1
+// CHECK: encoding: [0x62,0xf5,0x7c,0x48,0x36,0xc1]
+ vcvthf82ps zmm0, xmm1
+
+// CHECK: vcvthf82ps ymm0, xmm1
+// CHECK: encoding: [0x62,0xf5,0x7c,0x28,0x36,0xc1]
+ vcvthf82ps ymm0, xmm1
+
+// CHECK: vcvthf82ps xmm0, xmm1
+// CHECK: encoding: [0x62,0xf5,0x7c,0x08,0x36,0xc1]
+ vcvthf82ps xmm0, xmm1
+
+// CHECK: vcvthf82ps zmm0, xmmword ptr [rdi]
+// CHECK: encoding: [0x62,0xf5,0x7c,0x48,0x36,0x07]
+ vcvthf82ps zmm0, xmmword ptr [rdi]
+
+// CHECK: vcvthf82ps ymm0, qword ptr [rdi]
+// CHECK: encoding: [0x62,0xf5,0x7c,0x28,0x36,0x07]
+ vcvthf82ps ymm0, qword ptr [rdi]
+
+// CHECK: vcvthf82ps xmm0, dword ptr [rdi]
+// CHECK: encoding: [0x62,0xf5,0x7c,0x08,0x36,0x07]
+ vcvthf82ps xmm0, dword ptr [rdi]
+
+// CHECK: vcvthf82ps zmm0 {k1}, xmm1
+// CHECK: encoding: [0x62,0xf5,0x7c,0x49,0x36,0xc1]
+ vcvthf82ps zmm0 {k1}, xmm1
+
+// CHECK: vcvthf82ps zmm0 {k1} {z}, xmm1
+// CHECK: encoding: [0x62,0xf5,0x7c,0xc9,0x36,0xc1]
+ vcvthf82ps zmm0 {k1} {z}, xmm1
+
+//
+// Group D: BF8/HF8->BF4S store-like truncations
+//
+
+// vcvtbf82bf4s
+
+// CHECK: vcvtbf82bf4s ymm0, zmm1
+// CHECK: encoding: [0x62,0xf5,0xfe,0x48,0x3d,0xc8]
+ vcvtbf82bf4s ymm0, zmm1
+
+// CHECK: vcvtbf82bf4s xmm0, ymm1
+// CHECK: encoding: [0x62,0xf5,0xfe,0x28,0x3d,0xc8]
+ vcvtbf82bf4s xmm0, ymm1
+
+// CHECK: vcvtbf82bf4s xmm0, xmm1
+// CHECK: encoding: [0x62,0xf5,0xfe,0x08,0x3d,0xc8]
+ vcvtbf82bf4s xmm0, xmm1
+
+// CHECK: vcvtbf82bf4s ymmword ptr [rdi], zmm1
+// CHECK: encoding: [0x62,0xf5,0xfe,0x48,0x3d,0x0f]
+ vcvtbf82bf4s ymmword ptr [rdi], zmm1
+
+// CHECK: vcvtbf82bf4s xmmword ptr [rdi], ymm1
+// CHECK: encoding: [0x62,0xf5,0xfe,0x28,0x3d,0x0f]
+ vcvtbf82bf4s xmmword ptr [rdi], ymm1
+
+// CHECK: vcvtbf82bf4s qword ptr [rdi], xmm1
+// CHECK: encoding: [0x62,0xf5,0xfe,0x08,0x3d,0x0f]
+ vcvtbf82bf4s qword ptr [rdi], xmm1
+
+// vcvthf82bf4s
+
+// CHECK: vcvthf82bf4s ymm0, zmm1
+// CHECK: encoding: [0x62,0xf5,0x7e,0x48,0x3d,0xc8]
+ vcvthf82bf4s ymm0, zmm1
+
+// CHECK: vcvthf82bf4s xmm0, ymm1
+// CHECK: encoding: [0x62,0xf5,0x7e,0x28,0x3d,0xc8]
+ vcvthf82bf4s xmm0, ymm1
+
+// CHECK: vcvthf82bf4s xmm0, xmm1
+// CHECK: encoding: [0x62,0xf5,0x7e,0x08,0x3d,0xc8]
+ vcvthf82bf4s xmm0, xmm1
+
+// CHECK: vcvthf82bf4s ymmword ptr [rdi], zmm1
+// CHECK: encoding: [0x62,0xf5,0x7e,0x48,0x3d,0x0f]
+ vcvthf82bf4s ymmword ptr [rdi], zmm1
+
+// CHECK: vcvthf82bf4s xmmword ptr [rdi], ymm1
+// CHECK: encoding: [0x62,0xf5,0x7e,0x28,0x3d,0x0f]
+ vcvthf82bf4s xmmword ptr [rdi], ymm1
+
+// CHECK: vcvthf82bf4s qword ptr [rdi], xmm1
+// CHECK: encoding: [0x62,0xf5,0x7e,0x08,0x3d,0x0f]
+ vcvthf82bf4s qword ptr [rdi], xmm1
+
+//
+// Group E: Same-size reg-only conversions (no masking)
+//
+
+// vcvtbf82bf6s
+
+// CHECK: vcvtbf82bf6s zmm0, zmm1
+// CHECK: encoding: [0x62,0xf5,0xfe,0x48,0x3e,0xc1]
+ vcvtbf82bf6s zmm0, zmm1
+
+// CHECK: vcvtbf82bf6s ymm0, ymm1
+// CHECK: encoding: [0x62,0xf5,0xfe,0x28,0x3e,0xc1]
+ vcvtbf82bf6s ymm0, ymm1
+
+// CHECK: vcvtbf82bf6s xmm0, xmm1
+// CHECK: encoding: [0x62,0xf5,0xfe,0x08,0x3e,0xc1]
+ vcvtbf82bf6s xmm0, xmm1
+
+// vcvthf82hf6s
+
+// CHECK: vcvthf82hf6s zmm0, zmm1
+// CHECK: encoding: [0x62,0xf5,0x7e,0x48,0x3c,0xc1]
+ vcvthf82hf6s zmm0, zmm1
+
+// CHECK: vcvthf82hf6s ymm0, ymm1
+// CHECK: encoding: [0x62,0xf5,0x7e,0x28,0x3c,0xc1]
+ vcvthf82hf6s ymm0, ymm1
+
+// CHECK: vcvthf82hf6s xmm0, xmm1
+// CHECK: encoding: [0x62,0xf5,0x7e,0x08,0x3c,0xc1]
+ vcvthf82hf6s xmm0, xmm1
+
+//
+// Group F: Expanding/same-size conversions with masking
+//
+
+// vcvtbf42hf8
+
+// CHECK: vcvtbf42hf8 zmm0, ymm1
+// CHECK: encoding: [0x62,0xf5,0x7c,0x48,0x37,0xc1]
+ vcvtbf42hf8 zmm0, ymm1
+
+// CHECK: vcvtbf42hf8 ymm0, xmm1
+// CHECK: encoding: [0x62,0xf5,0x7c,0x28,0x37,0xc1]
+ vcvtbf42hf8 ymm0, xmm1
+
+// CHECK: vcvtbf42hf8 xmm0, xmm1
+// CHECK: encoding: [0x62,0xf5,0x7c,0x08,0x37,0xc1]
+ vcvtbf42hf8 xmm0, xmm1
+
+// CHECK: vcvtbf42hf8 zmm0, ymmword ptr [rdi]
+// CHECK: encoding: [0x62,0xf5,0x7c,0x48,0x37,0x07]
+ vcvtbf42hf8 zmm0, ymmword ptr [rdi]
+
+// CHECK: vcvtbf42hf8 ymm0, xmmword ptr [rdi]
+// CHECK: encoding: [0x62,0xf5,0x7c,0x28,0x37,0x07]
+ vcvtbf42hf8 ymm0, xmmword ptr [rdi]
+
+// CHECK: vcvtbf42hf8 xmm0, qword ptr [rdi]
+// CHECK: encoding: [0x62,0xf5,0x7c,0x08,0x37,0x07]
+ vcvtbf42hf8 xmm0, qword ptr [rdi]
+
+// CHECK: vcvtbf42hf8 zmm0 {k1}, ymm1
+// CHECK: encoding: [0x62,0xf5,0x7c,0x49,0x37,0xc1]
+ vcvtbf42hf8 zmm0 {k1}, ymm1
+
+// CHECK: vcvtbf42hf8 zmm0 {k1} {z}, ymm1
+// CHECK: encoding: [0x62,0xf5,0x7c,0xc9,0x37,0xc1]
+ vcvtbf42hf8 zmm0 {k1} {z}, ymm1
+
+// vcvtbf62hf8
+
+// CHECK: vcvtbf62hf8 zmm0, zmm1
+// CHECK: encoding: [0x62,0xf5,0xfd,0x48,0x37,0xc1]
+ vcvtbf62hf8 zmm0, zmm1
+
+// CHECK: vcvtbf62hf8 ymm0, ymm1
+// CHECK: encoding: [0x62,0xf5,0xfd,0x28,0x37,0xc1]
+ vcvtbf62hf8 ymm0, ymm1
+
+// CHECK: vcvtbf62hf8 xmm0, xmm1
+// CHECK: encoding: [0x62,0xf5,0xfd,0x08,0x37,0xc1]
+ vcvtbf62hf8 xmm0, xmm1
+
+// CHECK: vcvtbf62hf8 zmm0 {k1}, zmm1
+// CHECK: encoding: [0x62,0xf5,0xfd,0x49,0x37,0xc1]
+ vcvtbf62hf8 zmm0 {k1}, zmm1
+
+// CHECK: vcvtbf62hf8 zmm0 {k1} {z}, zmm1
+// CHECK: encoding: [0x62,0xf5,0xfd,0xc9,0x37,0xc1]
+ vcvtbf62hf8 zmm0 {k1} {z}, zmm1
+
+// vcvthf62hf8
+
+// CHECK: vcvthf62hf8 zmm0, zmm1
+// CHECK: encoding: [0x62,0xf5,0x7d,0x48,0x37,0xc1]
+ vcvthf62hf8 zmm0, zmm1
+
+// CHECK: vcvthf62hf8 ymm0, ymm1
+// CHECK: encoding: [0x62,0xf5,0x7d,0x28,0x37,0xc1]
+ vcvthf62hf8 ymm0, ymm1
+
+// CHECK: vcvthf62hf8 xmm0, xmm1
+// CHECK: encoding: [0x62,0xf5,0x7d,0x08,0x37,0xc1]
+ vcvthf62hf8 xmm0, xmm1
+
+// CHECK: vcvthf62hf8 zmm0 {k1}, zmm1
+// CHECK: encoding: [0x62,0xf5,0x7d,0x49,0x37,0xc1]
+ vcvthf62hf8 zmm0 {k1}, zmm1
+
+// CHECK: vcvthf62hf8 zmm0 {k1} {z}, zmm1
+// CHECK: encoding: [0x62,0xf5,0x7d,0xc9,0x37,0xc1]
+ vcvthf62hf8 zmm0 {k1} {z}, zmm1
+
+//
+// Group G: VPMOVSSDB - Integer DWord->Byte signed saturation
+//
+
+// CHECK: vpmovssdb xmm0, zmm1
+// CHECK: encoding: [0x62,0xf2,0x7e,0x48,0x41,0xc8]
+ vpmovssdb xmm0, zmm1
+
+// CHECK: vpmovssdb xmm0, ymm1
+// CHECK: encoding: [0x62,0xf2,0x7e,0x28,0x41,0xc8]
+ vpmovssdb xmm0, ymm1
+
+// CHECK: vpmovssdb xmm0, xmm1
+// CHECK: encoding: [0x62,0xf2,0x7e,0x08,0x41,0xc8]
+ vpmovssdb xmm0, xmm1
+
+// CHECK: vpmovssdb xmmword ptr [rdi], zmm1
+// CHECK: encoding: [0x62,0xf2,0x7e,0x48,0x41,0x0f]
+ vpmovssdb xmmword ptr [rdi], zmm1
+
+// CHECK: vpmovssdb qword ptr [rdi], ymm1
+// CHECK: encoding: [0x62,0xf2,0x7e,0x28,0x41,0x0f]
+ vpmovssdb qword ptr [rdi], ymm1
+
+// CHECK: vpmovssdb dword ptr [rdi], xmm1
+// CHECK: encoding: [0x62,0xf2,0x7e,0x08,0x41,0x0f]
+ vpmovssdb dword ptr [rdi], xmm1
+
+// CHECK: vpmovssdb xmm0 {k1}, zmm1
+// CHECK: encoding: [0x62,0xf2,0x7e,0x49,0x41,0xc8]
+ vpmovssdb xmm0 {k1}, zmm1
+
+// CHECK: vpmovssdb xmm0 {k1} {z}, zmm1
+// CHECK: encoding: [0x62,0xf2,0x7e,0xc9,0x41,0xc8]
+ vpmovssdb xmm0 {k1} {z}, zmm1
+
+//
+// Group H: VUNPACKB - Byte unpack with immediate
+//
+
+// CHECK: vunpackb zmm0, zmm1, 1
+// CHECK: encoding: [0x62,0xf3,0x7c,0x48,0x3d,0xc1,0x01]
+ vunpackb zmm0, zmm1, 1
+
+// CHECK: vunpackb ymm0, ymm1, 1
+// CHECK: encoding: [0x62,0xf3,0x7c,0x28,0x3d,0xc1,0x01]
+ vunpackb ymm0, ymm1, 1
+
+// CHECK: vunpackb xmm0, xmm1, 1
+// CHECK: encoding: [0x62,0xf3,0x7c,0x08,0x3d,0xc1,0x01]
+ vunpackb xmm0, xmm1, 1
+
+// CHECK: vunpackb zmm0, zmmword ptr [rdi], 1
+// CHECK: encoding: [0x62,0xf3,0x7c,0x48,0x3d,0x07,0x01]
+ vunpackb zmm0, zmmword ptr [rdi], 1
+
+// CHECK: vunpackb ymm0, ymmword ptr [rdi], 1
+// CHECK: encoding: [0x62,0xf3,0x7c,0x28,0x3d,0x07,0x01]
+ vunpackb ymm0, ymmword ptr [rdi], 1
+
+// CHECK: vunpackb xmm0, xmmword ptr [rdi], 1
+// CHECK: encoding: [0x62,0xf3,0x7c,0x08,0x3d,0x07,0x01]
+ vunpackb xmm0, xmmword ptr [rdi], 1
+
+// CHECK: vunpackb zmm0 {k1}, zmm1, 1
+// CHECK: encoding: [0x62,0xf3,0x7c,0x49,0x3d,0xc1,0x01]
+ vunpackb zmm0 {k1}, zmm1, 1
+
+// CHECK: vunpackb zmm0 {k1} {z}, zmm1, 1
+// CHECK: encoding: [0x62,0xf3,0x7c,0xc9,0x3d,0xc1,0x01]
+ vunpackb zmm0 {k1} {z}, zmm1, 1
diff --git a/llvm/test/TableGen/x86-fold-tables.inc b/llvm/test/TableGen/x86-fold-tables.inc
index b99b6ef60eac7..64f7ff432e83a 100644
--- a/llvm/test/TableGen/x86-fold-tables.inc
+++ b/llvm/test/TableGen/x86-fold-tables.inc
@@ -328,6 +328,9 @@ static const X86FoldTableEntry Table2Addr[] = {
{X86::SUB8ri_NF, X86::SUB8mi_NF, TB_NO_REVERSE},
{X86::SUB8rr, X86::SUB8mr, TB_NO_REVERSE},
{X86::SUB8rr_NF, X86::SUB8mr_NF, TB_NO_REVERSE},
+ {X86::VPMOVSSDZ128rrk, X86::VPMOVSSDZ128mrk, TB_NO_REVERSE},
+ {X86::VPMOVSSDZ256rrk, X86::VPMOVSSDZ256mrk, TB_NO_REVERSE},
+ {X86::VPMOVSSDZrrk, X86::VPMOVSSDZmrk, TB_NO_REVERSE},
{X86::XOR16ri, X86::XOR16mi, TB_NO_REVERSE},
{X86::XOR16ri8, X86::XOR16mi8, TB_NO_REVERSE},
{X86::XOR16ri8_NF, X86::XOR16mi8_NF, TB_NO_REVERSE},
@@ -483,6 +486,10 @@ static const X86FoldTableEntry Table0[] = {
{X86::TEST64rr, X86::TEST64mr, TB_FOLDED_LOAD},
{X86::TEST8ri, X86::TEST8mi, TB_FOLDED_LOAD},
{X86::TEST8rr, X86::TEST8mr, TB_FOLDED_LOAD},
+ {X86::VCVTBF82BF4SZ256rr, X86::VCVTBF82BF4SZ256mr, TB_FOLDED_STORE},
+ {X86::VCVTBF82BF4SZrr, X86::VCVTBF82BF4SZmr, TB_FOLDED_STORE},
+ {X86::VCVTHF82BF4SZ256rr, X86::VCVTHF82BF4SZ256mr, TB_FOLDED_STORE},
+ {X86::VCVTHF82BF4SZrr, X86::VCVTHF82BF4SZmr, TB_FOLDED_STORE},
{X86::VCVTPS2PHYrr, X86::VCVTPS2PHYmr, TB_FOLDED_STORE},
{X86::VCVTPS2PHZ256rr, X86::VCVTPS2PHZ256mr, TB_FOLDED_STORE},
{X86::VCVTPS2PHZrr, X86::VCVTPS2PHZmr, TB_FOLDED_STORE},
@@ -572,6 +579,7 @@ static const X86FoldTableEntry Table0[] = {
{X86::VPMOVSQDZ256rr, X86::VPMOVSQDZ256mr, TB_FOLDED_STORE},
{X86::VPMOVSQDZrr, X86::VPMOVSQDZmr, TB_FOLDED_STORE},
{X86::VPMOVSQWZrr, X86::VPMOVSQWZmr, TB_FOLDED_STORE},
+ {X86::VPMOVSSDZrr, X86::VPMOVSSDZmr, TB_FOLDED_STORE},
{X86::VPMOVSWBZ256rr, X86::VPMOVSWBZ256mr, TB_FOLDED_STORE},
{X86::VPMOVSWBZrr, X86::VPMOVSWBZmr, TB_FOLDED_STORE},
{X86::VPMOVUSDBZrr, X86::VPMOVUSDBZmr, TB_FOLDED_STORE},
@@ -1183,6 +1191,12 @@ static const X86FoldTableEntry Table1[] = {
{X86::VCVTBF162IUBSZ128rr, X86::VCVTBF162IUBSZ128rm, 0},
{X86::VCVTBF162IUBSZ256rr, X86::VCVTBF162IUBSZ256rm, 0},
{X86::VCVTBF162IUBSZrr, X86::VCVTBF162IUBSZrm, 0},
+ {X86::VCVTBF42HF8Z128rr, X86::VCVTBF42HF8Z128rm, TB_NO_REVERSE},
+ {X86::VCVTBF42HF8Z256rr, X86::VCVTBF42HF8Z256rm, 0},
+ {X86::VCVTBF42HF8Zrr, X86::VCVTBF42HF8Zrm, 0},
+ {X86::VCVTBF82PSZ128rr, X86::VCVTBF82PSZ128rm, TB_NO_REVERSE},
+ {X86::VCVTBF82PSZ256rr, X86::VCVTBF82PSZ256rm, TB_NO_REVERSE},
+ {X86::VCVTBF82PSZrr, X86::VCVTBF82PSZrm, 0},
{X86::VCVTDQ2PDYrr, X86::VCVTDQ2PDYrm, 0},
{X86::VCVTDQ2PDZ128rr, X86::VCVTDQ2PDZ128rm, TB_NO_REVERSE},
{X86::VCVTDQ2PDZ256rr, X86::VCVTDQ2PDZ256rm, 0},
@@ -1199,6 +1213,9 @@ static const X86FoldTableEntry Table1[] = {
{X86::VCVTHF82PHZ128rr, X86::VCVTHF82PHZ128rm, TB_NO_REVERSE},
{X86::VCVTHF82PHZ256rr, X86::VCVTHF82PHZ256rm, 0},
{X86::VCVTHF82PHZrr, X86::VCVTHF82PHZrm, 0},
+ {X86::VCVTHF82PSZ128rr, X86::VCVTHF82PSZ128rm, TB_NO_REVERSE},
+ {X86::VCVTHF82PSZ256rr, X86::VCVTHF82PSZ256rm, TB_NO_REVERSE},
+ {X86::VCVTHF82PSZrr, X86::VCVTHF82PSZrm, 0},
{X86::VCVTNEPS2BF16Yrr, X86::VCVTNEPS2BF16Yrm, 0},
{X86::VCVTNEPS2BF16Z128rr, X86::VCVTNEPS2BF16Z128rm, 0},
{X86::VCVTNEPS2BF16Z256rr, X86::VCVTNEPS2BF16Z256rm, 0},
@@ -1273,11 +1290,23 @@ static const X86FoldTableEntry Table1[] = {
{X86::VCVTPH2WZ128rr, X86::VCVTPH2WZ128rm, 0},
{X86::VCVTPH2WZ256rr, X86::VCVTPH2WZ256rm, 0},
{X86::VCVTPH2WZrr, X86::VCVTPH2WZrm, 0},
+ {X86::VCVTPS2BF8SZ128rr, X86::VCVTPS2BF8SZ128rm, 0},
+ {X86::VCVTPS2BF8SZ256rr, X86::VCVTPS2BF8SZ256rm, 0},
+ {X86::VCVTPS2BF8SZrr, X86::VCVTPS2BF8SZrm, 0},
+ {X86::VCVTPS2BF8Z128rr, X86::VCVTPS2BF8Z128rm, 0},
+ {X86::VCVTPS2BF8Z256rr, X86::VCVTPS2BF8Z256rm, 0},
+ {X86::VCVTPS2BF8Zrr, X86::VCVTPS2BF8Zrm, 0},
{X86::VCVTPS2DQYrr, X86::VCVTPS2DQYrm, 0},
{X86::VCVTPS2DQZ128rr, X86::VCVTPS2DQZ128rm, 0},
{X86::VCVTPS2DQZ256rr, X86::VCVTPS2DQZ256rm, 0},
{X86::VCVTPS2DQZrr, X86::VCVTPS2DQZrm, 0},
{X86::VCVTPS2DQrr, X86::VCVTPS2DQrm, 0},
+ {X86::VCVTPS2HF8SZ128rr, X86::VCVTPS2HF8SZ128rm, 0},
+ {X86::VCVTPS2HF8SZ256rr, X86::VCVTPS2HF8SZ256rm, 0},
+ {X86::VCVTPS2HF8SZrr, X86::VCVTPS2HF8SZrm, 0},
+ {X86::VCVTPS2HF8Z128rr, X86::VCVTPS2HF8Z128rm, 0},
+ {X86::VCVTPS2HF8Z256rr, X86::VCVTPS2HF8Z256rm, 0},
+ {X86::VCVTPS2HF8Zrr, X86::VCVTPS2HF8Zrm, 0},
{X86::VCVTPS2IBSZ128rr, X86::VCVTPS2IBSZ128rm, 0},
{X86::VCVTPS2IBSZ256rr, X86::VCVTPS2IBSZ256rm, 0},
{X86::VCVTPS2IBSZrr, X86::VCVTPS2IBSZrm, 0},
@@ -1310,6 +1339,12 @@ static const X86FoldTableEntry Table1[] = {
{X86::VCVTQQ2PSZ128rr, X86::VCVTQQ2PSZ128rm, 0},
{X86::VCVTQQ2PSZ256rr, X86::VCVTQQ2PSZ256rm, 0},
{X86::VCVTQQ2PSZrr, X86::VCVTQQ2PSZrm, 0},
+ {X86::VCVTROPS2HF8SZ128rr, X86::VCVTROPS2HF8SZ128rm, 0},
+ {X86::VCVTROPS2HF8SZ256rr, X86::VCVTROPS2HF8SZ256rm, 0},
+ {X86::VCVTROPS2HF8SZrr, X86::VCVTROPS2HF8SZrm, 0},
+ {X86::VCVTROPS2HF8Z128rr, X86::VCVTROPS2HF8Z128rm, 0},
+ {X86::VCVTROPS2HF8Z256rr, X86::VCVTROPS2HF8Z256rm, 0},
+ {X86::VCVTROPS2HF8Zrr, X86::VCVTROPS2HF8Zrm, 0},
{X86::VCVTSD2SI64Zrr, X86::VCVTSD2SI64Zrm, 0},
{X86::VCVTSD2SI64Zrr_Int, X86::VCVTSD2SI64Zrm_Int, TB_NO_REVERSE},
{X86::VCVTSD2SI64rr, X86::VCVTSD2SI64rm, 0},
@@ -1963,6 +1998,9 @@ static const X86FoldTableEntry Table1[] = {
{X86::VUCOMXSHZrr_Int, X86::VUCOMXSHZrm_Int, TB_NO_REVERSE},
{X86::VUCOMXSSZrr, X86::VUCOMXSSZrm, 0},
{X86::VUCOMXSSZrr_Int, X86::VUCOMXSSZrm_Int, TB_NO_REVERSE},
+ {X86::VUNPACKBZ128ri, X86::VUNPACKBZ128mi, 0},
+ {X86::VUNPACKBZ256ri, X86::VUNPACKBZ256mi, 0},
+ {X86::VUNPACKBZri, X86::VUNPACKBZmi, 0},
{X86::XOR16ri8_ND, X86::XOR16mi8_ND, 0},
{X86::XOR16ri8_NF_ND, X86::XOR16mi8_NF_ND, 0},
{X86::XOR16ri_ND, X86::XOR16mi_ND, 0},
@@ -2563,6 +2601,12 @@ static const X86FoldTableEntry Table2[] = {
{X86::VCVTBF162IUBSZ128rrkz, X86::VCVTBF162IUBSZ128rmkz, 0},
{X86::VCVTBF162IUBSZ256rrkz, X86::VCVTBF162IUBSZ256rmkz, 0},
{X86::VCVTBF162IUBSZrrkz, X86::VCVTBF162IUBSZrmkz, 0},
+ {X86::VCVTBF42HF8Z128rrkz, X86::VCVTBF42HF8Z128rmkz, TB_NO_REVERSE},
+ {X86::VCVTBF42HF8Z256rrkz, X86::VCVTBF42HF8Z256rmkz, 0},
+ {X86::VCVTBF42HF8Zrrkz, X86::VCVTBF42HF8Zrmkz, 0},
+ {X86::VCVTBF82PSZ128rrkz, X86::VCVTBF82PSZ128rmkz, TB_NO_REVERSE},
+ {X86::VCVTBF82PSZ256rrkz, X86::VCVTBF82PSZ256rmkz, TB_NO_REVERSE},
+ {X86::VCVTBF82PSZrrkz, X86::VCVTBF82PSZrmkz, 0},
{X86::VCVTBIASPH2BF8SZ128rr, X86::VCVTBIASPH2BF8SZ128rm, 0},
{X86::VCVTBIASPH2BF8SZ256rr, X86::VCVTBIASPH2BF8SZ256rm, 0},
{X86::VCVTBIASPH2BF8SZrr, X86::VCVTBIASPH2BF8SZrm, 0},
@@ -2575,6 +2619,18 @@ static const X86FoldTableEntry Table2[] = {
{X86::VCVTBIASPH2HF8Z128rr, X86::VCVTBIASPH2HF8Z128rm, 0},
{X86::VCVTBIASPH2HF8Z256rr, X86::VCVTBIASPH2HF8Z256rm, 0},
{X86::VCVTBIASPH2HF8Zrr, X86::VCVTBIASPH2HF8Zrm, 0},
+ {X86::VCVTBIASPS2BF8SZ128rr, X86::VCVTBIASPS2BF8SZ128rm, 0},
+ {X86::VCVTBIASPS2BF8SZ256rr, X86::VCVTBIASPS2BF8SZ256rm, 0},
+ {X86::VCVTBIASPS2BF8SZrr, X86::VCVTBIASPS2BF8SZrm, 0},
+ {X86::VCVTBIASPS2BF8Z128rr, X86::VCVTBIASPS2BF8Z128rm, 0},
+ {X86::VCVTBIASPS2BF8Z256rr, X86::VCVTBIASPS2BF8Z256rm, 0},
+ {X86::VCVTBIASPS2BF8Zrr, X86::VCVTBIASPS2BF8Zrm, 0},
+ {X86::VCVTBIASPS2HF8SZ128rr, X86::VCVTBIASPS2HF8SZ128rm, 0},
+ {X86::VCVTBIASPS2HF8SZ256rr, X86::VCVTBIASPS2HF8SZ256rm, 0},
+ {X86::VCVTBIASPS2HF8SZrr, X86::VCVTBIASPS2HF8SZrm, 0},
+ {X86::VCVTBIASPS2HF8Z128rr, X86::VCVTBIASPS2HF8Z128rm, 0},
+ {X86::VCVTBIASPS2HF8Z256rr, X86::VCVTBIASPS2HF8Z256rm, 0},
+ {X86::VCVTBIASPS2HF8Zrr, X86::VCVTBIASPS2HF8Zrm, 0},
{X86::VCVTDQ2PDZ128rrkz, X86::VCVTDQ2PDZ128rmkz, TB_NO_REVERSE},
{X86::VCVTDQ2PDZ256rrkz, X86::VCVTDQ2PDZ256rmkz, 0},
{X86::VCVTDQ2PDZrrkz, X86::VCVTDQ2PDZrmkz, 0},
@@ -2587,6 +2643,9 @@ static const X86FoldTableEntry Table2[] = {
{X86::VCVTHF82PHZ128rrkz, X86::VCVTHF82PHZ128rmkz, TB_NO_REVERSE},
{X86::VCVTHF82PHZ256rrkz, X86::VCVTHF82PHZ256rmkz, 0},
{X86::VCVTHF82PHZrrkz, X86::VCVTHF82PHZrmkz, 0},
+ {X86::VCVTHF82PSZ128rrkz, X86::VCVTHF82PSZ128rmkz, TB_NO_REVERSE},
+ {X86::VCVTHF82PSZ256rrkz, X86::VCVTHF82PSZ256rmkz, TB_NO_REVERSE},
+ {X86::VCVTHF82PSZrrkz, X86::VCVTHF82PSZrmkz, 0},
{X86::VCVTNE2PS2BF16Z128rr, X86::VCVTNE2PS2BF16Z128rm, 0},
{X86::VCVTNE2PS2BF16Z256rr, X86::VCVTNE2PS2BF16Z256rm, 0},
{X86::VCVTNE2PS2BF16Zrr, X86::VCVTNE2PS2BF16Zrm, 0},
@@ -2656,9 +2715,21 @@ static const X86FoldTableEntry Table2[] = {
{X86::VCVTPH2WZ128rrkz, X86::VCVTPH2WZ128rmkz, 0},
{X86::VCVTPH2WZ256rrkz, X86::VCVTPH2WZ256rmkz, 0},
{X86::VCVTPH2WZrrkz, X86::VCVTPH2WZrmkz, 0},
+ {X86::VCVTPS2BF8SZ128rrkz, X86::VCVTPS2BF8SZ128rmkz, 0},
+ {X86::VCVTPS2BF8SZ256rrkz, X86::VCVTPS2BF8SZ256rmkz, 0},
+ {X86::VCVTPS2BF8SZrrkz, X86::VCVTPS2BF8SZrmkz, 0},
+ {X86::VCVTPS2BF8Z128rrkz, X86::VCVTPS2BF8Z128rmkz, 0},
+ {X86::VCVTPS2BF8Z256rrkz, X86::VCVTPS2BF8Z256rmkz, 0},
+ {X86::VCVTPS2BF8Zrrkz, X86::VCVTPS2BF8Zrmkz, 0},
{X86::VCVTPS2DQZ128rrkz, X86::VCVTPS2DQZ128rmkz, 0},
{X86::VCVTPS2DQZ256rrkz, X86::VCVTPS2DQZ256rmkz, 0},
{X86::VCVTPS2DQZrrkz, X86::VCVTPS2DQZrmkz, 0},
+ {X86::VCVTPS2HF8SZ128rrkz, X86::VCVTPS2HF8SZ128rmkz, 0},
+ {X86::VCVTPS2HF8SZ256rrkz, X86::VCVTPS2HF8SZ256rmkz, 0},
+ {X86::VCVTPS2HF8SZrrkz, X86::VCVTPS2HF8SZrmkz, 0},
+ {X86::VCVTPS2HF8Z128rrkz, X86::VCVTPS2HF8Z128rmkz, 0},
+ {X86::VCVTPS2HF8Z256rrkz, X86::VCVTPS2HF8Z256rmkz, 0},
+ {X86::VCVTPS2HF8Zrrkz, X86::VCVTPS2HF8Zrmkz, 0},
{X86::VCVTPS2IBSZ128rrkz, X86::VCVTPS2IBSZ128rmkz, 0},
{X86::VCVTPS2IBSZ256rrkz, X86::VCVTPS2IBSZ256rmkz, 0},
{X86::VCVTPS2IBSZrrkz, X86::VCVTPS2IBSZrmkz, 0},
@@ -2689,6 +2760,12 @@ static const X86FoldTableEntry Table2[] = {
{X86::VCVTQQ2PSZ128rrkz, X86::VCVTQQ2PSZ128rmkz, 0},
{X86::VCVTQQ2PSZ256rrkz, X86::VCVTQQ2PSZ256rmkz, 0},
{X86::VCVTQQ2PSZrrkz, X86::VCVTQQ2PSZrmkz, 0},
+ {X86::VCVTROPS2HF8SZ128rrkz, X86::VCVTROPS2HF8SZ128rmkz, 0},
+ {X86::VCVTROPS2HF8SZ256rrkz, X86::VCVTROPS2HF8SZ256rmkz, 0},
+ {X86::VCVTROPS2HF8SZrrkz, X86::VCVTROPS2HF8SZrmkz, 0},
+ {X86::VCVTROPS2HF8Z128rrkz, X86::VCVTROPS2HF8Z128rmkz, 0},
+ {X86::VCVTROPS2HF8Z256rrkz, X86::VCVTROPS2HF8Z256rmkz, 0},
+ {X86::VCVTROPS2HF8Zrrkz, X86::VCVTROPS2HF8Zrmkz, 0},
{X86::VCVTSD2SHZrr, X86::VCVTSD2SHZrm, 0},
{X86::VCVTSD2SHZrr_Int, X86::VCVTSD2SHZrm_Int, TB_NO_REVERSE},
{X86::VCVTSD2SSZrr, X86::VCVTSD2SSZrm, 0},
@@ -4180,6 +4257,9 @@ static const X86FoldTableEntry Table2[] = {
{X86::VSUBSSZrr_Int, X86::VSUBSSZrm_Int, TB_NO_REVERSE},
{X86::VSUBSSrr, X86::VSUBSSrm, 0},
{X86::VSUBSSrr_Int, X86::VSUBSSrm_Int, TB_NO_REVERSE},
+ {X86::VUNPACKBZ128rikz, X86::VUNPACKBZ128mikz, 0},
+ {X86::VUNPACKBZ256rikz, X86::VUNPACKBZ256mikz, 0},
+ {X86::VUNPACKBZrikz, X86::VUNPACKBZmikz, 0},
{X86::VUNPCKHPDYrr, X86::VUNPCKHPDYrm, 0},
{X86::VUNPCKHPDZ128rr, X86::VUNPCKHPDZ128rm, 0},
{X86::VUNPCKHPDZ256rr, X86::VUNPCKHPDZ256rm, 0},
@@ -4316,6 +4396,12 @@ static const X86FoldTableEntry Table3[] = {
{X86::VCVTBF162IUBSZ128rrk, X86::VCVTBF162IUBSZ128rmk, 0},
{X86::VCVTBF162IUBSZ256rrk, X86::VCVTBF162IUBSZ256rmk, 0},
{X86::VCVTBF162IUBSZrrk, X86::VCVTBF162IUBSZrmk, 0},
+ {X86::VCVTBF42HF8Z128rrk, X86::VCVTBF42HF8Z128rmk, TB_NO_REVERSE},
+ {X86::VCVTBF42HF8Z256rrk, X86::VCVTBF42HF8Z256rmk, 0},
+ {X86::VCVTBF42HF8Zrrk, X86::VCVTBF42HF8Zrmk, 0},
+ {X86::VCVTBF82PSZ128rrk, X86::VCVTBF82PSZ128rmk, TB_NO_REVERSE},
+ {X86::VCVTBF82PSZ256rrk, X86::VCVTBF82PSZ256rmk, TB_NO_REVERSE},
+ {X86::VCVTBF82PSZrrk, X86::VCVTBF82PSZrmk, 0},
{X86::VCVTBIASPH2BF8SZ128rrkz, X86::VCVTBIASPH2BF8SZ128rmkz, 0},
{X86::VCVTBIASPH2BF8SZ256rrkz, X86::VCVTBIASPH2BF8SZ256rmkz, 0},
{X86::VCVTBIASPH2BF8SZrrkz, X86::VCVTBIASPH2BF8SZrmkz, 0},
@@ -4328,6 +4414,18 @@ static const X86FoldTableEntry Table3[] = {
{X86::VCVTBIASPH2HF8Z128rrkz, X86::VCVTBIASPH2HF8Z128rmkz, 0},
{X86::VCVTBIASPH2HF8Z256rrkz, X86::VCVTBIASPH2HF8Z256rmkz, 0},
{X86::VCVTBIASPH2HF8Zrrkz, X86::VCVTBIASPH2HF8Zrmkz, 0},
+ {X86::VCVTBIASPS2BF8SZ128rrkz, X86::VCVTBIASPS2BF8SZ128rmkz, 0},
+ {X86::VCVTBIASPS2BF8SZ256rrkz, X86::VCVTBIASPS2BF8SZ256rmkz, 0},
+ {X86::VCVTBIASPS2BF8SZrrkz, X86::VCVTBIASPS2BF8SZrmkz, 0},
+ {X86::VCVTBIASPS2BF8Z128rrkz, X86::VCVTBIASPS2BF8Z128rmkz, 0},
+ {X86::VCVTBIASPS2BF8Z256rrkz, X86::VCVTBIASPS2BF8Z256rmkz, 0},
+ {X86::VCVTBIASPS2BF8Zrrkz, X86::VCVTBIASPS2BF8Zrmkz, 0},
+ {X86::VCVTBIASPS2HF8SZ128rrkz, X86::VCVTBIASPS2HF8SZ128rmkz, 0},
+ {X86::VCVTBIASPS2HF8SZ256rrkz, X86::VCVTBIASPS2HF8SZ256rmkz, 0},
+ {X86::VCVTBIASPS2HF8SZrrkz, X86::VCVTBIASPS2HF8SZrmkz, 0},
+ {X86::VCVTBIASPS2HF8Z128rrkz, X86::VCVTBIASPS2HF8Z128rmkz, 0},
+ {X86::VCVTBIASPS2HF8Z256rrkz, X86::VCVTBIASPS2HF8Z256rmkz, 0},
+ {X86::VCVTBIASPS2HF8Zrrkz, X86::VCVTBIASPS2HF8Zrmkz, 0},
{X86::VCVTDQ2PDZ128rrk, X86::VCVTDQ2PDZ128rmk, TB_NO_REVERSE},
{X86::VCVTDQ2PDZ256rrk, X86::VCVTDQ2PDZ256rmk, 0},
{X86::VCVTDQ2PDZrrk, X86::VCVTDQ2PDZrmk, 0},
@@ -4340,6 +4438,9 @@ static const X86FoldTableEntry Table3[] = {
{X86::VCVTHF82PHZ128rrk, X86::VCVTHF82PHZ128rmk, TB_NO_REVERSE},
{X86::VCVTHF82PHZ256rrk, X86::VCVTHF82PHZ256rmk, 0},
{X86::VCVTHF82PHZrrk, X86::VCVTHF82PHZrmk, 0},
+ {X86::VCVTHF82PSZ128rrk, X86::VCVTHF82PSZ128rmk, TB_NO_REVERSE},
+ {X86::VCVTHF82PSZ256rrk, X86::VCVTHF82PSZ256rmk, TB_NO_REVERSE},
+ {X86::VCVTHF82PSZrrk, X86::VCVTHF82PSZrmk, 0},
{X86::VCVTNE2PS2BF16Z128rrkz, X86::VCVTNE2PS2BF16Z128rmkz, 0},
{X86::VCVTNE2PS2BF16Z256rrkz, X86::VCVTNE2PS2BF16Z256rmkz, 0},
{X86::VCVTNE2PS2BF16Zrrkz, X86::VCVTNE2PS2BF16Zrmkz, 0},
@@ -4409,9 +4510,21 @@ static const X86FoldTableEntry Table3[] = {
{X86::VCVTPH2WZ128rrk, X86::VCVTPH2WZ128rmk, 0},
{X86::VCVTPH2WZ256rrk, X86::VCVTPH2WZ256rmk, 0},
{X86::VCVTPH2WZrrk, X86::VCVTPH2WZrmk, 0},
+ {X86::VCVTPS2BF8SZ128rrk, X86::VCVTPS2BF8SZ128rmk, 0},
+ {X86::VCVTPS2BF8SZ256rrk, X86::VCVTPS2BF8SZ256rmk, 0},
+ {X86::VCVTPS2BF8SZrrk, X86::VCVTPS2BF8SZrmk, 0},
+ {X86::VCVTPS2BF8Z128rrk, X86::VCVTPS2BF8Z128rmk, 0},
+ {X86::VCVTPS2BF8Z256rrk, X86::VCVTPS2BF8Z256rmk, 0},
+ {X86::VCVTPS2BF8Zrrk, X86::VCVTPS2BF8Zrmk, 0},
{X86::VCVTPS2DQZ128rrk, X86::VCVTPS2DQZ128rmk, 0},
{X86::VCVTPS2DQZ256rrk, X86::VCVTPS2DQZ256rmk, 0},
{X86::VCVTPS2DQZrrk, X86::VCVTPS2DQZrmk, 0},
+ {X86::VCVTPS2HF8SZ128rrk, X86::VCVTPS2HF8SZ128rmk, 0},
+ {X86::VCVTPS2HF8SZ256rrk, X86::VCVTPS2HF8SZ256rmk, 0},
+ {X86::VCVTPS2HF8SZrrk, X86::VCVTPS2HF8SZrmk, 0},
+ {X86::VCVTPS2HF8Z128rrk, X86::VCVTPS2HF8Z128rmk, 0},
+ {X86::VCVTPS2HF8Z256rrk, X86::VCVTPS2HF8Z256rmk, 0},
+ {X86::VCVTPS2HF8Zrrk, X86::VCVTPS2HF8Zrmk, 0},
{X86::VCVTPS2IBSZ128rrk, X86::VCVTPS2IBSZ128rmk, 0},
{X86::VCVTPS2IBSZ256rrk, X86::VCVTPS2IBSZ256rmk, 0},
{X86::VCVTPS2IBSZrrk, X86::VCVTPS2IBSZrmk, 0},
@@ -4442,6 +4555,12 @@ static const X86FoldTableEntry Table3[] = {
{X86::VCVTQQ2PSZ128rrk, X86::VCVTQQ2PSZ128rmk, 0},
{X86::VCVTQQ2PSZ256rrk, X86::VCVTQQ2PSZ256rmk, 0},
{X86::VCVTQQ2PSZrrk, X86::VCVTQQ2PSZrmk, 0},
+ {X86::VCVTROPS2HF8SZ128rrk, X86::VCVTROPS2HF8SZ128rmk, 0},
+ {X86::VCVTROPS2HF8SZ256rrk, X86::VCVTROPS2HF8SZ256rmk, 0},
+ {X86::VCVTROPS2HF8SZrrk, X86::VCVTROPS2HF8SZrmk, 0},
+ {X86::VCVTROPS2HF8Z128rrk, X86::VCVTROPS2HF8Z128rmk, 0},
+ {X86::VCVTROPS2HF8Z256rrk, X86::VCVTROPS2HF8Z256rmk, 0},
+ {X86::VCVTROPS2HF8Zrrk, X86::VCVTROPS2HF8Zrmk, 0},
{X86::VCVTSD2SHZrrkz_Int, X86::VCVTSD2SHZrmkz_Int, TB_NO_REVERSE},
{X86::VCVTSD2SSZrrkz_Int, X86::VCVTSD2SSZrmkz_Int, TB_NO_REVERSE},
{X86::VCVTSH2SDZrrkz_Int, X86::VCVTSH2SDZrmkz_Int, TB_NO_REVERSE},
@@ -6060,6 +6179,9 @@ static const X86FoldTableEntry Table3[] = {
{X86::VSUBSDZrrkz_Int, X86::VSUBSDZrmkz_Int, TB_NO_REVERSE},
{X86::VSUBSHZrrkz_Int, X86::VSUBSHZrmkz_Int, TB_NO_REVERSE},
{X86::VSUBSSZrrkz_Int, X86::VSUBSSZrmkz_Int, TB_NO_REVERSE},
+ {X86::VUNPACKBZ128rik, X86::VUNPACKBZ128mik, 0},
+ {X86::VUNPACKBZ256rik, X86::VUNPACKBZ256mik, 0},
+ {X86::VUNPACKBZrik, X86::VUNPACKBZmik, 0},
{X86::VUNPCKHPDZ128rrkz, X86::VUNPCKHPDZ128rmkz, 0},
{X86::VUNPCKHPDZ256rrkz, X86::VUNPCKHPDZ256rmkz, 0},
{X86::VUNPCKHPDZrrkz, X86::VUNPCKHPDZrmkz, 0},
@@ -6141,6 +6263,18 @@ static const X86FoldTableEntry Table4[] = {
{X86::VCVTBIASPH2HF8Z128rrk, X86::VCVTBIASPH2HF8Z128rmk, 0},
{X86::VCVTBIASPH2HF8Z256rrk, X86::VCVTBIASPH2HF8Z256rmk, 0},
{X86::VCVTBIASPH2HF8Zrrk, X86::VCVTBIASPH2HF8Zrmk, 0},
+ {X86::VCVTBIASPS2BF8SZ128rrk, X86::VCVTBIASPS2BF8SZ128rmk, 0},
+ {X86::VCVTBIASPS2BF8SZ256rrk, X86::VCVTBIASPS2BF8SZ256rmk, 0},
+ {X86::VCVTBIASPS2BF8SZrrk, X86::VCVTBIASPS2BF8SZrmk, 0},
+ {X86::VCVTBIASPS2BF8Z128rrk, X86::VCVTBIASPS2BF8Z128rmk, 0},
+ {X86::VCVTBIASPS2BF8Z256rrk, X86::VCVTBIASPS2BF8Z256rmk, 0},
+ {X86::VCVTBIASPS2BF8Zrrk, X86::VCVTBIASPS2BF8Zrmk, 0},
+ {X86::VCVTBIASPS2HF8SZ128rrk, X86::VCVTBIASPS2HF8SZ128rmk, 0},
+ {X86::VCVTBIASPS2HF8SZ256rrk, X86::VCVTBIASPS2HF8SZ256rmk, 0},
+ {X86::VCVTBIASPS2HF8SZrrk, X86::VCVTBIASPS2HF8SZrmk, 0},
+ {X86::VCVTBIASPS2HF8Z128rrk, X86::VCVTBIASPS2HF8Z128rmk, 0},
+ {X86::VCVTBIASPS2HF8Z256rrk, X86::VCVTBIASPS2HF8Z256rmk, 0},
+ {X86::VCVTBIASPS2HF8Zrrk, X86::VCVTBIASPS2HF8Zrmk, 0},
{X86::VCVTNE2PS2BF16Z128rrk, X86::VCVTNE2PS2BF16Z128rmk, 0},
{X86::VCVTNE2PS2BF16Z256rrk, X86::VCVTNE2PS2BF16Z256rmk, 0},
{X86::VCVTNE2PS2BF16Zrrk, X86::VCVTNE2PS2BF16Zrmk, 0},
@@ -7505,9 +7639,21 @@ static const X86FoldTableEntry BroadcastTable1[] = {
{X86::VCVTPH2WZ128rr, X86::VCVTPH2WZ128rmb, TB_BCAST_SH},
{X86::VCVTPH2WZ256rr, X86::VCVTPH2WZ256rmb, TB_BCAST_SH},
{X86::VCVTPH2WZrr, X86::VCVTPH2WZrmb, TB_BCAST_SH},
+ {X86::VCVTPS2BF8SZ128rr, X86::VCVTPS2BF8SZ128rmb, TB_BCAST_SS},
+ {X86::VCVTPS2BF8SZ256rr, X86::VCVTPS2BF8SZ256rmb, TB_BCAST_SS},
+ {X86::VCVTPS2BF8SZrr, X86::VCVTPS2BF8SZrmb, TB_BCAST_SS},
+ {X86::VCVTPS2BF8Z128rr, X86::VCVTPS2BF8Z128rmb, TB_BCAST_SS},
+ {X86::VCVTPS2BF8Z256rr, X86::VCVTPS2BF8Z256rmb, TB_BCAST_SS},
+ {X86::VCVTPS2BF8Zrr, X86::VCVTPS2BF8Zrmb, TB_BCAST_SS},
{X86::VCVTPS2DQZ128rr, X86::VCVTPS2DQZ128rmb, TB_BCAST_SS},
{X86::VCVTPS2DQZ256rr, X86::VCVTPS2DQZ256rmb, TB_BCAST_SS},
{X86::VCVTPS2DQZrr, X86::VCVTPS2DQZrmb, TB_BCAST_SS},
+ {X86::VCVTPS2HF8SZ128rr, X86::VCVTPS2HF8SZ128rmb, TB_BCAST_SS},
+ {X86::VCVTPS2HF8SZ256rr, X86::VCVTPS2HF8SZ256rmb, TB_BCAST_SS},
+ {X86::VCVTPS2HF8SZrr, X86::VCVTPS2HF8SZrmb, TB_BCAST_SS},
+ {X86::VCVTPS2HF8Z128rr, X86::VCVTPS2HF8Z128rmb, TB_BCAST_SS},
+ {X86::VCVTPS2HF8Z256rr, X86::VCVTPS2HF8Z256rmb, TB_BCAST_SS},
+ {X86::VCVTPS2HF8Zrr, X86::VCVTPS2HF8Zrmb, TB_BCAST_SS},
{X86::VCVTPS2IBSZ128rr, X86::VCVTPS2IBSZ128rmb, TB_BCAST_SS},
{X86::VCVTPS2IBSZ256rr, X86::VCVTPS2IBSZ256rmb, TB_BCAST_SS},
{X86::VCVTPS2IBSZrr, X86::VCVTPS2IBSZrmb, TB_BCAST_SS},
@@ -7538,6 +7684,12 @@ static const X86FoldTableEntry BroadcastTable1[] = {
{X86::VCVTQQ2PSZ128rr, X86::VCVTQQ2PSZ128rmb, TB_BCAST_Q},
{X86::VCVTQQ2PSZ256rr, X86::VCVTQQ2PSZ256rmb, TB_BCAST_Q},
{X86::VCVTQQ2PSZrr, X86::VCVTQQ2PSZrmb, TB_BCAST_Q},
+ {X86::VCVTROPS2HF8SZ128rr, X86::VCVTROPS2HF8SZ128rmb, TB_BCAST_SS},
+ {X86::VCVTROPS2HF8SZ256rr, X86::VCVTROPS2HF8SZ256rmb, TB_BCAST_SS},
+ {X86::VCVTROPS2HF8SZrr, X86::VCVTROPS2HF8SZrmb, TB_BCAST_SS},
+ {X86::VCVTROPS2HF8Z128rr, X86::VCVTROPS2HF8Z128rmb, TB_BCAST_SS},
+ {X86::VCVTROPS2HF8Z256rr, X86::VCVTROPS2HF8Z256rmb, TB_BCAST_SS},
+ {X86::VCVTROPS2HF8Zrr, X86::VCVTROPS2HF8Zrmb, TB_BCAST_SS},
{X86::VCVTTBF162IBSZ128rr, X86::VCVTTBF162IBSZ128rmb, TB_BCAST_SH},
{X86::VCVTTBF162IBSZ256rr, X86::VCVTTBF162IBSZ256rmb, TB_BCAST_SH},
{X86::VCVTTBF162IBSZrr, X86::VCVTTBF162IBSZrmb, TB_BCAST_SH},
@@ -7899,6 +8051,18 @@ static const X86FoldTableEntry BroadcastTable2[] = {
{X86::VCVTBIASPH2HF8Z128rr, X86::VCVTBIASPH2HF8Z128rmb, TB_BCAST_SH},
{X86::VCVTBIASPH2HF8Z256rr, X86::VCVTBIASPH2HF8Z256rmb, TB_BCAST_SH},
{X86::VCVTBIASPH2HF8Zrr, X86::VCVTBIASPH2HF8Zrmb, TB_BCAST_SH},
+ {X86::VCVTBIASPS2BF8SZ128rr, X86::VCVTBIASPS2BF8SZ128rmb, TB_BCAST_SS},
+ {X86::VCVTBIASPS2BF8SZ256rr, X86::VCVTBIASPS2BF8SZ256rmb, TB_BCAST_SS},
+ {X86::VCVTBIASPS2BF8SZrr, X86::VCVTBIASPS2BF8SZrmb, TB_BCAST_SS},
+ {X86::VCVTBIASPS2BF8Z128rr, X86::VCVTBIASPS2BF8Z128rmb, TB_BCAST_SS},
+ {X86::VCVTBIASPS2BF8Z256rr, X86::VCVTBIASPS2BF8Z256rmb, TB_BCAST_SS},
+ {X86::VCVTBIASPS2BF8Zrr, X86::VCVTBIASPS2BF8Zrmb, TB_BCAST_SS},
+ {X86::VCVTBIASPS2HF8SZ128rr, X86::VCVTBIASPS2HF8SZ128rmb, TB_BCAST_SS},
+ {X86::VCVTBIASPS2HF8SZ256rr, X86::VCVTBIASPS2HF8SZ256rmb, TB_BCAST_SS},
+ {X86::VCVTBIASPS2HF8SZrr, X86::VCVTBIASPS2HF8SZrmb, TB_BCAST_SS},
+ {X86::VCVTBIASPS2HF8Z128rr, X86::VCVTBIASPS2HF8Z128rmb, TB_BCAST_SS},
+ {X86::VCVTBIASPS2HF8Z256rr, X86::VCVTBIASPS2HF8Z256rmb, TB_BCAST_SS},
+ {X86::VCVTBIASPS2HF8Zrr, X86::VCVTBIASPS2HF8Zrmb, TB_BCAST_SS},
{X86::VCVTDQ2PDZ128rrkz, X86::VCVTDQ2PDZ128rmbkz, TB_BCAST_D},
{X86::VCVTDQ2PDZ256rrkz, X86::VCVTDQ2PDZ256rmbkz, TB_BCAST_D},
{X86::VCVTDQ2PDZrrkz, X86::VCVTDQ2PDZrmbkz, TB_BCAST_D},
@@ -7974,9 +8138,21 @@ static const X86FoldTableEntry BroadcastTable2[] = {
{X86::VCVTPH2WZ128rrkz, X86::VCVTPH2WZ128rmbkz, TB_BCAST_SH},
{X86::VCVTPH2WZ256rrkz, X86::VCVTPH2WZ256rmbkz, TB_BCAST_SH},
{X86::VCVTPH2WZrrkz, X86::VCVTPH2WZrmbkz, TB_BCAST_SH},
+ {X86::VCVTPS2BF8SZ128rrkz, X86::VCVTPS2BF8SZ128rmbkz, TB_BCAST_SS},
+ {X86::VCVTPS2BF8SZ256rrkz, X86::VCVTPS2BF8SZ256rmbkz, TB_BCAST_SS},
+ {X86::VCVTPS2BF8SZrrkz, X86::VCVTPS2BF8SZrmbkz, TB_BCAST_SS},
+ {X86::VCVTPS2BF8Z128rrkz, X86::VCVTPS2BF8Z128rmbkz, TB_BCAST_SS},
+ {X86::VCVTPS2BF8Z256rrkz, X86::VCVTPS2BF8Z256rmbkz, TB_BCAST_SS},
+ {X86::VCVTPS2BF8Zrrkz, X86::VCVTPS2BF8Zrmbkz, TB_BCAST_SS},
{X86::VCVTPS2DQZ128rrkz, X86::VCVTPS2DQZ128rmbkz, TB_BCAST_SS},
{X86::VCVTPS2DQZ256rrkz, X86::VCVTPS2DQZ256rmbkz, TB_BCAST_SS},
{X86::VCVTPS2DQZrrkz, X86::VCVTPS2DQZrmbkz, TB_BCAST_SS},
+ {X86::VCVTPS2HF8SZ128rrkz, X86::VCVTPS2HF8SZ128rmbkz, TB_BCAST_SS},
+ {X86::VCVTPS2HF8SZ256rrkz, X86::VCVTPS2HF8SZ256rmbkz, TB_BCAST_SS},
+ {X86::VCVTPS2HF8SZrrkz, X86::VCVTPS2HF8SZrmbkz, TB_BCAST_SS},
+ {X86::VCVTPS2HF8Z128rrkz, X86::VCVTPS2HF8Z128rmbkz, TB_BCAST_SS},
+ {X86::VCVTPS2HF8Z256rrkz, X86::VCVTPS2HF8Z256rmbkz, TB_BCAST_SS},
+ {X86::VCVTPS2HF8Zrrkz, X86::VCVTPS2HF8Zrmbkz, TB_BCAST_SS},
{X86::VCVTPS2IBSZ128rrkz, X86::VCVTPS2IBSZ128rmbkz, TB_BCAST_SS},
{X86::VCVTPS2IBSZ256rrkz, X86::VCVTPS2IBSZ256rmbkz, TB_BCAST_SS},
{X86::VCVTPS2IBSZrrkz, X86::VCVTPS2IBSZrmbkz, TB_BCAST_SS},
@@ -8007,6 +8183,12 @@ static const X86FoldTableEntry BroadcastTable2[] = {
{X86::VCVTQQ2PSZ128rrkz, X86::VCVTQQ2PSZ128rmbkz, TB_BCAST_Q},
{X86::VCVTQQ2PSZ256rrkz, X86::VCVTQQ2PSZ256rmbkz, TB_BCAST_Q},
{X86::VCVTQQ2PSZrrkz, X86::VCVTQQ2PSZrmbkz, TB_BCAST_Q},
+ {X86::VCVTROPS2HF8SZ128rrkz, X86::VCVTROPS2HF8SZ128rmbkz, TB_BCAST_SS},
+ {X86::VCVTROPS2HF8SZ256rrkz, X86::VCVTROPS2HF8SZ256rmbkz, TB_BCAST_SS},
+ {X86::VCVTROPS2HF8SZrrkz, X86::VCVTROPS2HF8SZrmbkz, TB_BCAST_SS},
+ {X86::VCVTROPS2HF8Z128rrkz, X86::VCVTROPS2HF8Z128rmbkz, TB_BCAST_SS},
+ {X86::VCVTROPS2HF8Z256rrkz, X86::VCVTROPS2HF8Z256rmbkz, TB_BCAST_SS},
+ {X86::VCVTROPS2HF8Zrrkz, X86::VCVTROPS2HF8Zrmbkz, TB_BCAST_SS},
{X86::VCVTTBF162IBSZ128rrkz, X86::VCVTTBF162IBSZ128rmbkz, TB_BCAST_SH},
{X86::VCVTTBF162IBSZ256rrkz, X86::VCVTTBF162IBSZ256rmbkz, TB_BCAST_SH},
{X86::VCVTTBF162IBSZrrkz, X86::VCVTTBF162IBSZrmbkz, TB_BCAST_SH},
@@ -8723,6 +8905,18 @@ static const X86FoldTableEntry BroadcastTable3[] = {
{X86::VCVTBIASPH2HF8Z128rrkz, X86::VCVTBIASPH2HF8Z128rmbkz, TB_BCAST_SH},
{X86::VCVTBIASPH2HF8Z256rrkz, X86::VCVTBIASPH2HF8Z256rmbkz, TB_BCAST_SH},
{X86::VCVTBIASPH2HF8Zrrkz, X86::VCVTBIASPH2HF8Zrmbkz, TB_BCAST_SH},
+ {X86::VCVTBIASPS2BF8SZ128rrkz, X86::VCVTBIASPS2BF8SZ128rmbkz, TB_BCAST_SS},
+ {X86::VCVTBIASPS2BF8SZ256rrkz, X86::VCVTBIASPS2BF8SZ256rmbkz, TB_BCAST_SS},
+ {X86::VCVTBIASPS2BF8SZrrkz, X86::VCVTBIASPS2BF8SZrmbkz, TB_BCAST_SS},
+ {X86::VCVTBIASPS2BF8Z128rrkz, X86::VCVTBIASPS2BF8Z128rmbkz, TB_BCAST_SS},
+ {X86::VCVTBIASPS2BF8Z256rrkz, X86::VCVTBIASPS2BF8Z256rmbkz, TB_BCAST_SS},
+ {X86::VCVTBIASPS2BF8Zrrkz, X86::VCVTBIASPS2BF8Zrmbkz, TB_BCAST_SS},
+ {X86::VCVTBIASPS2HF8SZ128rrkz, X86::VCVTBIASPS2HF8SZ128rmbkz, TB_BCAST_SS},
+ {X86::VCVTBIASPS2HF8SZ256rrkz, X86::VCVTBIASPS2HF8SZ256rmbkz, TB_BCAST_SS},
+ {X86::VCVTBIASPS2HF8SZrrkz, X86::VCVTBIASPS2HF8SZrmbkz, TB_BCAST_SS},
+ {X86::VCVTBIASPS2HF8Z128rrkz, X86::VCVTBIASPS2HF8Z128rmbkz, TB_BCAST_SS},
+ {X86::VCVTBIASPS2HF8Z256rrkz, X86::VCVTBIASPS2HF8Z256rmbkz, TB_BCAST_SS},
+ {X86::VCVTBIASPS2HF8Zrrkz, X86::VCVTBIASPS2HF8Zrmbkz, TB_BCAST_SS},
{X86::VCVTDQ2PDZ128rrk, X86::VCVTDQ2PDZ128rmbk, TB_BCAST_D},
{X86::VCVTDQ2PDZ256rrk, X86::VCVTDQ2PDZ256rmbk, TB_BCAST_D},
{X86::VCVTDQ2PDZrrk, X86::VCVTDQ2PDZrmbk, TB_BCAST_D},
@@ -8798,9 +8992,21 @@ static const X86FoldTableEntry BroadcastTable3[] = {
{X86::VCVTPH2WZ128rrk, X86::VCVTPH2WZ128rmbk, TB_BCAST_SH},
{X86::VCVTPH2WZ256rrk, X86::VCVTPH2WZ256rmbk, TB_BCAST_SH},
{X86::VCVTPH2WZrrk, X86::VCVTPH2WZrmbk, TB_BCAST_SH},
+ {X86::VCVTPS2BF8SZ128rrk, X86::VCVTPS2BF8SZ128rmbk, TB_BCAST_SS},
+ {X86::VCVTPS2BF8SZ256rrk, X86::VCVTPS2BF8SZ256rmbk, TB_BCAST_SS},
+ {X86::VCVTPS2BF8SZrrk, X86::VCVTPS2BF8SZrmbk, TB_BCAST_SS},
+ {X86::VCVTPS2BF8Z128rrk, X86::VCVTPS2BF8Z128rmbk, TB_BCAST_SS},
+ {X86::VCVTPS2BF8Z256rrk, X86::VCVTPS2BF8Z256rmbk, TB_BCAST_SS},
+ {X86::VCVTPS2BF8Zrrk, X86::VCVTPS2BF8Zrmbk, TB_BCAST_SS},
{X86::VCVTPS2DQZ128rrk, X86::VCVTPS2DQZ128rmbk, TB_BCAST_SS},
{X86::VCVTPS2DQZ256rrk, X86::VCVTPS2DQZ256rmbk, TB_BCAST_SS},
{X86::VCVTPS2DQZrrk, X86::VCVTPS2DQZrmbk, TB_BCAST_SS},
+ {X86::VCVTPS2HF8SZ128rrk, X86::VCVTPS2HF8SZ128rmbk, TB_BCAST_SS},
+ {X86::VCVTPS2HF8SZ256rrk, X86::VCVTPS2HF8SZ256rmbk, TB_BCAST_SS},
+ {X86::VCVTPS2HF8SZrrk, X86::VCVTPS2HF8SZrmbk, TB_BCAST_SS},
+ {X86::VCVTPS2HF8Z128rrk, X86::VCVTPS2HF8Z128rmbk, TB_BCAST_SS},
+ {X86::VCVTPS2HF8Z256rrk, X86::VCVTPS2HF8Z256rmbk, TB_BCAST_SS},
+ {X86::VCVTPS2HF8Zrrk, X86::VCVTPS2HF8Zrmbk, TB_BCAST_SS},
{X86::VCVTPS2IBSZ128rrk, X86::VCVTPS2IBSZ128rmbk, TB_BCAST_SS},
{X86::VCVTPS2IBSZ256rrk, X86::VCVTPS2IBSZ256rmbk, TB_BCAST_SS},
{X86::VCVTPS2IBSZrrk, X86::VCVTPS2IBSZrmbk, TB_BCAST_SS},
@@ -8831,6 +9037,12 @@ static const X86FoldTableEntry BroadcastTable3[] = {
{X86::VCVTQQ2PSZ128rrk, X86::VCVTQQ2PSZ128rmbk, TB_BCAST_Q},
{X86::VCVTQQ2PSZ256rrk, X86::VCVTQQ2PSZ256rmbk, TB_BCAST_Q},
{X86::VCVTQQ2PSZrrk, X86::VCVTQQ2PSZrmbk, TB_BCAST_Q},
+ {X86::VCVTROPS2HF8SZ128rrk, X86::VCVTROPS2HF8SZ128rmbk, TB_BCAST_SS},
+ {X86::VCVTROPS2HF8SZ256rrk, X86::VCVTROPS2HF8SZ256rmbk, TB_BCAST_SS},
+ {X86::VCVTROPS2HF8SZrrk, X86::VCVTROPS2HF8SZrmbk, TB_BCAST_SS},
+ {X86::VCVTROPS2HF8Z128rrk, X86::VCVTROPS2HF8Z128rmbk, TB_BCAST_SS},
+ {X86::VCVTROPS2HF8Z256rrk, X86::VCVTROPS2HF8Z256rmbk, TB_BCAST_SS},
+ {X86::VCVTROPS2HF8Zrrk, X86::VCVTROPS2HF8Zrmbk, TB_BCAST_SS},
{X86::VCVTTBF162IBSZ128rrk, X86::VCVTTBF162IBSZ128rmbk, TB_BCAST_SH},
{X86::VCVTTBF162IBSZ256rrk, X86::VCVTTBF162IBSZ256rmbk, TB_BCAST_SH},
{X86::VCVTTBF162IBSZrrk, X86::VCVTTBF162IBSZrmbk, TB_BCAST_SH},
@@ -9817,6 +10029,18 @@ static const X86FoldTableEntry BroadcastTable4[] = {
{X86::VCVTBIASPH2HF8Z128rrk, X86::VCVTBIASPH2HF8Z128rmbk, TB_BCAST_SH},
{X86::VCVTBIASPH2HF8Z256rrk, X86::VCVTBIASPH2HF8Z256rmbk, TB_BCAST_SH},
{X86::VCVTBIASPH2HF8Zrrk, X86::VCVTBIASPH2HF8Zrmbk, TB_BCAST_SH},
+ {X86::VCVTBIASPS2BF8SZ128rrk, X86::VCVTBIASPS2BF8SZ128rmbk, TB_BCAST_SS},
+ {X86::VCVTBIASPS2BF8SZ256rrk, X86::VCVTBIASPS2BF8SZ256rmbk, TB_BCAST_SS},
+ {X86::VCVTBIASPS2BF8SZrrk, X86::VCVTBIASPS2BF8SZrmbk, TB_BCAST_SS},
+ {X86::VCVTBIASPS2BF8Z128rrk, X86::VCVTBIASPS2BF8Z128rmbk, TB_BCAST_SS},
+ {X86::VCVTBIASPS2BF8Z256rrk, X86::VCVTBIASPS2BF8Z256rmbk, TB_BCAST_SS},
+ {X86::VCVTBIASPS2BF8Zrrk, X86::VCVTBIASPS2BF8Zrmbk, TB_BCAST_SS},
+ {X86::VCVTBIASPS2HF8SZ128rrk, X86::VCVTBIASPS2HF8SZ128rmbk, TB_BCAST_SS},
+ {X86::VCVTBIASPS2HF8SZ256rrk, X86::VCVTBIASPS2HF8SZ256rmbk, TB_BCAST_SS},
+ {X86::VCVTBIASPS2HF8SZrrk, X86::VCVTBIASPS2HF8SZrmbk, TB_BCAST_SS},
+ {X86::VCVTBIASPS2HF8Z128rrk, X86::VCVTBIASPS2HF8Z128rmbk, TB_BCAST_SS},
+ {X86::VCVTBIASPS2HF8Z256rrk, X86::VCVTBIASPS2HF8Z256rmbk, TB_BCAST_SS},
+ {X86::VCVTBIASPS2HF8Zrrk, X86::VCVTBIASPS2HF8Zrmbk, TB_BCAST_SS},
{X86::VCVTNE2PS2BF16Z128rrk, X86::VCVTNE2PS2BF16Z128rmbk, TB_BCAST_SS},
{X86::VCVTNE2PS2BF16Z256rrk, X86::VCVTNE2PS2BF16Z256rmbk, TB_BCAST_SS},
{X86::VCVTNE2PS2BF16Zrrk, X86::VCVTNE2PS2BF16Zrmbk, TB_BCAST_SS},
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