[clang] [llvm] [X86] AVX10_V2_AUX Implementation (PR #206888)
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Tue Jun 30 21:48:28 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-x86
Author: Ganesh (ganeshgit)
<details>
<summary>Changes</summary>
- AVX10_V2_AUX extends AVX10.2 with FP8/FP4/FP6 format conversions optimized for AI/ML inference workloads, enabling efficient low-precision arithmetic
- Narrowing conversions from single-precision to FP8: VCVTPS2BF8, VCVTPS2HF8, VCVTPS2BF8S, VCVTPS2HF8S with optional saturation, biasing (VCVTBIASPS2BF8/HF8), and round-to-odd (VCVTROPS2HF8) variants
- Expanding conversions from FP8 to single-precision: VCVTBF82PS, VCVTHF82PS that widen 8-bit FP formats with masking support
- FP4/FP6 conversions: VCVTBF82BF4S, VCVTHF82BF4S for truncating, VCVTBF82BF6S, VCVTHF82HF6S for same-size, and expanding VCVTBF42HF8, VCVTBF62BF8, VCVTHF62HF8
- Support includes instruction definitions, intrinsics, and Clang headers
- Tests covering AT&T and Intel syntax assembly for both 32-bit and 64-bit modes, plus disassembler tests verifying encoding and decoding
Specification: [ACE (AI Compute Extensions) Specification v1.0](https://x86ecosystem.org/wp-content/uploads/2026/06/ACE_v1_Specification_public_1_15.pdf)
Co-authored-by: Umesh Kalvakuntla
---
Patch is 367.15 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/206888.diff
26 Files Affected:
- (modified) clang/include/clang/Basic/BuiltinsX86.td (+247)
- (modified) clang/lib/Basic/Targets/X86.cpp (+6)
- (modified) clang/lib/Basic/Targets/X86.h (+1)
- (modified) clang/lib/Headers/CMakeLists.txt (+1)
- (added) clang/lib/Headers/avx10_2_v2auxintrin.h (+1067)
- (modified) clang/lib/Headers/cpuid.h (+3)
- (modified) clang/lib/Headers/immintrin.h (+4)
- (added) clang/test/CodeGen/X86/avx10_2_v2aux-builtins.c (+1056)
- (modified) clang/test/CodeGen/attr-target-x86.c (+2-2)
- (modified) llvm/include/llvm/IR/IntrinsicsX86.td (+197)
- (modified) llvm/include/llvm/TargetParser/X86TargetParser.def (+1)
- (modified) llvm/lib/Target/X86/X86.td (+3)
- (added) llvm/lib/Target/X86/X86InstrAVX10_V2_AUX.td (+588)
- (modified) llvm/lib/Target/X86/X86InstrFragmentsSIMD.td (+57)
- (modified) llvm/lib/Target/X86/X86InstrInfo.td (+3)
- (modified) llvm/lib/Target/X86/X86InstrPredicates.td (+1)
- (modified) llvm/lib/Target/X86/X86IntrinsicsInfo.h (+72)
- (modified) llvm/lib/TargetParser/X86TargetParser.cpp (+1)
- (added) llvm/test/CodeGen/X86/avx10_2_v2aux-intrinsics.ll (+1931)
- (added) llvm/test/MC/Disassembler/X86/avx10_v2_aux-32.txt (+460)
- (added) llvm/test/MC/Disassembler/X86/avx10_v2_aux-64.txt (+460)
- (added) llvm/test/MC/X86/avx10_v2_aux-att-32.s (+463)
- (added) llvm/test/MC/X86/avx10_v2_aux-att-64.s (+687)
- (added) llvm/test/MC/X86/avx10_v2_aux-intel-32.s (+331)
- (added) llvm/test/MC/X86/avx10_v2_aux-intel-64.s (+687)
- (modified) llvm/test/TableGen/x86-fold-tables.inc (+220)
``````````diff
diff --git a/clang/include/clang/Basic/BuiltinsX86.td b/clang/include/clang/Basic/BuiltinsX86.td
index b0f95d98b8471..82fd8d80cc82d 100644
--- a/clang/include/clang/Basic/BuiltinsX86.td
+++ b/clang/include/clang/Basic/BuiltinsX86.td
@@ -5045,3 +5045,250 @@ let Features = "avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<256>
let Features = "avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in {
def vgetmantbf16512_mask : X86Builtin<"_Vector<32, __bf16>(_Vector<32, __bf16>, _Constant int, _Vector<32, __bf16>, unsigned int)">;
}
+
+// AVX10 V2 AUX - Convert instructions
+
+// Group A: PS(f32) -> i8 truncating conversions (quarter-size: output always v16i8)
+
+// VCVTPS2BF8
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<128>] in {
+ def vcvtps2bf8_128_mask : X86Builtin<"_Vector<16, char>(_Vector<4, float>, _Vector<16, char>, unsigned char)">;
+}
+
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<256>] in {
+ def vcvtps2bf8_256_mask : X86Builtin<"_Vector<16, char>(_Vector<8, float>, _Vector<16, char>, unsigned char)">;
+}
+
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<512>] in {
+ def vcvtps2bf8_512_mask : X86Builtin<"_Vector<16, char>(_Vector<16, float>, _Vector<16, char>, unsigned short)">;
+}
+
+// VCVTPS2BF8S
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<128>] in {
+ def vcvtps2bf8s_128_mask : X86Builtin<"_Vector<16, char>(_Vector<4, float>, _Vector<16, char>, unsigned char)">;
+}
+
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<256>] in {
+ def vcvtps2bf8s_256_mask : X86Builtin<"_Vector<16, char>(_Vector<8, float>, _Vector<16, char>, unsigned char)">;
+}
+
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<512>] in {
+ def vcvtps2bf8s_512_mask : X86Builtin<"_Vector<16, char>(_Vector<16, float>, _Vector<16, char>, unsigned short)">;
+}
+
+// VCVTPS2HF8
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<128>] in {
+ def vcvtps2hf8_128_mask : X86Builtin<"_Vector<16, char>(_Vector<4, float>, _Vector<16, char>, unsigned char)">;
+}
+
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<256>] in {
+ def vcvtps2hf8_256_mask : X86Builtin<"_Vector<16, char>(_Vector<8, float>, _Vector<16, char>, unsigned char)">;
+}
+
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<512>] in {
+ def vcvtps2hf8_512_mask : X86Builtin<"_Vector<16, char>(_Vector<16, float>, _Vector<16, char>, unsigned short)">;
+}
+
+// VCVTPS2HF8S
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<128>] in {
+ def vcvtps2hf8s_128_mask : X86Builtin<"_Vector<16, char>(_Vector<4, float>, _Vector<16, char>, unsigned char)">;
+}
+
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<256>] in {
+ def vcvtps2hf8s_256_mask : X86Builtin<"_Vector<16, char>(_Vector<8, float>, _Vector<16, char>, unsigned char)">;
+}
+
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<512>] in {
+ def vcvtps2hf8s_512_mask : X86Builtin<"_Vector<16, char>(_Vector<16, float>, _Vector<16, char>, unsigned short)">;
+}
+
+// VCVTROPS2HF8
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<128>] in {
+ def vcvtrops2hf8_128_mask : X86Builtin<"_Vector<16, char>(_Vector<4, float>, _Vector<16, char>, unsigned char)">;
+}
+
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<256>] in {
+ def vcvtrops2hf8_256_mask : X86Builtin<"_Vector<16, char>(_Vector<8, float>, _Vector<16, char>, unsigned char)">;
+}
+
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<512>] in {
+ def vcvtrops2hf8_512_mask : X86Builtin<"_Vector<16, char>(_Vector<16, float>, _Vector<16, char>, unsigned short)">;
+}
+
+// VCVTROPS2HF8S
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<128>] in {
+ def vcvtrops2hf8s_128_mask : X86Builtin<"_Vector<16, char>(_Vector<4, float>, _Vector<16, char>, unsigned char)">;
+}
+
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<256>] in {
+ def vcvtrops2hf8s_256_mask : X86Builtin<"_Vector<16, char>(_Vector<8, float>, _Vector<16, char>, unsigned char)">;
+}
+
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<512>] in {
+ def vcvtrops2hf8s_512_mask : X86Builtin<"_Vector<16, char>(_Vector<16, float>, _Vector<16, char>, unsigned short)">;
+}
+
+// Group B: Bias PS -> i8 conversions (3-operand: bias + f32 source -> i8 dest)
+
+// VCVTBIASPS2BF8
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<128>] in {
+ def vcvtbiasps2bf8_128_mask : X86Builtin<"_Vector<16, char>(_Vector<16, char>, _Vector<4, float>, _Vector<16, char>, unsigned char)">;
+}
+
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<256>] in {
+ def vcvtbiasps2bf8_256_mask : X86Builtin<"_Vector<16, char>(_Vector<32, char>, _Vector<8, float>, _Vector<16, char>, unsigned char)">;
+}
+
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<512>] in {
+ def vcvtbiasps2bf8_512_mask : X86Builtin<"_Vector<16, char>(_Vector<64, char>, _Vector<16, float>, _Vector<16, char>, unsigned short)">;
+}
+
+// VCVTBIASPS2BF8S
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<128>] in {
+ def vcvtbiasps2bf8s_128_mask : X86Builtin<"_Vector<16, char>(_Vector<16, char>, _Vector<4, float>, _Vector<16, char>, unsigned char)">;
+}
+
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<256>] in {
+ def vcvtbiasps2bf8s_256_mask : X86Builtin<"_Vector<16, char>(_Vector<32, char>, _Vector<8, float>, _Vector<16, char>, unsigned char)">;
+}
+
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<512>] in {
+ def vcvtbiasps2bf8s_512_mask : X86Builtin<"_Vector<16, char>(_Vector<64, char>, _Vector<16, float>, _Vector<16, char>, unsigned short)">;
+}
+
+// VCVTBIASPS2HF8
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<128>] in {
+ def vcvtbiasps2hf8_128_mask : X86Builtin<"_Vector<16, char>(_Vector<16, char>, _Vector<4, float>, _Vector<16, char>, unsigned char)">;
+}
+
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<256>] in {
+ def vcvtbiasps2hf8_256_mask : X86Builtin<"_Vector<16, char>(_Vector<32, char>, _Vector<8, float>, _Vector<16, char>, unsigned char)">;
+}
+
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<512>] in {
+ def vcvtbiasps2hf8_512_mask : X86Builtin<"_Vector<16, char>(_Vector<64, char>, _Vector<16, float>, _Vector<16, char>, unsigned short)">;
+}
+
+// VCVTBIASPS2HF8S
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<128>] in {
+ def vcvtbiasps2hf8s_128_mask : X86Builtin<"_Vector<16, char>(_Vector<16, char>, _Vector<4, float>, _Vector<16, char>, unsigned char)">;
+}
+
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<256>] in {
+ def vcvtbiasps2hf8s_256_mask : X86Builtin<"_Vector<16, char>(_Vector<32, char>, _Vector<8, float>, _Vector<16, char>, unsigned char)">;
+}
+
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<512>] in {
+ def vcvtbiasps2hf8s_512_mask : X86Builtin<"_Vector<16, char>(_Vector<64, char>, _Vector<16, float>, _Vector<16, char>, unsigned short)">;
+}
+
+// Group C: 8bit -> PS expanding conversions
+
+// VCVTBF82PS
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<128>] in {
+ def vcvtbf8_2ps128_mask : X86Builtin<"_Vector<4, float>(_Vector<16, char>, _Vector<4, float>, unsigned char)">;
+}
+
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<256>] in {
+ def vcvtbf8_2ps256_mask : X86Builtin<"_Vector<8, float>(_Vector<16, char>, _Vector<8, float>, unsigned char)">;
+}
+
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<512>] in {
+ def vcvtbf8_2ps512_mask : X86Builtin<"_Vector<16, float>(_Vector<16, char>, _Vector<16, float>, unsigned short)">;
+}
+
+// VCVTHF82PS
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<128>] in {
+ def vcvthf8_2ps128_mask : X86Builtin<"_Vector<4, float>(_Vector<16, char>, _Vector<4, float>, unsigned char)">;
+}
+
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<256>] in {
+ def vcvthf8_2ps256_mask : X86Builtin<"_Vector<8, float>(_Vector<16, char>, _Vector<8, float>, unsigned char)">;
+}
+
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<512>] in {
+ def vcvthf8_2ps512_mask : X86Builtin<"_Vector<16, float>(_Vector<16, char>, _Vector<16, float>, unsigned short)">;
+}
+
+// Group E: Same-size reg-only conversions (no masking)
+
+// VCVTBF82BF6S
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<128>] in {
+ def vcvtbf82bf6s128 : X86Builtin<"_Vector<16, char>(_Vector<16, char>)">;
+}
+
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<256>] in {
+ def vcvtbf82bf6s256 : X86Builtin<"_Vector<32, char>(_Vector<32, char>)">;
+}
+
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<512>] in {
+ def vcvtbf82bf6s512 : X86Builtin<"_Vector<64, char>(_Vector<64, char>)">;
+}
+
+// VCVTHF82HF6S
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<128>] in {
+ def vcvthf82hf6s128 : X86Builtin<"_Vector<16, char>(_Vector<16, char>)">;
+}
+
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<256>] in {
+ def vcvthf82hf6s256 : X86Builtin<"_Vector<32, char>(_Vector<32, char>)">;
+}
+
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<512>] in {
+ def vcvthf82hf6s512 : X86Builtin<"_Vector<64, char>(_Vector<64, char>)">;
+}
+
+// Group F: Expanding/same-size conversions (no masking in intrinsic; use selectb for masking)
+
+// VCVTBF42HF8
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<128>] in {
+ def vcvtbf42hf8128 : X86Builtin<"_Vector<16, char>(_Vector<16, char>)">;
+}
+
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<256>] in {
+ def vcvtbf42hf8256 : X86Builtin<"_Vector<32, char>(_Vector<16, char>)">;
+}
+
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<512>] in {
+ def vcvtbf42hf8512 : X86Builtin<"_Vector<64, char>(_Vector<32, char>)">;
+}
+
+// VCVTBF62HF8
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<128>] in {
+ def vcvtbf62hf8128 : X86Builtin<"_Vector<16, char>(_Vector<16, char>)">;
+}
+
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<256>] in {
+ def vcvtbf62hf8256 : X86Builtin<"_Vector<32, char>(_Vector<32, char>)">;
+}
+
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<512>] in {
+ def vcvtbf62hf8512 : X86Builtin<"_Vector<64, char>(_Vector<64, char>)">;
+}
+
+// VCVTHF62HF8
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<128>] in {
+ def vcvthf62hf8128 : X86Builtin<"_Vector<16, char>(_Vector<16, char>)">;
+}
+
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<256>] in {
+ def vcvthf62hf8256 : X86Builtin<"_Vector<32, char>(_Vector<32, char>)">;
+}
+
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<512>] in {
+ def vcvthf62hf8512 : X86Builtin<"_Vector<64, char>(_Vector<64, char>)">;
+}
+
+// Group H: VUNPACKB - Byte unpack with immediate (no masking in intrinsic)
+
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<128>] in {
+ def vunpackb128 : X86Builtin<"_Vector<16, char>(_Vector<16, char>, _Constant unsigned char)">;
+}
+
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<256>] in {
+ def vunpackb256 : X86Builtin<"_Vector<32, char>(_Vector<32, char>, _Constant unsigned char)">;
+}
+
+let Features = "avx10-v2-aux", Attributes = [NoThrow, RequiredVectorWidth<512>] in {
+ def vunpackb512 : X86Builtin<"_Vector<64, char>(_Vector<64, char>, _Constant unsigned char)">;
+}
diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index 2943604f8c8ff..9482e179dee5c 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -281,6 +281,8 @@ bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
} else if (Feature == "+avx10.2") {
HasAVX10_2 = true;
HasFullBFloat16 = true;
+ } else if (Feature == "+avx10-v2-aux") {
+ HasAVX10_V2_AUX = true;
} else if (Feature == "+avx512cd") {
HasAVX512CD = true;
} else if (Feature == "+avx512vpopcntdq") {
@@ -836,6 +838,8 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
Builder.defineMacro("__AVX10_2__");
Builder.defineMacro("__AVX10_2_512__");
}
+ if (HasAVX10_V2_AUX)
+ Builder.defineMacro("__AVX10_V2_AUX__");
if (HasAVX512CD)
Builder.defineMacro("__AVX512CD__");
if (HasAVX512VPOPCNTDQ)
@@ -1087,6 +1091,7 @@ bool X86TargetInfo::isValidFeatureName(StringRef Name) const {
.Case("avx", true)
.Case("avx10.1", true)
.Case("avx10.2", true)
+ .Case("avx10-v2-aux", true)
.Case("avx2", true)
.Case("avx512f", true)
.Case("avx512cd", true)
@@ -1208,6 +1213,7 @@ bool X86TargetInfo::hasFeature(StringRef Feature) const {
.Case("avx", SSELevel >= AVX)
.Case("avx10.1", HasAVX10_1)
.Case("avx10.2", HasAVX10_2)
+ .Case("avx10-v2-aux", HasAVX10_V2_AUX)
.Case("avx2", SSELevel >= AVX2)
.Case("avx512f", SSELevel >= AVX512F)
.Case("avx512cd", HasAVX512CD)
diff --git a/clang/lib/Basic/Targets/X86.h b/clang/lib/Basic/Targets/X86.h
index f9c39b31f5e08..02f7e8c5807ca 100644
--- a/clang/lib/Basic/Targets/X86.h
+++ b/clang/lib/Basic/Targets/X86.h
@@ -98,6 +98,7 @@ class LLVM_LIBRARY_VISIBILITY X86TargetInfo : public TargetInfo {
bool HasF16C = false;
bool HasAVX10_1 = false;
bool HasAVX10_2 = false;
+ bool HasAVX10_V2_AUX = false;
bool HasAVX512CD = false;
bool HasAVX512VPOPCNTDQ = false;
bool HasAVX512VNNI = false;
diff --git a/clang/lib/Headers/CMakeLists.txt b/clang/lib/Headers/CMakeLists.txt
index 439f2725168ba..b4891961a4598 100644
--- a/clang/lib/Headers/CMakeLists.txt
+++ b/clang/lib/Headers/CMakeLists.txt
@@ -183,6 +183,7 @@ set(x86_files
avx10_2_512niintrin.h
avx10_2_512satcvtdsintrin.h
avx10_2_512satcvtintrin.h
+ avx10_2_v2auxintrin.h
avx10_2bf16intrin.h
avx10_2convertintrin.h
avx10_2copyintrin.h
diff --git a/clang/lib/Headers/avx10_2_v2auxintrin.h b/clang/lib/Headers/avx10_2_v2auxintrin.h
new file mode 100644
index 0000000000000..5e54085c104c5
--- /dev/null
+++ b/clang/lib/Headers/avx10_2_v2auxintrin.h
@@ -0,0 +1,1067 @@
+/*===------------ avx10_2_v2auxintrin.h - AVX10_2_V2AUX -------------------===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ *
+ *===-----------------------------------------------------------------------===
+ */
+#ifndef __IMMINTRIN_H
+#error \
+ "Never use <avx10_2_v2auxintrin.h> directly; include <immintrin.h> instead."
+#endif // __IMMINTRIN_H
+
+#ifdef __SSE2__
+
+#ifndef __AVX10_2_V2AUXINTRIN_H
+#define __AVX10_2_V2AUXINTRIN_H
+
+/* Define the default attributes for the functions in this file. */
+#define __DEFAULT_FN_ATTRS128 \
+ __attribute__((__always_inline__, __nodebug__, __target__("avx10-v2-aux"), \
+ __min_vector_width__(128)))
+#define __DEFAULT_FN_ATTRS256 \
+ __attribute__((__always_inline__, __nodebug__, __target__("avx10-v2-aux"), \
+ __min_vector_width__(256)))
+#define __DEFAULT_FN_ATTRS512 \
+ __attribute__((__always_inline__, __nodebug__, __target__("avx10-v2-aux"), \
+ __min_vector_width__(512)))
+
+// clang-format off
+
+//===----------------------------------------------------------------------===//
+// Group A: VCVTPS2BF8 / VCVTPS2BF8S / VCVTPS2HF8 / VCVTPS2HF8S /
+// VCVTROPS2HF8 / VCVTROPS2HF8S
+// Convert packed single-precision to FP8. Output is always __m128i.
+//===----------------------------------------------------------------------===//
+
+// VCVTPS2BF8 - 128-bit
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS128
+_mm_cvtps_bf8(__m128 __A) {
+ return (__m128i)__builtin_ia32_vcvtps2bf8_128_mask(
+ (__v4sf)__A, (__v16qi)_mm_undefined_si128(), (__mmask8)-1);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS128
+_mm_mask_cvtps_bf8(__m128i __W, __mmask8 __U, __m128 __A) {
+ return (__m128i)__builtin_ia32_vcvtps2bf8_128_mask(
+ (__v4sf)__A, (__v16qi)(__m128i)__W, (__mmask8)__U);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS128
+_mm_maskz_cvtps_bf8(__mmask8 __U, __m128 __A) {
+ return (__m128i)__builtin_ia32_vcvtps2bf8_128_mask(
+ (__v4sf)__A, (__v16qi)(__m128i)_mm_setzero_si128(), (__mmask8)__U);
+}
+
+// VCVTPS2BF8 - 256-bit
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS256
+_mm256_cvtps_bf8(__m256 __A) {
+ return (__m128i)__builtin_ia32_vcvtps2bf8_256_mask(
+ (__v8sf)__A, (__v16qi)_mm_undefined_si128(), (__mmask8)-1);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS256
+_mm256_mask_cvtps_bf8(__m128i __W, __mmask8 __U, __m256 __A) {
+ return (__m128i)__builtin_ia32_vcvtps2bf8_256_mask(
+ (__v8sf)__A, (__v16qi)(__m128i)__W, (__mmask8)__U);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS256
+_mm256_maskz_cvtps_bf8(__mmask8 __U, __m256 __A) {
+ return (__m128i)__builtin_ia32_vcvtps2bf8_256_mask(
+ (__v8sf)__A, (__v16qi)(__m128i)_mm_setzero_si128(), (__mmask8)__U);
+}
+
+// VCVTPS2BF8 - 512-bit
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS512
+_mm512_cvtps_bf8(__m512 __A) {
+ return (__m128i)__builtin_ia32_vcvtps2bf8_512_mask(
+ (__v16sf)__A, (__v16qi)_mm_undefined_si128(), (__mmask16)-1);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS512
+_mm512_mask_cvtps_bf8(__m128i __W, __mmask16 __U, __m512 __A) {
+ return (__m128i)__builtin_ia32_vcvtps2bf8_512_mask(
+ (__v16sf)__A, (__v16qi)(__m128i)__W, (__mmask16)__U);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS512
+_mm512_maskz_cvtps_bf8(__mmask16 __U, __m512 __A) {
+ return (__m128i)__builtin_ia32_vcvtps2bf8_512_mask(
+ (__v16sf)__A, (__v16qi)(__m128i)_mm_setzero_si128(), (__mmask16)__U);
+}
+
+// VCVTPS2BF8S - 128-bit
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS128
+_mm_cvts_ps_bf8(__m128 __A) {
+ return (__m128i)__builtin_ia32_vcvtps2bf8s_128_mask(
+ (__v4sf)__A, (__v16qi)_mm_undefined_si128(), (__mmask8)-1);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS128
+_mm_mask_cvts_ps_bf8(__m128i __W, __mmask8 __U, __m128 __A) {
+ return (__m128i)__builtin_ia32_vcvtps2bf8s_128_mask(
+ (__v4sf)__A, (__v16qi)(__m128i)__W, (__mmask8)__U);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS128
+_mm_maskz_cvts_ps_bf8(__mmask8 __U, __m128 __A) {
+ return (__m128i)__builtin_ia32_vcvtps2bf8s_128_mask(
+ (__v4sf)__A, (__v16qi)(__m128i)_mm_setzero_si128(), (__mmask8)__U);
+}
+
+// VCVTPS2BF8S - 256-bit
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS256
+_mm256_cvts_ps_bf8(__m256 __A) {
+ return (__m128i)__builtin_ia32_vcvtps2bf8s_256_mask(
+ (__v8sf)__A, (__v16qi)_mm_undefined_si128(), (__mmask8)-1);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS256
+_mm256_mask_cvts_ps_bf8(__m128i __W, __mmask8 __U, __m256 __A) {
+ return (__m128i)__builtin_ia32_vcvtps2bf8s_256_mask(
+ (__v8sf)__A, (__v16qi)(__m128i)__W, (__mmask8)__U);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS256
+_mm256_maskz_cvts_ps_bf8(__mmask8 __U, __m256 __A) {
+ return (__m128i)__builtin_ia32_vcvtps2bf8s_256_mask(
+ (__v8sf)__A, (__v16qi)(__m128i)_mm_setzero_si128(), (__mmask8)__U);
+}
+
+// VCVTPS2BF8S - 512-bit
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS512
+_mm512_cvts_ps_bf8(__m512 __A) {
+ return (__m128i)__builtin_ia32_vcvtps2bf8s_512_mask(
+ (__v16sf)__A, (__v16qi)_mm_undefined_si128(), (__mmask16)-1);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS512
+_mm512_mask_cvts_ps_bf8(__m128i __W, __mmask...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/206888
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