[clang] [CIR][AArch64] Upstream narrowing-addition NEON builtins (PR #204989)

[Andrzej Warzyński via cfe-commits]

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@@ -1191,12 +1191,17 @@ Value *CodeGenFunction::EmitCommonNeonBuiltinExpr(
     return Builder.CreateBitCast(Ops[0], Ty);
   }
   case NEON::BI__builtin_neon_vaddhn_v: {
+    // SrcTy has double-width elements (e.g. <8 x i16> when VTy is <8 x i8>).
     llvm::FixedVectorType *SrcTy =
         llvm::FixedVectorType::getExtendedElementVectorType(VTy);
 
-    // %sum = add <4 x i32> %lhs, %rhs
+    // Example: vaddhn_s16(int16x8_t, int16x8_t)
+    // Ops are <16 x i8>, SrcTy is <8 x i16> -> mismatch
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banach-space wrote:

What you did matches one of the options that I had in mind - great minds think alike 😂 Neat!

https://github.com/llvm/llvm-project/pull/204989