[clang] [llvm] [AArch64][clang][llvm] Add ACLE Armv9.7 lookup table intrinsics (PR #187046)

[via cfe-commits]

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@@ -6037,6 +6066,16 @@ void AArch64DAGToDAGISel::Select(SDNode *Node) {
                AArch64::SRSHL_VG4_4ZZ_S, AArch64::SRSHL_VG4_4ZZ_D}))
         SelectDestructiveMultiIntrinsic(Node, 4, false, Op);
       return;
+    case Intrinsic::aarch64_sme_luti6_lane_x4:
+      if (auto Opc = SelectOpcodeFromVT<SelectTypeKind::AnyType>(
+              Node->getValueType(0), {0, AArch64::LUTI6_4Z2Z2ZI, 0}))
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CarolineConcatto wrote:

I think If we only have one instructions we dont need this if.
It could be only : SelectMultiVectorLuti6LaneX4(Node, AArch64::LUTI6_4Z2Z2ZI , 2);
Same comments for  Intrinsic::aarch64_sme_luti6_lane_x4_x3
SelectMultiVectorLuti6LaneX4(Node, AArch64::LUTI6_4Z2Z3ZI, 2)

https://github.com/llvm/llvm-project/pull/187046