[clang] [llvm] [AArch64][clang][llvm] Add ACLE Armv9.7 lookup table intrinsics (PR #187046)

[via cfe-commits]

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@@ -3978,14 +3983,21 @@ class sme2_luti6_vector_vg4_base<RegisterOperand zd_ty, string asm>
 }
 
 class sme2_luti6_vector_vg4_consecutive<string asm>
-  : sme2_luti6_vector_vg4_base<ZZZZ_h_mul_r, asm> {
+  : sme2_luti6_vector_vg4_base<ZZZZ_h_mul_r, ZZ_Any, asm> {
+  let Inst{15-10} = 0b111101;
+  let Inst{4-2}   = Zd;
+  let Inst{1-0}   = 0b00;
+}
+
+class sme2_luti6_vector_vg4_consecutive_x3<string asm>
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CarolineConcatto wrote:

We could join this as only one class and let ZZZ_Any or ZZ_Any be a parameter.

https://github.com/llvm/llvm-project/pull/187046