[clang] [llvm] [AMDGPU] Add async variants of tensor load/store LDS intrinsics. (PR #200775)

[Sameer Sahasrabuddhe via cfe-commits]

ssahasra wrote:

> @RyanRio That has the downside of breaking the "you can usually read the instruction name off of the intrinsic name" tendency for intrinsics that definitively correspond to some hardware instruction

This "convention" that intrinsics should correspond to instructions is severely outdated. It is from a time when all we did was expose ISA to LLVM IR. We have moved beyond that, where we use intrinsics to represent semantics rather than instructions. Added to that, it's long known that ISA constructs themselves often don't mean what they spell. These intrinsics are tracked by asyncmarks, and they *must* have ".async" in their names. I am strongly opposed to any use of that legacy convention on that.

https://github.com/llvm/llvm-project/pull/200775