[clang] [llvm] [RISCV] Add partial support for -fzero-call-used-regs (PR #194883)

[Craig Topper via cfe-commits]

================
@@ -3935,6 +3939,22 @@ MachineBasicBlock::iterator RISCVInstrInfo::insertOutlinedCall(
   return It;
 }
 
+void RISCVInstrInfo::buildClearRegister(Register Reg, MachineBasicBlock &MBB,
+                                        MachineBasicBlock::iterator Iter,
+                                        DebugLoc &DL,
+                                        bool AllowSideEffects) const {
+
+  const MachineFunction &MF = *MBB.getParent();
+  const RISCVSubtarget &STI = MF.getSubtarget<RISCVSubtarget>();
+  const RISCVRegisterInfo &TRI = *STI.getRegisterInfo();
+
+  if (TRI.isGeneralPurposeRegister(MF, Reg)) {
+    BuildMI(MBB, Iter, DL, get(RISCV::PseudoLI), Reg).addImm(0);
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topperc wrote:

> I don't understand how, but I think it is used. ADDI rd, x0, 1 are turned into li rd, 1.

It prints as `li` but it can't encode to binary. If you test with -filetype=obj I think it will fail.

https://github.com/llvm/llvm-project/pull/194883