[clang] [llvm] [AArch64][clang][llvm] Add support for Armv9.7-A lookup table intrinsics (PR #187046)

[Kerry McLaughlin via cfe-commits]

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@@ -2224,6 +2229,33 @@ void AArch64DAGToDAGISel::SelectFrintFromVT(SDNode *N, unsigned NumVecs,
   SelectUnaryMultiIntrinsic(N, NumVecs, true, Opcode);
 }
 
+void AArch64DAGToDAGISel::EmitMultiVectorLutiLane(SDNode *Node,
+                                                  unsigned NumOutVecs,
+                                                  unsigned Opc,
+                                                  ArrayRef<SDValue> Ops) {
+  SDLoc DL(Node);
+  EVT VT = Node->getValueType(0);
+  bool HasChain = Node->getOpcode() == ISD::INTRINSIC_W_CHAIN;
+
+  SmallVector<SDValue, 4> MachineOps(Ops);
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kmclaughlin-arm wrote:

Sorry, what I meant in my previous review was that the Chain can be added to `Ops` before calling `EmitMultiVectorLutiLane`. That way you don't need to create a new vector here and can just use `Ops` directly.

https://github.com/llvm/llvm-project/pull/187046