[clang] [CIR][AArch64] Upstream Neon vget_lane/vgetq_lane builtins (PR #186119)

[Ayush Kumar Gaur via cfe-commits]

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@@ -0,0 +1,302 @@
+// REQUIRES: aarch64-registered-target || arm-registered-target
+
+// RUN:                   %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -flax-vector-conversions=none           -emit-llvm -o - %s | opt -S -passes=mem2reg,sroa | FileCheck %s --check-prefixes=LLVM
+// RUN: %if cir-enabled %{%clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -flax-vector-conversions=none -fclangir -emit-llvm -o - %s | opt -S -passes=mem2reg,sroa | FileCheck %s --check-prefixes=LLVM %}
+// RUN: %if cir-enabled %{%clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -flax-vector-conversions=none -fclangir -emit-cir  -o - %s |                               FileCheck %s --check-prefixes=CIR %}
+
+//=============================================================================
+// NOTES
+//
+// This file contains tests that were originally located in
+//  * clang/test/CodeGen/AArch64/neon-vget.c
+//  * clang/test/CodeGen/AArch64/poly64.c
+// The main difference is the use of RUN lines that enable ClangIR lowering;
+// therefore only builtins currently supported by ClangIR are tested here.
+//
+// The half-precision extract variants are intentionally omitted here because
+// they lower through the vduph_* builtin IDs, which are still unsupported in
+// CIR for this patch.
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Ayush3941 wrote:

nvm that comment it was my mistake I got confused because I did not see explicit f16 vget handling in CIRGenBuiltinAArch64.cpp and I incorrectly assumed those cases were going through vduph_* fixed that part

https://github.com/llvm/llvm-project/pull/186119