[clang] [CIR][AArch64] Upstream Neon vget_lane/vgetq_lane builtins (PR #186119)
Ayush Kumar Gaur via cfe-commits
cfe-commits at lists.llvm.org
Fri Mar 20 07:05:11 PDT 2026
https://github.com/Ayush3941 updated https://github.com/llvm/llvm-project/pull/186119
>From 2745d339bc2eec3d3dc9a548d2cf70c49cd9215f Mon Sep 17 00:00:00 2001
From: Ayush3941 <ayushkgaur1 at gmail.com>
Date: Thu, 12 Mar 2026 09:31:43 -0400
Subject: [PATCH 1/5] [CIR][AArch64] Upstream Neon vget_lane/vgetq_lane
builtins
---
.../lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp | 82 +++++
clang/test/CodeGen/AArch64/neon/neon-vget.c | 302 ++++++++++++++++++
2 files changed, 384 insertions(+)
create mode 100644 clang/test/CodeGen/AArch64/neon/neon-vget.c
diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
index 5534e69b5f8bc..107271893844d 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
@@ -2724,33 +2724,115 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr,
case NEON::BI__builtin_neon_vset_lane_mf8:
case NEON::BI__builtin_neon_vsetq_lane_mf8:
case NEON::BI__builtin_neon_vsetq_lane_f64:
+ cgm.errorNYI(expr->getSourceRange(),
+ std::string("unimplemented AArch64 builtin call: ") +
+ getContext().BuiltinInfo.getName(builtinID));
+ return mlir::Value{};
+
case NEON::BI__builtin_neon_vget_lane_i8:
+ ops[0] = builder.createBitcast(ops[0], cir::VectorType::get(uInt8Ty, 8));
+ return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()), ops[0],
+ emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vdupb_lane_i8:
+ cgm.errorNYI(expr->getSourceRange(),
+ std::string("unimplemented AArch64 builtin call: ") +
+ getContext().BuiltinInfo.getName(builtinID));
+ return mlir::Value{};
+
case NEON::BI__builtin_neon_vgetq_lane_i8:
+ ops[0] = builder.createBitcast(ops[0], cir::VectorType::get(uInt8Ty, 16));
+ return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()), ops[0],
+ emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vdupb_laneq_i8:
+ cgm.errorNYI(expr->getSourceRange(),
+ std::string("unimplemented AArch64 builtin call: ") +
+ getContext().BuiltinInfo.getName(builtinID));
+ return mlir::Value{};
case NEON::BI__builtin_neon_vget_lane_mf8:
case NEON::BI__builtin_neon_vdupb_lane_mf8:
case NEON::BI__builtin_neon_vgetq_lane_mf8:
case NEON::BI__builtin_neon_vdupb_laneq_mf8:
+ cgm.errorNYI(expr->getSourceRange(),
+ std::string("unimplemented AArch64 builtin call: ") +
+ getContext().BuiltinInfo.getName(builtinID));
+ return mlir::Value{};
case NEON::BI__builtin_neon_vget_lane_i16:
+ ops[0] = builder.createBitcast(ops[0], cir::VectorType::get(uInt16Ty, 4));
+ return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()), ops[0],
+ emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vduph_lane_i16:
+ cgm.errorNYI(expr->getSourceRange(),
+ std::string("unimplemented AArch64 builtin call: ") +
+ getContext().BuiltinInfo.getName(builtinID));
+ return mlir::Value{};
case NEON::BI__builtin_neon_vgetq_lane_i16:
+ ops[0] = builder.createBitcast(ops[0], cir::VectorType::get(uInt16Ty, 8));
+ return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()), ops[0],
+ emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vduph_laneq_i16:
+ cgm.errorNYI(expr->getSourceRange(),
+ std::string("unimplemented AArch64 builtin call: ") +
+ getContext().BuiltinInfo.getName(builtinID));
+ return mlir::Value{};
case NEON::BI__builtin_neon_vget_lane_i32:
+ ops[0] = builder.createBitcast(ops[0], cir::VectorType::get(uInt32Ty, 2));
+ return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()), ops[0],
+ emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vdups_lane_i32:
case NEON::BI__builtin_neon_vdups_lane_f32:
+ cgm.errorNYI(expr->getSourceRange(),
+ std::string("unimplemented AArch64 builtin call: ") +
+ getContext().BuiltinInfo.getName(builtinID));
+ return mlir::Value{};
case NEON::BI__builtin_neon_vgetq_lane_i32:
+ ops[0] = builder.createBitcast(ops[0], cir::VectorType::get(uInt32Ty, 4));
+ return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()), ops[0],
+ emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vdups_laneq_i32:
+ cgm.errorNYI(expr->getSourceRange(),
+ std::string("unimplemented AArch64 builtin call: ") +
+ getContext().BuiltinInfo.getName(builtinID));
+ return mlir::Value{};
case NEON::BI__builtin_neon_vget_lane_i64:
+ ops[0] = builder.createBitcast(ops[0], cir::VectorType::get(uInt64Ty, 1));
+ return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()), ops[0],
+ emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vdupd_lane_i64:
case NEON::BI__builtin_neon_vdupd_lane_f64:
+ cgm.errorNYI(expr->getSourceRange(),
+ std::string("unimplemented AArch64 builtin call: ") +
+ getContext().BuiltinInfo.getName(builtinID));
+ return mlir::Value{};
case NEON::BI__builtin_neon_vgetq_lane_i64:
+ ops[0] = builder.createBitcast(ops[0], cir::VectorType::get(uInt64Ty, 2));
+ return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()), ops[0],
+ emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vdupd_laneq_i64:
+ cgm.errorNYI(expr->getSourceRange(),
+ std::string("unimplemented AArch64 builtin call: ") +
+ getContext().BuiltinInfo.getName(builtinID));
+ return mlir::Value{};
case NEON::BI__builtin_neon_vget_lane_f32:
+ ops[0] = builder.createBitcast(ops[0], cir::VectorType::get(floatTy, 2));
+ return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()), ops[0],
+ emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vget_lane_f64:
+ ops[0] = builder.createBitcast(ops[0], cir::VectorType::get(doubleTy, 1));
+ return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()), ops[0],
+ emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vgetq_lane_f32:
+ ops[0] = builder.createBitcast(ops[0], cir::VectorType::get(floatTy, 4));
+ return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()), ops[0],
+ emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vdups_laneq_f32:
+ cgm.errorNYI(expr->getSourceRange(),
+ std::string("unimplemented AArch64 builtin call: ") +
+ getContext().BuiltinInfo.getName(builtinID));
+ return mlir::Value{};
case NEON::BI__builtin_neon_vgetq_lane_f64:
+ ops[0] = builder.createBitcast(ops[0], cir::VectorType::get(doubleTy, 2));
+ return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()), ops[0],
+ emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vdupd_laneq_f64:
case NEON::BI__builtin_neon_vaddh_f16:
case NEON::BI__builtin_neon_vsubh_f16:
diff --git a/clang/test/CodeGen/AArch64/neon/neon-vget.c b/clang/test/CodeGen/AArch64/neon/neon-vget.c
new file mode 100644
index 0000000000000..297a07ced2f41
--- /dev/null
+++ b/clang/test/CodeGen/AArch64/neon/neon-vget.c
@@ -0,0 +1,302 @@
+// REQUIRES: aarch64-registered-target || arm-registered-target
+
+// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -flax-vector-conversions=none -emit-llvm -o - %s | opt -S -passes=mem2reg,sroa | FileCheck %s --check-prefixes=LLVM
+// RUN: %if cir-enabled %{%clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -flax-vector-conversions=none -fclangir -emit-llvm -o - %s | opt -S -passes=mem2reg,sroa | FileCheck %s --check-prefixes=LLVM %}
+// RUN: %if cir-enabled %{%clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -flax-vector-conversions=none -fclangir -emit-cir -o - %s | FileCheck %s --check-prefixes=CIR %}
+
+//=============================================================================
+// NOTES
+//
+// This file contains tests that were originally located in
+// * clang/test/CodeGen/AArch64/neon-vget.c
+// * clang/test/CodeGen/AArch64/poly64.c
+// The main difference is the use of RUN lines that enable ClangIR lowering;
+// therefore only builtins currently supported by ClangIR are tested here.
+//
+// The half-precision extract variants are intentionally omitted here because
+// they lower through the vduph_* builtin IDs, which are still unsupported in
+// CIR for this patch.
+//
+//=============================================================================
+
+#include <arm_neon.h>
+
+//===------------------------------------------------------===//
+// Extract one element from vector
+//===------------------------------------------------------===//
+
+// LLVM-LABEL: @test_vget_lane_u8(
+// CIR-LABEL: @test_vget_lane_u8(
+uint8_t test_vget_lane_u8(uint8x8_t a) {
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : {{.*}}] : !cir.vector<8 x !u8i>
+
+// LLVM: [[VGET_LANE:%.*]] = extractelement <8 x i8> %{{.*}}, i32 7
+// LLVM: ret i8 [[VGET_LANE]]
+ return vget_lane_u8(a, 7);
+}
+
+// LLVM-LABEL: @test_vget_lane_u16(
+// CIR-LABEL: @test_vget_lane_u16(
+uint16_t test_vget_lane_u16(uint16x4_t a) {
+// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<4 x !u16i>
+// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<4 x !u16i>
+
+// LLVM: [[VGET_LANE:%.*]] = extractelement <4 x i16> %{{.*}}, i32 3
+// LLVM: ret i16 [[VGET_LANE]]
+ return vget_lane_u16(a, 3);
+}
+
+// LLVM-LABEL: @test_vget_lane_u32(
+// CIR-LABEL: @test_vget_lane_u32(
+uint32_t test_vget_lane_u32(uint32x2_t a) {
+// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<2 x !u32i>
+// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<2 x !u32i>
+
+// LLVM: [[VGET_LANE:%.*]] = extractelement <2 x i32> %{{.*}}, i32 1
+// LLVM: ret i32 [[VGET_LANE]]
+ return vget_lane_u32(a, 1);
+}
+
+// LLVM-LABEL: @test_vget_lane_s8(
+// CIR-LABEL: @test_vget_lane_s8(
+int8_t test_vget_lane_s8(int8x8_t a) {
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : {{.*}}] : !cir.vector<8 x !u8i>
+
+// LLVM: [[VGET_LANE:%.*]] = extractelement <8 x i8> %{{.*}}, i32 7
+// LLVM: ret i8 [[VGET_LANE]]
+ return vget_lane_s8(a, 7);
+}
+
+// LLVM-LABEL: @test_vget_lane_s16(
+// CIR-LABEL: @test_vget_lane_s16(
+int16_t test_vget_lane_s16(int16x4_t a) {
+// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<4 x !u16i>
+// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<4 x !u16i>
+
+// LLVM: [[VGET_LANE:%.*]] = extractelement <4 x i16> %{{.*}}, i32 3
+// LLVM: ret i16 [[VGET_LANE]]
+ return vget_lane_s16(a, 3);
+}
+
+// LLVM-LABEL: @test_vget_lane_s32(
+// CIR-LABEL: @test_vget_lane_s32(
+int32_t test_vget_lane_s32(int32x2_t a) {
+// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<2 x !u32i>
+// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<2 x !u32i>
+
+// LLVM: [[VGET_LANE:%.*]] = extractelement <2 x i32> %{{.*}}, i32 1
+// LLVM: ret i32 [[VGET_LANE]]
+ return vget_lane_s32(a, 1);
+}
+
+// LLVM-LABEL: @test_vget_lane_p8(
+// CIR-LABEL: @test_vget_lane_p8(
+poly8_t test_vget_lane_p8(poly8x8_t a) {
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : {{.*}}] : !cir.vector<8 x !u8i>
+
+// LLVM: [[VGET_LANE:%.*]] = extractelement <8 x i8> %{{.*}}, i32 7
+// LLVM: ret i8 [[VGET_LANE]]
+ return vget_lane_p8(a, 7);
+}
+
+// LLVM-LABEL: @test_vget_lane_p16(
+// CIR-LABEL: @test_vget_lane_p16(
+poly16_t test_vget_lane_p16(poly16x4_t a) {
+// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<4 x !u16i>
+// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<4 x !u16i>
+
+// LLVM: [[VGET_LANE:%.*]] = extractelement <4 x i16> %{{.*}}, i32 3
+// LLVM: ret i16 [[VGET_LANE]]
+ return vget_lane_p16(a, 3);
+}
+
+// LLVM-LABEL: @test_vget_lane_f32(
+// CIR-LABEL: @test_vget_lane_f32(
+float32_t test_vget_lane_f32(float32x2_t a) {
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : {{.*}}] : !cir.vector<2 x !cir.float>
+
+// LLVM: [[VGET_LANE:%.*]] = extractelement <2 x float> %{{.*}}, i32 1
+// LLVM: ret float [[VGET_LANE]]
+ return vget_lane_f32(a, 1);
+}
+
+// LLVM-LABEL: @test_vget_lane_f64(
+// CIR-LABEL: @test_vget_lane_f64(
+float64_t test_vget_lane_f64(float64x1_t a) {
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : {{.*}}] : !cir.vector<1 x !cir.double>
+
+// LLVM: [[VGET_LANE:%.*]] = extractelement <1 x double> %{{.*}}, i32 0
+// LLVM: ret double [[VGET_LANE]]
+ return vget_lane_f64(a, 0);
+}
+
+// LLVM-LABEL: @test_vgetq_lane_u8(
+// CIR-LABEL: @test_vgetq_lane_u8(
+uint8_t test_vgetq_lane_u8(uint8x16_t a) {
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : {{.*}}] : !cir.vector<16 x !u8i>
+
+// LLVM: [[VGETQ_LANE:%.*]] = extractelement <16 x i8> %{{.*}}, i32 15
+// LLVM: ret i8 [[VGETQ_LANE]]
+ return vgetq_lane_u8(a, 15);
+}
+
+// LLVM-LABEL: @test_vgetq_lane_u16(
+// CIR-LABEL: @test_vgetq_lane_u16(
+uint16_t test_vgetq_lane_u16(uint16x8_t a) {
+// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<8 x !u16i>
+// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<8 x !u16i>
+
+// LLVM: [[VGETQ_LANE:%.*]] = extractelement <8 x i16> %{{.*}}, i32 7
+// LLVM: ret i16 [[VGETQ_LANE]]
+ return vgetq_lane_u16(a, 7);
+}
+
+// LLVM-LABEL: @test_vgetq_lane_u32(
+// CIR-LABEL: @test_vgetq_lane_u32(
+uint32_t test_vgetq_lane_u32(uint32x4_t a) {
+// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<4 x !u32i>
+// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<4 x !u32i>
+
+// LLVM: [[VGETQ_LANE:%.*]] = extractelement <4 x i32> %{{.*}}, i32 3
+// LLVM: ret i32 [[VGETQ_LANE]]
+ return vgetq_lane_u32(a, 3);
+}
+
+// LLVM-LABEL: @test_vgetq_lane_s8(
+// CIR-LABEL: @test_vgetq_lane_s8(
+int8_t test_vgetq_lane_s8(int8x16_t a) {
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : {{.*}}] : !cir.vector<16 x !u8i>
+
+// LLVM: [[VGETQ_LANE:%.*]] = extractelement <16 x i8> %{{.*}}, i32 15
+// LLVM: ret i8 [[VGETQ_LANE]]
+ return vgetq_lane_s8(a, 15);
+}
+
+// LLVM-LABEL: @test_vgetq_lane_s16(
+// CIR-LABEL: @test_vgetq_lane_s16(
+int16_t test_vgetq_lane_s16(int16x8_t a) {
+// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<8 x !u16i>
+// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<8 x !u16i>
+
+// LLVM: [[VGETQ_LANE:%.*]] = extractelement <8 x i16> %{{.*}}, i32 7
+// LLVM: ret i16 [[VGETQ_LANE]]
+ return vgetq_lane_s16(a, 7);
+}
+
+// LLVM-LABEL: @test_vgetq_lane_s32(
+// CIR-LABEL: @test_vgetq_lane_s32(
+int32_t test_vgetq_lane_s32(int32x4_t a) {
+// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<4 x !u32i>
+// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<4 x !u32i>
+
+// LLVM: [[VGETQ_LANE:%.*]] = extractelement <4 x i32> %{{.*}}, i32 3
+// LLVM: ret i32 [[VGETQ_LANE]]
+ return vgetq_lane_s32(a, 3);
+}
+
+// LLVM-LABEL: @test_vgetq_lane_p8(
+// CIR-LABEL: @test_vgetq_lane_p8(
+poly8_t test_vgetq_lane_p8(poly8x16_t a) {
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : {{.*}}] : !cir.vector<16 x !u8i>
+
+// LLVM: [[VGETQ_LANE:%.*]] = extractelement <16 x i8> %{{.*}}, i32 15
+// LLVM: ret i8 [[VGETQ_LANE]]
+ return vgetq_lane_p8(a, 15);
+}
+
+// LLVM-LABEL: @test_vgetq_lane_p16(
+// CIR-LABEL: @test_vgetq_lane_p16(
+poly16_t test_vgetq_lane_p16(poly16x8_t a) {
+// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<8 x !u16i>
+// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<8 x !u16i>
+
+// LLVM: [[VGETQ_LANE:%.*]] = extractelement <8 x i16> %{{.*}}, i32 7
+// LLVM: ret i16 [[VGETQ_LANE]]
+ return vgetq_lane_p16(a, 7);
+}
+
+// LLVM-LABEL: @test_vgetq_lane_f32(
+// CIR-LABEL: @test_vgetq_lane_f32(
+float32_t test_vgetq_lane_f32(float32x4_t a) {
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : {{.*}}] : !cir.vector<4 x !cir.float>
+
+// LLVM: [[VGETQ_LANE:%.*]] = extractelement <4 x float> %{{.*}}, i32 3
+// LLVM: ret float [[VGETQ_LANE]]
+ return vgetq_lane_f32(a, 3);
+}
+
+// LLVM-LABEL: @test_vgetq_lane_f64(
+// CIR-LABEL: @test_vgetq_lane_f64(
+float64_t test_vgetq_lane_f64(float64x2_t a) {
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : {{.*}}] : !cir.vector<2 x !cir.double>
+
+// LLVM: [[VGETQ_LANE:%.*]] = extractelement <2 x double> %{{.*}}, i32 1
+// LLVM: ret double [[VGETQ_LANE]]
+ return vgetq_lane_f64(a, 1);
+}
+
+// LLVM-LABEL: @test_vget_lane_s64(
+// CIR-LABEL: @test_vget_lane_s64(
+int64_t test_vget_lane_s64(int64x1_t a) {
+// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<1 x !u64i>
+// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<1 x !u64i>
+
+// LLVM: [[VGET_LANE:%.*]] = extractelement <1 x i64> %{{.*}}, i32 0
+// LLVM: ret i64 [[VGET_LANE]]
+ return vget_lane_s64(a, 0);
+}
+
+// LLVM-LABEL: @test_vget_lane_u64(
+// CIR-LABEL: @test_vget_lane_u64(
+uint64_t test_vget_lane_u64(uint64x1_t a) {
+// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<1 x !u64i>
+// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<1 x !u64i>
+
+// LLVM: [[VGET_LANE:%.*]] = extractelement <1 x i64> %{{.*}}, i32 0
+// LLVM: ret i64 [[VGET_LANE]]
+ return vget_lane_u64(a, 0);
+}
+
+// LLVM-LABEL: @test_vget_lane_p64(
+// CIR-LABEL: @test_vget_lane_p64(
+poly64_t test_vget_lane_p64(poly64x1_t v) {
+// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<1 x !u64i>
+// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<1 x !u64i>
+
+// LLVM: [[VGET_LANE:%.*]] = extractelement <1 x i64> %{{.*}}, i32 0
+// LLVM: ret i64 [[VGET_LANE]]
+ return vget_lane_p64(v, 0);
+}
+
+// LLVM-LABEL: @test_vgetq_lane_s64(
+// CIR-LABEL: @test_vgetq_lane_s64(
+int64_t test_vgetq_lane_s64(int64x2_t a) {
+// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<2 x !u64i>
+// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<2 x !u64i>
+
+// LLVM: [[VGETQ_LANE:%.*]] = extractelement <2 x i64> %{{.*}}, i32 1
+// LLVM: ret i64 [[VGETQ_LANE]]
+ return vgetq_lane_s64(a, 1);
+}
+
+// LLVM-LABEL: @test_vgetq_lane_u64(
+// CIR-LABEL: @test_vgetq_lane_u64(
+uint64_t test_vgetq_lane_u64(uint64x2_t a) {
+// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<2 x !u64i>
+// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<2 x !u64i>
+
+// LLVM: [[VGETQ_LANE:%.*]] = extractelement <2 x i64> %{{.*}}, i32 1
+// LLVM: ret i64 [[VGETQ_LANE]]
+ return vgetq_lane_u64(a, 1);
+}
+
+// LLVM-LABEL: @test_vgetq_lane_p64(
+// CIR-LABEL: @test_vgetq_lane_p64(
+poly64_t test_vgetq_lane_p64(poly64x2_t v) {
+// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<2 x !u64i>
+// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<2 x !u64i>
+
+// LLVM: [[VGETQ_LANE:%.*]] = extractelement <2 x i64> %{{.*}}, i32 1
+// LLVM: ret i64 [[VGETQ_LANE]]
+ return vgetq_lane_p64(v, 1);
+}
>From 42e2e3e20b7921fb7d79c6fea2522314e0ffd3d7 Mon Sep 17 00:00:00 2001
From: Ayush3941 <ayushkgaur1 at gmail.com>
Date: Thu, 12 Mar 2026 09:45:55 -0400
Subject: [PATCH 2/5] [CIR][AArch64] Upstream Neon vget_lane/vgetq_lane
builtins v2
---
clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp | 4 ----
1 file changed, 4 deletions(-)
diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
index 107271893844d..275bf56411d87 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
@@ -2744,10 +2744,6 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr,
return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()), ops[0],
emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vdupb_laneq_i8:
- cgm.errorNYI(expr->getSourceRange(),
- std::string("unimplemented AArch64 builtin call: ") +
- getContext().BuiltinInfo.getName(builtinID));
- return mlir::Value{};
case NEON::BI__builtin_neon_vget_lane_mf8:
case NEON::BI__builtin_neon_vdupb_lane_mf8:
case NEON::BI__builtin_neon_vgetq_lane_mf8:
>From 7f74a5a352a414752a16aa49f0f10c56fdafe664 Mon Sep 17 00:00:00 2001
From: Ayush3941 <ayushkgaur1 at gmail.com>
Date: Thu, 12 Mar 2026 09:58:24 -0400
Subject: [PATCH 3/5] [CIR][AArch64] Upstream Neon vget_lane/vgetq_lane
builtins v2 fixed format
---
.../lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp | 48 +++++++++----------
1 file changed, 24 insertions(+), 24 deletions(-)
diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
index 275bf56411d87..d7347c55de6cd 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
@@ -2731,8 +2731,8 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr,
case NEON::BI__builtin_neon_vget_lane_i8:
ops[0] = builder.createBitcast(ops[0], cir::VectorType::get(uInt8Ty, 8));
- return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()), ops[0],
- emitScalarExpr(expr->getArg(1)));
+ return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()),
+ ops[0], emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vdupb_lane_i8:
cgm.errorNYI(expr->getSourceRange(),
std::string("unimplemented AArch64 builtin call: ") +
@@ -2741,8 +2741,8 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr,
case NEON::BI__builtin_neon_vgetq_lane_i8:
ops[0] = builder.createBitcast(ops[0], cir::VectorType::get(uInt8Ty, 16));
- return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()), ops[0],
- emitScalarExpr(expr->getArg(1)));
+ return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()),
+ ops[0], emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vdupb_laneq_i8:
case NEON::BI__builtin_neon_vget_lane_mf8:
case NEON::BI__builtin_neon_vdupb_lane_mf8:
@@ -2754,8 +2754,8 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr,
return mlir::Value{};
case NEON::BI__builtin_neon_vget_lane_i16:
ops[0] = builder.createBitcast(ops[0], cir::VectorType::get(uInt16Ty, 4));
- return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()), ops[0],
- emitScalarExpr(expr->getArg(1)));
+ return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()),
+ ops[0], emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vduph_lane_i16:
cgm.errorNYI(expr->getSourceRange(),
std::string("unimplemented AArch64 builtin call: ") +
@@ -2763,8 +2763,8 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr,
return mlir::Value{};
case NEON::BI__builtin_neon_vgetq_lane_i16:
ops[0] = builder.createBitcast(ops[0], cir::VectorType::get(uInt16Ty, 8));
- return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()), ops[0],
- emitScalarExpr(expr->getArg(1)));
+ return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()),
+ ops[0], emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vduph_laneq_i16:
cgm.errorNYI(expr->getSourceRange(),
std::string("unimplemented AArch64 builtin call: ") +
@@ -2772,8 +2772,8 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr,
return mlir::Value{};
case NEON::BI__builtin_neon_vget_lane_i32:
ops[0] = builder.createBitcast(ops[0], cir::VectorType::get(uInt32Ty, 2));
- return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()), ops[0],
- emitScalarExpr(expr->getArg(1)));
+ return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()),
+ ops[0], emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vdups_lane_i32:
case NEON::BI__builtin_neon_vdups_lane_f32:
cgm.errorNYI(expr->getSourceRange(),
@@ -2782,8 +2782,8 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr,
return mlir::Value{};
case NEON::BI__builtin_neon_vgetq_lane_i32:
ops[0] = builder.createBitcast(ops[0], cir::VectorType::get(uInt32Ty, 4));
- return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()), ops[0],
- emitScalarExpr(expr->getArg(1)));
+ return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()),
+ ops[0], emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vdups_laneq_i32:
cgm.errorNYI(expr->getSourceRange(),
std::string("unimplemented AArch64 builtin call: ") +
@@ -2791,8 +2791,8 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr,
return mlir::Value{};
case NEON::BI__builtin_neon_vget_lane_i64:
ops[0] = builder.createBitcast(ops[0], cir::VectorType::get(uInt64Ty, 1));
- return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()), ops[0],
- emitScalarExpr(expr->getArg(1)));
+ return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()),
+ ops[0], emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vdupd_lane_i64:
case NEON::BI__builtin_neon_vdupd_lane_f64:
cgm.errorNYI(expr->getSourceRange(),
@@ -2801,8 +2801,8 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr,
return mlir::Value{};
case NEON::BI__builtin_neon_vgetq_lane_i64:
ops[0] = builder.createBitcast(ops[0], cir::VectorType::get(uInt64Ty, 2));
- return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()), ops[0],
- emitScalarExpr(expr->getArg(1)));
+ return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()),
+ ops[0], emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vdupd_laneq_i64:
cgm.errorNYI(expr->getSourceRange(),
std::string("unimplemented AArch64 builtin call: ") +
@@ -2810,16 +2810,16 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr,
return mlir::Value{};
case NEON::BI__builtin_neon_vget_lane_f32:
ops[0] = builder.createBitcast(ops[0], cir::VectorType::get(floatTy, 2));
- return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()), ops[0],
- emitScalarExpr(expr->getArg(1)));
+ return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()),
+ ops[0], emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vget_lane_f64:
ops[0] = builder.createBitcast(ops[0], cir::VectorType::get(doubleTy, 1));
- return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()), ops[0],
- emitScalarExpr(expr->getArg(1)));
+ return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()),
+ ops[0], emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vgetq_lane_f32:
ops[0] = builder.createBitcast(ops[0], cir::VectorType::get(floatTy, 4));
- return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()), ops[0],
- emitScalarExpr(expr->getArg(1)));
+ return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()),
+ ops[0], emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vdups_laneq_f32:
cgm.errorNYI(expr->getSourceRange(),
std::string("unimplemented AArch64 builtin call: ") +
@@ -2827,8 +2827,8 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr,
return mlir::Value{};
case NEON::BI__builtin_neon_vgetq_lane_f64:
ops[0] = builder.createBitcast(ops[0], cir::VectorType::get(doubleTy, 2));
- return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()), ops[0],
- emitScalarExpr(expr->getArg(1)));
+ return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()),
+ ops[0], emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vdupd_laneq_f64:
case NEON::BI__builtin_neon_vaddh_f16:
case NEON::BI__builtin_neon_vsubh_f16:
>From 171931ff99d17d4008d1ec665ef69866fcfa394b Mon Sep 17 00:00:00 2001
From: Ayush3941 <ayushkgaur1 at gmail.com>
Date: Fri, 20 Mar 2026 09:15:18 -0400
Subject: [PATCH 4/5] [CIR][AArch64] Upstream Neon vget_lane/vgetq_lane
builtins v3
---
clang/test/CodeGen/AArch64/neon-vget.c | 155 ------------------
.../AArch64/neon/{neon-vget.c => getset.c} | 84 ++++------
clang/test/CodeGen/AArch64/poly64.c | 20 ---
3 files changed, 29 insertions(+), 230 deletions(-)
rename clang/test/CodeGen/AArch64/neon/{neon-vget.c => getset.c} (82%)
diff --git a/clang/test/CodeGen/AArch64/neon-vget.c b/clang/test/CodeGen/AArch64/neon-vget.c
index ebc8c2f9228ed..df399b3901f74 100644
--- a/clang/test/CodeGen/AArch64/neon-vget.c
+++ b/clang/test/CodeGen/AArch64/neon-vget.c
@@ -6,69 +6,6 @@
#include <arm_neon.h>
-// CHECK-LABEL: define{{.*}} i8 @test_vget_lane_u8(<8 x i8> noundef %a) #0 {
-// CHECK: [[VGET_LANE:%.*]] = extractelement <8 x i8> %a, i32 7
-// CHECK: ret i8 [[VGET_LANE]]
-uint8_t test_vget_lane_u8(uint8x8_t a) {
- return vget_lane_u8(a, 7);
-}
-
-// CHECK-LABEL: define{{.*}} i16 @test_vget_lane_u16(<4 x i16> noundef %a) #0 {
-// CHECK: [[VGET_LANE:%.*]] = extractelement <4 x i16> %a, i32 3
-// CHECK: ret i16 [[VGET_LANE]]
-uint16_t test_vget_lane_u16(uint16x4_t a) {
- return vget_lane_u16(a, 3);
-}
-
-// CHECK-LABEL: define{{.*}} i32 @test_vget_lane_u32(<2 x i32> noundef %a) #0 {
-// CHECK: [[VGET_LANE:%.*]] = extractelement <2 x i32> %a, i32 1
-// CHECK: ret i32 [[VGET_LANE]]
-uint32_t test_vget_lane_u32(uint32x2_t a) {
- return vget_lane_u32(a, 1);
-}
-
-// CHECK-LABEL: define{{.*}} i8 @test_vget_lane_s8(<8 x i8> noundef %a) #0 {
-// CHECK: [[VGET_LANE:%.*]] = extractelement <8 x i8> %a, i32 7
-// CHECK: ret i8 [[VGET_LANE]]
-int8_t test_vget_lane_s8(int8x8_t a) {
- return vget_lane_s8(a, 7);
-}
-
-// CHECK-LABEL: define{{.*}} i16 @test_vget_lane_s16(<4 x i16> noundef %a) #0 {
-// CHECK: [[VGET_LANE:%.*]] = extractelement <4 x i16> %a, i32 3
-// CHECK: ret i16 [[VGET_LANE]]
-int16_t test_vget_lane_s16(int16x4_t a) {
- return vget_lane_s16(a, 3);
-}
-
-// CHECK-LABEL: define{{.*}} i32 @test_vget_lane_s32(<2 x i32> noundef %a) #0 {
-// CHECK: [[VGET_LANE:%.*]] = extractelement <2 x i32> %a, i32 1
-// CHECK: ret i32 [[VGET_LANE]]
-int32_t test_vget_lane_s32(int32x2_t a) {
- return vget_lane_s32(a, 1);
-}
-
-// CHECK-LABEL: define{{.*}} i8 @test_vget_lane_p8(<8 x i8> noundef %a) #0 {
-// CHECK: [[VGET_LANE:%.*]] = extractelement <8 x i8> %a, i32 7
-// CHECK: ret i8 [[VGET_LANE]]
-poly8_t test_vget_lane_p8(poly8x8_t a) {
- return vget_lane_p8(a, 7);
-}
-
-// CHECK-LABEL: define{{.*}} i16 @test_vget_lane_p16(<4 x i16> noundef %a) #0 {
-// CHECK: [[VGET_LANE:%.*]] = extractelement <4 x i16> %a, i32 3
-// CHECK: ret i16 [[VGET_LANE]]
-poly16_t test_vget_lane_p16(poly16x4_t a) {
- return vget_lane_p16(a, 3);
-}
-
-// CHECK-LABEL: define{{.*}} float @test_vget_lane_f32(<2 x float> noundef %a) #0 {
-// CHECK: [[VGET_LANE:%.*]] = extractelement <2 x float> %a, i32 1
-// CHECK: ret float [[VGET_LANE]]
-float32_t test_vget_lane_f32(float32x2_t a) {
- return vget_lane_f32(a, 1);
-}
-
// CHECK-LABEL: define{{.*}} float @test_vget_lane_f16(<4 x half> noundef %a) #0 {
// CHECK: [[__REINT_242:%.*]] = alloca <4 x half>, align 8
// CHECK: [[__REINT1_242:%.*]] = alloca i16, align 2
@@ -83,69 +20,6 @@ float32_t test_vget_lane_f16(float16x4_t a) {
return vget_lane_f16(a, 1);
}
-// CHECK-LABEL: define{{.*}} i8 @test_vgetq_lane_u8(<16 x i8> noundef %a) #0 {
-// CHECK: [[VGETQ_LANE:%.*]] = extractelement <16 x i8> %a, i32 15
-// CHECK: ret i8 [[VGETQ_LANE]]
-uint8_t test_vgetq_lane_u8(uint8x16_t a) {
- return vgetq_lane_u8(a, 15);
-}
-
-// CHECK-LABEL: define{{.*}} i16 @test_vgetq_lane_u16(<8 x i16> noundef %a) #0 {
-// CHECK: [[VGETQ_LANE:%.*]] = extractelement <8 x i16> %a, i32 7
-// CHECK: ret i16 [[VGETQ_LANE]]
-uint16_t test_vgetq_lane_u16(uint16x8_t a) {
- return vgetq_lane_u16(a, 7);
-}
-
-// CHECK-LABEL: define{{.*}} i32 @test_vgetq_lane_u32(<4 x i32> noundef %a) #0 {
-// CHECK: [[VGETQ_LANE:%.*]] = extractelement <4 x i32> %a, i32 3
-// CHECK: ret i32 [[VGETQ_LANE]]
-uint32_t test_vgetq_lane_u32(uint32x4_t a) {
- return vgetq_lane_u32(a, 3);
-}
-
-// CHECK-LABEL: define{{.*}} i8 @test_vgetq_lane_s8(<16 x i8> noundef %a) #0 {
-// CHECK: [[VGETQ_LANE:%.*]] = extractelement <16 x i8> %a, i32 15
-// CHECK: ret i8 [[VGETQ_LANE]]
-int8_t test_vgetq_lane_s8(int8x16_t a) {
- return vgetq_lane_s8(a, 15);
-}
-
-// CHECK-LABEL: define{{.*}} i16 @test_vgetq_lane_s16(<8 x i16> noundef %a) #0 {
-// CHECK: [[VGETQ_LANE:%.*]] = extractelement <8 x i16> %a, i32 7
-// CHECK: ret i16 [[VGETQ_LANE]]
-int16_t test_vgetq_lane_s16(int16x8_t a) {
- return vgetq_lane_s16(a, 7);
-}
-
-// CHECK-LABEL: define{{.*}} i32 @test_vgetq_lane_s32(<4 x i32> noundef %a) #0 {
-// CHECK: [[VGETQ_LANE:%.*]] = extractelement <4 x i32> %a, i32 3
-// CHECK: ret i32 [[VGETQ_LANE]]
-int32_t test_vgetq_lane_s32(int32x4_t a) {
- return vgetq_lane_s32(a, 3);
-}
-
-// CHECK-LABEL: define{{.*}} i8 @test_vgetq_lane_p8(<16 x i8> noundef %a) #0 {
-// CHECK: [[VGETQ_LANE:%.*]] = extractelement <16 x i8> %a, i32 15
-// CHECK: ret i8 [[VGETQ_LANE]]
-poly8_t test_vgetq_lane_p8(poly8x16_t a) {
- return vgetq_lane_p8(a, 15);
-}
-
-// CHECK-LABEL: define{{.*}} i16 @test_vgetq_lane_p16(<8 x i16> noundef %a) #0 {
-// CHECK: [[VGETQ_LANE:%.*]] = extractelement <8 x i16> %a, i32 7
-// CHECK: ret i16 [[VGETQ_LANE]]
-poly16_t test_vgetq_lane_p16(poly16x8_t a) {
- return vgetq_lane_p16(a, 7);
-}
-
-// CHECK-LABEL: define{{.*}} float @test_vgetq_lane_f32(<4 x float> noundef %a) #0 {
-// CHECK: [[VGETQ_LANE:%.*]] = extractelement <4 x float> %a, i32 3
-// CHECK: ret float [[VGETQ_LANE]]
-float32_t test_vgetq_lane_f32(float32x4_t a) {
- return vgetq_lane_f32(a, 3);
-}
-
// CHECK-LABEL: define{{.*}} float @test_vgetq_lane_f16(<8 x half> noundef %a) #0 {
// CHECK: [[__REINT_244:%.*]] = alloca <8 x half>, align 16
// CHECK: [[__REINT1_244:%.*]] = alloca i16, align 2
@@ -160,35 +34,6 @@ float32_t test_vgetq_lane_f16(float16x8_t a) {
return vgetq_lane_f16(a, 3);
}
-// CHECK-LABEL: define{{.*}} i64 @test_vget_lane_s64(<1 x i64> noundef %a) #0 {
-// CHECK: [[VGET_LANE:%.*]] = extractelement <1 x i64> %a, i32 0
-// CHECK: ret i64 [[VGET_LANE]]
-int64_t test_vget_lane_s64(int64x1_t a) {
- return vget_lane_s64(a, 0);
-}
-
-// CHECK-LABEL: define{{.*}} i64 @test_vget_lane_u64(<1 x i64> noundef %a) #0 {
-// CHECK: [[VGET_LANE:%.*]] = extractelement <1 x i64> %a, i32 0
-// CHECK: ret i64 [[VGET_LANE]]
-uint64_t test_vget_lane_u64(uint64x1_t a) {
- return vget_lane_u64(a, 0);
-}
-
-// CHECK-LABEL: define{{.*}} i64 @test_vgetq_lane_s64(<2 x i64> noundef %a) #0 {
-// CHECK: [[VGETQ_LANE:%.*]] = extractelement <2 x i64> %a, i32 1
-// CHECK: ret i64 [[VGETQ_LANE]]
-int64_t test_vgetq_lane_s64(int64x2_t a) {
- return vgetq_lane_s64(a, 1);
-}
-
-// CHECK-LABEL: define{{.*}} i64 @test_vgetq_lane_u64(<2 x i64> noundef %a) #0 {
-// CHECK: [[VGETQ_LANE:%.*]] = extractelement <2 x i64> %a, i32 1
-// CHECK: ret i64 [[VGETQ_LANE]]
-uint64_t test_vgetq_lane_u64(uint64x2_t a) {
- return vgetq_lane_u64(a, 1);
-}
-
-
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vset_lane_u8(i8 noundef %a, <8 x i8> noundef %b) #0 {
// CHECK: [[VSET_LANE:%.*]] = insertelement <8 x i8> %b, i8 %a, i32 7
// CHECK: ret <8 x i8> [[VSET_LANE]]
diff --git a/clang/test/CodeGen/AArch64/neon/neon-vget.c b/clang/test/CodeGen/AArch64/neon/getset.c
similarity index 82%
rename from clang/test/CodeGen/AArch64/neon/neon-vget.c
rename to clang/test/CodeGen/AArch64/neon/getset.c
index 297a07ced2f41..0f697cbcf87e0 100644
--- a/clang/test/CodeGen/AArch64/neon/neon-vget.c
+++ b/clang/test/CodeGen/AArch64/neon/getset.c
@@ -1,8 +1,8 @@
// REQUIRES: aarch64-registered-target || arm-registered-target
-// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -flax-vector-conversions=none -emit-llvm -o - %s | opt -S -passes=mem2reg,sroa | FileCheck %s --check-prefixes=LLVM
-// RUN: %if cir-enabled %{%clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -flax-vector-conversions=none -fclangir -emit-llvm -o - %s | opt -S -passes=mem2reg,sroa | FileCheck %s --check-prefixes=LLVM %}
-// RUN: %if cir-enabled %{%clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -flax-vector-conversions=none -fclangir -emit-cir -o - %s | FileCheck %s --check-prefixes=CIR %}
+// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -flax-vector-conversions=none -emit-llvm -o - %s | opt -S -passes=mem2reg,sroa | FileCheck %s --check-prefixes=ALL,LLVM
+// RUN: %if cir-enabled %{%clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -flax-vector-conversions=none -fclangir -emit-llvm -o - %s | opt -S -passes=mem2reg,sroa | FileCheck %s --check-prefixes=ALL,LLVM %}
+// RUN: %if cir-enabled %{%clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -flax-vector-conversions=none -fclangir -emit-cir -o - %s | FileCheck %s --check-prefixes=ALL,CIR %}
//=============================================================================
// NOTES
@@ -25,8 +25,7 @@
// Extract one element from vector
//===------------------------------------------------------===//
-// LLVM-LABEL: @test_vget_lane_u8(
-// CIR-LABEL: @test_vget_lane_u8(
+// ALL-LABEL: @test_vget_lane_u8(
uint8_t test_vget_lane_u8(uint8x8_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : {{.*}}] : !cir.vector<8 x !u8i>
@@ -35,8 +34,7 @@ uint8_t test_vget_lane_u8(uint8x8_t a) {
return vget_lane_u8(a, 7);
}
-// LLVM-LABEL: @test_vget_lane_u16(
-// CIR-LABEL: @test_vget_lane_u16(
+// ALL-LABEL: @test_vget_lane_u16(
uint16_t test_vget_lane_u16(uint16x4_t a) {
// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<4 x !u16i>
// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<4 x !u16i>
@@ -46,8 +44,7 @@ uint16_t test_vget_lane_u16(uint16x4_t a) {
return vget_lane_u16(a, 3);
}
-// LLVM-LABEL: @test_vget_lane_u32(
-// CIR-LABEL: @test_vget_lane_u32(
+// ALL-LABEL: @test_vget_lane_u32(
uint32_t test_vget_lane_u32(uint32x2_t a) {
// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<2 x !u32i>
// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<2 x !u32i>
@@ -57,8 +54,7 @@ uint32_t test_vget_lane_u32(uint32x2_t a) {
return vget_lane_u32(a, 1);
}
-// LLVM-LABEL: @test_vget_lane_s8(
-// CIR-LABEL: @test_vget_lane_s8(
+// ALL-LABEL: @test_vget_lane_s8(
int8_t test_vget_lane_s8(int8x8_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : {{.*}}] : !cir.vector<8 x !u8i>
@@ -67,8 +63,7 @@ int8_t test_vget_lane_s8(int8x8_t a) {
return vget_lane_s8(a, 7);
}
-// LLVM-LABEL: @test_vget_lane_s16(
-// CIR-LABEL: @test_vget_lane_s16(
+// ALL-LABEL: @test_vget_lane_s16(
int16_t test_vget_lane_s16(int16x4_t a) {
// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<4 x !u16i>
// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<4 x !u16i>
@@ -78,8 +73,7 @@ int16_t test_vget_lane_s16(int16x4_t a) {
return vget_lane_s16(a, 3);
}
-// LLVM-LABEL: @test_vget_lane_s32(
-// CIR-LABEL: @test_vget_lane_s32(
+// ALL-LABEL: @test_vget_lane_s32(
int32_t test_vget_lane_s32(int32x2_t a) {
// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<2 x !u32i>
// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<2 x !u32i>
@@ -89,8 +83,7 @@ int32_t test_vget_lane_s32(int32x2_t a) {
return vget_lane_s32(a, 1);
}
-// LLVM-LABEL: @test_vget_lane_p8(
-// CIR-LABEL: @test_vget_lane_p8(
+// ALL-LABEL: @test_vget_lane_p8(
poly8_t test_vget_lane_p8(poly8x8_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : {{.*}}] : !cir.vector<8 x !u8i>
@@ -99,8 +92,7 @@ poly8_t test_vget_lane_p8(poly8x8_t a) {
return vget_lane_p8(a, 7);
}
-// LLVM-LABEL: @test_vget_lane_p16(
-// CIR-LABEL: @test_vget_lane_p16(
+// ALL-LABEL: @test_vget_lane_p16(
poly16_t test_vget_lane_p16(poly16x4_t a) {
// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<4 x !u16i>
// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<4 x !u16i>
@@ -110,8 +102,7 @@ poly16_t test_vget_lane_p16(poly16x4_t a) {
return vget_lane_p16(a, 3);
}
-// LLVM-LABEL: @test_vget_lane_f32(
-// CIR-LABEL: @test_vget_lane_f32(
+// ALL-LABEL: @test_vget_lane_f32(
float32_t test_vget_lane_f32(float32x2_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : {{.*}}] : !cir.vector<2 x !cir.float>
@@ -120,8 +111,7 @@ float32_t test_vget_lane_f32(float32x2_t a) {
return vget_lane_f32(a, 1);
}
-// LLVM-LABEL: @test_vget_lane_f64(
-// CIR-LABEL: @test_vget_lane_f64(
+// ALL-LABEL: @test_vget_lane_f64(
float64_t test_vget_lane_f64(float64x1_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : {{.*}}] : !cir.vector<1 x !cir.double>
@@ -130,8 +120,7 @@ float64_t test_vget_lane_f64(float64x1_t a) {
return vget_lane_f64(a, 0);
}
-// LLVM-LABEL: @test_vgetq_lane_u8(
-// CIR-LABEL: @test_vgetq_lane_u8(
+// ALL-LABEL: @test_vgetq_lane_u8(
uint8_t test_vgetq_lane_u8(uint8x16_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : {{.*}}] : !cir.vector<16 x !u8i>
@@ -140,8 +129,7 @@ uint8_t test_vgetq_lane_u8(uint8x16_t a) {
return vgetq_lane_u8(a, 15);
}
-// LLVM-LABEL: @test_vgetq_lane_u16(
-// CIR-LABEL: @test_vgetq_lane_u16(
+// ALL-LABEL: @test_vgetq_lane_u16(
uint16_t test_vgetq_lane_u16(uint16x8_t a) {
// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<8 x !u16i>
// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<8 x !u16i>
@@ -151,8 +139,7 @@ uint16_t test_vgetq_lane_u16(uint16x8_t a) {
return vgetq_lane_u16(a, 7);
}
-// LLVM-LABEL: @test_vgetq_lane_u32(
-// CIR-LABEL: @test_vgetq_lane_u32(
+// ALL-LABEL: @test_vgetq_lane_u32(
uint32_t test_vgetq_lane_u32(uint32x4_t a) {
// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<4 x !u32i>
// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<4 x !u32i>
@@ -162,8 +149,7 @@ uint32_t test_vgetq_lane_u32(uint32x4_t a) {
return vgetq_lane_u32(a, 3);
}
-// LLVM-LABEL: @test_vgetq_lane_s8(
-// CIR-LABEL: @test_vgetq_lane_s8(
+// ALL-LABEL: @test_vgetq_lane_s8(
int8_t test_vgetq_lane_s8(int8x16_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : {{.*}}] : !cir.vector<16 x !u8i>
@@ -172,8 +158,7 @@ int8_t test_vgetq_lane_s8(int8x16_t a) {
return vgetq_lane_s8(a, 15);
}
-// LLVM-LABEL: @test_vgetq_lane_s16(
-// CIR-LABEL: @test_vgetq_lane_s16(
+// ALL-LABEL: @test_vgetq_lane_s16(
int16_t test_vgetq_lane_s16(int16x8_t a) {
// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<8 x !u16i>
// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<8 x !u16i>
@@ -183,8 +168,7 @@ int16_t test_vgetq_lane_s16(int16x8_t a) {
return vgetq_lane_s16(a, 7);
}
-// LLVM-LABEL: @test_vgetq_lane_s32(
-// CIR-LABEL: @test_vgetq_lane_s32(
+// ALL-LABEL: @test_vgetq_lane_s32(
int32_t test_vgetq_lane_s32(int32x4_t a) {
// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<4 x !u32i>
// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<4 x !u32i>
@@ -194,8 +178,7 @@ int32_t test_vgetq_lane_s32(int32x4_t a) {
return vgetq_lane_s32(a, 3);
}
-// LLVM-LABEL: @test_vgetq_lane_p8(
-// CIR-LABEL: @test_vgetq_lane_p8(
+// ALL-LABEL: @test_vgetq_lane_p8(
poly8_t test_vgetq_lane_p8(poly8x16_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : {{.*}}] : !cir.vector<16 x !u8i>
@@ -204,8 +187,7 @@ poly8_t test_vgetq_lane_p8(poly8x16_t a) {
return vgetq_lane_p8(a, 15);
}
-// LLVM-LABEL: @test_vgetq_lane_p16(
-// CIR-LABEL: @test_vgetq_lane_p16(
+// ALL-LABEL: @test_vgetq_lane_p16(
poly16_t test_vgetq_lane_p16(poly16x8_t a) {
// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<8 x !u16i>
// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<8 x !u16i>
@@ -215,8 +197,7 @@ poly16_t test_vgetq_lane_p16(poly16x8_t a) {
return vgetq_lane_p16(a, 7);
}
-// LLVM-LABEL: @test_vgetq_lane_f32(
-// CIR-LABEL: @test_vgetq_lane_f32(
+// ALL-LABEL: @test_vgetq_lane_f32(
float32_t test_vgetq_lane_f32(float32x4_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : {{.*}}] : !cir.vector<4 x !cir.float>
@@ -225,8 +206,7 @@ float32_t test_vgetq_lane_f32(float32x4_t a) {
return vgetq_lane_f32(a, 3);
}
-// LLVM-LABEL: @test_vgetq_lane_f64(
-// CIR-LABEL: @test_vgetq_lane_f64(
+// ALL-LABEL: @test_vgetq_lane_f64(
float64_t test_vgetq_lane_f64(float64x2_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : {{.*}}] : !cir.vector<2 x !cir.double>
@@ -235,8 +215,7 @@ float64_t test_vgetq_lane_f64(float64x2_t a) {
return vgetq_lane_f64(a, 1);
}
-// LLVM-LABEL: @test_vget_lane_s64(
-// CIR-LABEL: @test_vget_lane_s64(
+// ALL-LABEL: @test_vget_lane_s64(
int64_t test_vget_lane_s64(int64x1_t a) {
// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<1 x !u64i>
// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<1 x !u64i>
@@ -246,8 +225,7 @@ int64_t test_vget_lane_s64(int64x1_t a) {
return vget_lane_s64(a, 0);
}
-// LLVM-LABEL: @test_vget_lane_u64(
-// CIR-LABEL: @test_vget_lane_u64(
+// ALL-LABEL: @test_vget_lane_u64(
uint64_t test_vget_lane_u64(uint64x1_t a) {
// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<1 x !u64i>
// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<1 x !u64i>
@@ -257,8 +235,7 @@ uint64_t test_vget_lane_u64(uint64x1_t a) {
return vget_lane_u64(a, 0);
}
-// LLVM-LABEL: @test_vget_lane_p64(
-// CIR-LABEL: @test_vget_lane_p64(
+// ALL-LABEL: @test_vget_lane_p64(
poly64_t test_vget_lane_p64(poly64x1_t v) {
// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<1 x !u64i>
// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<1 x !u64i>
@@ -268,8 +245,7 @@ poly64_t test_vget_lane_p64(poly64x1_t v) {
return vget_lane_p64(v, 0);
}
-// LLVM-LABEL: @test_vgetq_lane_s64(
-// CIR-LABEL: @test_vgetq_lane_s64(
+// ALL-LABEL: @test_vgetq_lane_s64(
int64_t test_vgetq_lane_s64(int64x2_t a) {
// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<2 x !u64i>
// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<2 x !u64i>
@@ -279,8 +255,7 @@ int64_t test_vgetq_lane_s64(int64x2_t a) {
return vgetq_lane_s64(a, 1);
}
-// LLVM-LABEL: @test_vgetq_lane_u64(
-// CIR-LABEL: @test_vgetq_lane_u64(
+// ALL-LABEL: @test_vgetq_lane_u64(
uint64_t test_vgetq_lane_u64(uint64x2_t a) {
// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<2 x !u64i>
// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<2 x !u64i>
@@ -290,8 +265,7 @@ uint64_t test_vgetq_lane_u64(uint64x2_t a) {
return vgetq_lane_u64(a, 1);
}
-// LLVM-LABEL: @test_vgetq_lane_p64(
-// CIR-LABEL: @test_vgetq_lane_p64(
+// ALL-LABEL: @test_vgetq_lane_p64(
poly64_t test_vgetq_lane_p64(poly64x2_t v) {
// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<2 x !u64i>
// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<2 x !u64i>
diff --git a/clang/test/CodeGen/AArch64/poly64.c b/clang/test/CodeGen/AArch64/poly64.c
index 00838b648dfe6..67c9afd188381 100644
--- a/clang/test/CodeGen/AArch64/poly64.c
+++ b/clang/test/CodeGen/AArch64/poly64.c
@@ -99,26 +99,6 @@ poly64x2_t test_vbslq_p64(poly64x2_t a, poly64x2_t b, poly64x2_t c) {
return vbslq_p64(a, b, c);
}
-// CHECK-LABEL: define dso_local i64 @test_vget_lane_p64(
-// CHECK-SAME: <1 x i64> noundef [[V:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[VGET_LANE:%.*]] = extractelement <1 x i64> [[V]], i32 0
-// CHECK-NEXT: ret i64 [[VGET_LANE]]
-//
-poly64_t test_vget_lane_p64(poly64x1_t v) {
- return vget_lane_p64(v, 0);
-}
-
-// CHECK-LABEL: define dso_local i64 @test_vgetq_lane_p64(
-// CHECK-SAME: <2 x i64> noundef [[V:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[VGETQ_LANE:%.*]] = extractelement <2 x i64> [[V]], i32 1
-// CHECK-NEXT: ret i64 [[VGETQ_LANE]]
-//
-poly64_t test_vgetq_lane_p64(poly64x2_t v) {
- return vgetq_lane_p64(v, 1);
-}
-
// CHECK-LABEL: define dso_local <1 x i64> @test_vset_lane_p64(
// CHECK-SAME: i64 noundef [[A:%.*]], <1 x i64> noundef [[V:%.*]]) #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
>From 45f3d2135eeeb55825068d3e455495c3a8a6045a Mon Sep 17 00:00:00 2001
From: Ayush3941 <ayushkgaur1 at gmail.com>
Date: Fri, 20 Mar 2026 10:04:39 -0400
Subject: [PATCH 5/5] [CIR][AArch64] Upstream Neon vget_lane/vgetq_lane
builtins v3.5
---
clang/test/CodeGen/AArch64/neon-vget.c | 28 ------------------
clang/test/CodeGen/AArch64/neon/getset.c | 37 ++++++++++++++++++++----
2 files changed, 32 insertions(+), 33 deletions(-)
diff --git a/clang/test/CodeGen/AArch64/neon-vget.c b/clang/test/CodeGen/AArch64/neon-vget.c
index df399b3901f74..9d5c5e61a2dcd 100644
--- a/clang/test/CodeGen/AArch64/neon-vget.c
+++ b/clang/test/CodeGen/AArch64/neon-vget.c
@@ -6,34 +6,6 @@
#include <arm_neon.h>
-// CHECK-LABEL: define{{.*}} float @test_vget_lane_f16(<4 x half> noundef %a) #0 {
-// CHECK: [[__REINT_242:%.*]] = alloca <4 x half>, align 8
-// CHECK: [[__REINT1_242:%.*]] = alloca i16, align 2
-// CHECK: store <4 x half> %a, ptr [[__REINT_242]], align 8
-// CHECK: [[TMP1:%.*]] = load <4 x i16>, ptr [[__REINT_242]], align 8
-// CHECK: [[VGET_LANE:%.*]] = extractelement <4 x i16> [[TMP1]], i32 1
-// CHECK: store i16 [[VGET_LANE]], ptr [[__REINT1_242]], align 2
-// CHECK: [[TMP5:%.*]] = load half, ptr [[__REINT1_242]], align 2
-// CHECK: [[CONV:%.*]] = fpext half [[TMP5]] to float
-// CHECK: ret float [[CONV]]
-float32_t test_vget_lane_f16(float16x4_t a) {
- return vget_lane_f16(a, 1);
-}
-
-// CHECK-LABEL: define{{.*}} float @test_vgetq_lane_f16(<8 x half> noundef %a) #0 {
-// CHECK: [[__REINT_244:%.*]] = alloca <8 x half>, align 16
-// CHECK: [[__REINT1_244:%.*]] = alloca i16, align 2
-// CHECK: store <8 x half> %a, ptr [[__REINT_244]], align 16
-// CHECK: [[TMP1:%.*]] = load <8 x i16>, ptr [[__REINT_244]], align 16
-// CHECK: [[VGETQ_LANE:%.*]] = extractelement <8 x i16> [[TMP1]], i32 3
-// CHECK: store i16 [[VGETQ_LANE]], ptr [[__REINT1_244]], align 2
-// CHECK: [[TMP5:%.*]] = load half, ptr [[__REINT1_244]], align 2
-// CHECK: [[CONV:%.*]] = fpext half [[TMP5]] to float
-// CHECK: ret float [[CONV]]
-float32_t test_vgetq_lane_f16(float16x8_t a) {
- return vgetq_lane_f16(a, 3);
-}
-
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vset_lane_u8(i8 noundef %a, <8 x i8> noundef %b) #0 {
// CHECK: [[VSET_LANE:%.*]] = insertelement <8 x i8> %b, i8 %a, i32 7
// CHECK: ret <8 x i8> [[VSET_LANE]]
diff --git a/clang/test/CodeGen/AArch64/neon/getset.c b/clang/test/CodeGen/AArch64/neon/getset.c
index 0f697cbcf87e0..b7d5870581caf 100644
--- a/clang/test/CodeGen/AArch64/neon/getset.c
+++ b/clang/test/CodeGen/AArch64/neon/getset.c
@@ -12,11 +12,6 @@
// * clang/test/CodeGen/AArch64/poly64.c
// The main difference is the use of RUN lines that enable ClangIR lowering;
// therefore only builtins currently supported by ClangIR are tested here.
-//
-// The half-precision extract variants are intentionally omitted here because
-// they lower through the vduph_* builtin IDs, which are still unsupported in
-// CIR for this patch.
-//
//=============================================================================
#include <arm_neon.h>
@@ -102,6 +97,22 @@ poly16_t test_vget_lane_p16(poly16x4_t a) {
return vget_lane_p16(a, 3);
}
+// ALL-LABEL: @test_vget_lane_f16(
+float32_t test_vget_lane_f16(float16x4_t a) {
+// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<4 x !u16i>
+// CIR: [[ELEM:%.*]] = cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<4 x !u16i>
+// CIR: [[HALF:%.*]] = cir.cast bitcast [[ELEM]] : !u16i -> !cir.f16
+// CIR: [[RES:%.*]] = cir.cast floating [[HALF]] : !cir.f16 -> !cir.float
+// CIR: cir.return [[RES]] : !cir.float
+
+// LLVM: [[TMP:%.*]] = bitcast <4 x half> %{{.*}} to <4 x i16>
+// LLVM: [[VGET_LANE:%.*]] = extractelement <4 x i16> [[TMP]], i32 1
+// LLVM: [[HALF:%.*]] = bitcast i16 [[VGET_LANE]] to half
+// LLVM: [[RES:%.*]] = fpext half [[HALF]] to float
+// LLVM: ret float [[RES]]
+ return vget_lane_f16(a, 1);
+}
+
// ALL-LABEL: @test_vget_lane_f32(
float32_t test_vget_lane_f32(float32x2_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : {{.*}}] : !cir.vector<2 x !cir.float>
@@ -197,6 +208,22 @@ poly16_t test_vgetq_lane_p16(poly16x8_t a) {
return vgetq_lane_p16(a, 7);
}
+// ALL-LABEL: @test_vgetq_lane_f16(
+float32_t test_vgetq_lane_f16(float16x8_t a) {
+// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<8 x !u16i>
+// CIR: [[ELEM:%.*]] = cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<8 x !u16i>
+// CIR: [[HALF:%.*]] = cir.cast bitcast [[ELEM]] : !u16i -> !cir.f16
+// CIR: [[RES:%.*]] = cir.cast floating [[HALF]] : !cir.f16 -> !cir.float
+// CIR: cir.return [[RES]] : !cir.float
+
+// LLVM: [[TMP:%.*]] = bitcast <8 x half> %{{.*}} to <8 x i16>
+// LLVM: [[VGETQ_LANE:%.*]] = extractelement <8 x i16> [[TMP]], i32 3
+// LLVM: [[HALF:%.*]] = bitcast i16 [[VGETQ_LANE]] to half
+// LLVM: [[RES:%.*]] = fpext half [[HALF]] to float
+// LLVM: ret float [[RES]]
+ return vgetq_lane_f16(a, 3);
+}
+
// ALL-LABEL: @test_vgetq_lane_f32(
float32_t test_vgetq_lane_f32(float32x4_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : {{.*}}] : !cir.vector<4 x !cir.float>
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