[clang] [llvm] [AMDGPU] Split OPERAND_REG_IMM_INT64 into signed and unsigned variants (PR #186575)

[Jay Foad via cfe-commits]

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@@ -201,7 +201,8 @@ namespace AMDGPU {
 enum OperandType : unsigned {
   /// Operands with register, 32-bit, or 64-bit immediate
   OPERAND_REG_IMM_INT32 = MCOI::OPERAND_FIRST_TARGET,
-  OPERAND_REG_IMM_INT64,
+  OPERAND_REG_IMM_I64, // Signed 64-bit integer operand (uses isInt<32>)
+  OPERAND_REG_IMM_U64, // Unsigned 64-bit integer operand (uses isUInt<32>)
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jayfoad wrote:

IsInt/IsUInt is just an implementation detail. Don't keep repeating it in comments.

https://github.com/llvm/llvm-project/pull/186575