[clang] [CIR][AArch64] Upstream vrshrd_n_s64/u64 and vrshr_n_v vector rounding shift right (PR #185992)

[Md Mouzam Arfi Hussain via cfe-commits]

================
@@ -409,301 +407,6 @@ static const ARMVectorIntrinsicInfo AArch64SIMDIntrinsicMap[] = {
     NEONMAP1(vxarq_u64, aarch64_crypto_xar, 0),
 };
 
-// Single-Instruction-Single-Data (SISD) intrinsics.
----------------
ArfiH wrote:

Thank you for the feedback. I have updated the implementation to match the original codegen structure:

- `NEONMAP2(vrshr_n_v, ...)` and `NEONMAP2(vrshrq_n_v, ...)` are kept in
  `AArch64SIMDIntrinsicMap` so the routing stays consistent with the original codegen.
- The implementation is now inside `emitCommonNeonBuiltinExpr`, mirroring the original
  codegen's `EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vrshr_n", 1, true)` — using
  `emitNeonCall` with `shift=1, rightshift=true`.
- To support this, the `shift`/`rightshift` path in `emitNeonCallToOp` has been
  implemented (it previously hit `errorNYI`).
- `vrshrd_n_s64`/`vrshrd_n_u64` remain in the first switch, matching the original
  codegen's handling in the AArch64-specific section.

The updated patch will be pushed shortly once the build and tests complete.

https://github.com/llvm/llvm-project/pull/185992