[clang] [llvm] [RISCV] Support 'f' Inline Assembly Constraint for bfloat16 (PR #184566)

[via cfe-commits]

https://github.com/joshua-arch1 updated https://github.com/llvm/llvm-project/pull/184566

>From e383040c9bdfbde77fca740bde3ed1ffe541ef1a Mon Sep 17 00:00:00 2001
From: joshua-arch1 <cooper.joshua at linux.alibaba.com>
Date: Wed, 4 Mar 2026 17:08:06 +0800
Subject: [PATCH] [RISCV] Support 'f' Inline Assembly Constraint for bfloat16

---
 clang/test/CodeGen/RISCV/riscv-inline-asm.c | 4 ++++
 llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 2 ++
 2 files changed, 6 insertions(+)

diff --git a/clang/test/CodeGen/RISCV/riscv-inline-asm.c b/clang/test/CodeGen/RISCV/riscv-inline-asm.c
index f2031e0adcbcb..183ee7e34764c 100644
--- a/clang/test/CodeGen/RISCV/riscv-inline-asm.c
+++ b/clang/test/CodeGen/RISCV/riscv-inline-asm.c
@@ -78,6 +78,7 @@ void test_K(void) {
 
 float f;
 double d;
+__bf16 bf;
 void test_f(void) {
 // CHECK-LABEL: define{{.*}} void @test_f()
 // CHECK: [[FLT_ARG:%[a-zA-Z_0-9]+]] = load float, ptr @f
@@ -86,6 +87,9 @@ void test_f(void) {
 // CHECK: [[FLT_ARG:%[a-zA-Z_0-9]+]] = load double, ptr @d
 // CHECK: call void asm sideeffect "", "f"(double [[FLT_ARG]])
   asm volatile ("" :: "f"(d));
+// CHECK: [[FLT_ARG:%[a-zA-Z_0-9]+]] = load bfloat, ptr @bf
+// CHECK: call void asm sideeffect "", "f"(bfloat [[FLT_ARG]])
+  asm volatile ("" :: "f"(bf));
 }
 
 void test_A(int *p) {
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 7e62957529fea..c5b360052cdbb 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -25215,6 +25215,8 @@ RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
           return std::make_pair(0U, &RISCV::FPR16RegClass);
         if (Subtarget.hasStdExtZhinxmin())
           return std::make_pair(0U, &RISCV::GPRF16NoX0RegClass);
+      } else if (VT == MVT::bf16 && Subtarget.hasStdExtZfbfmin()) {
+        return std::make_pair(0U, &RISCV::FPR16RegClass);
       } else if (VT == MVT::f32) {
         if (Subtarget.hasStdExtF())
           return std::make_pair(0U, &RISCV::FPR32RegClass);