[clang] [llvm] [RISCV] Support 'f' Inline Assembly Constraint for bfloat16 (PR #184566)

[via cfe-commits]

https://github.com/joshua-arch1 created https://github.com/llvm/llvm-project/pull/184566

This patch is to add 'f' Inline Assembly Constraint for bfloat16 type.

>From bf5bc9ea83fb02f31783621d97c39a25de0329c8 Mon Sep 17 00:00:00 2001
From: joshua-arch1 <cooper.joshua at linux.alibaba.com>
Date: Wed, 4 Mar 2026 16:37:40 +0800
Subject: [PATCH] [RISCV] Support 'f' Inline Assembly Constraint for bfloat16

---
 clang/test/CodeGen/LoongArch/inline-asm-constraints.c | 3 +++
 clang/test/CodeGen/RISCV/riscv-inline-asm.c           | 3 +++
 llvm/lib/Target/RISCV/RISCVISelLowering.cpp           | 2 ++
 3 files changed, 8 insertions(+)

diff --git a/clang/test/CodeGen/LoongArch/inline-asm-constraints.c b/clang/test/CodeGen/LoongArch/inline-asm-constraints.c
index ded21206d63bf..f7e8b73e59dbd 100644
--- a/clang/test/CodeGen/LoongArch/inline-asm-constraints.c
+++ b/clang/test/CodeGen/LoongArch/inline-asm-constraints.c
@@ -13,6 +13,9 @@ void test_f(void) {
 // CHECK: [[FLT_ARG:%[a-zA-Z_0-9]+]] = load double, ptr @d
 // CHECK: call void asm sideeffect "", "f"(double [[FLT_ARG]])
   asm volatile ("" :: "f"(d));
+// CHECK: [[FLT_ARG:%[a-zA-Z_0-9]+]] = load bfloat, ptr @bf
+// CHECK: call void asm sideeffect "", "f"(bfloat [[FLT_ARG]])
+  asm volatile ("" :: "f"(bf));
 }
 
 void test_k(int *p, int idx) {
diff --git a/clang/test/CodeGen/RISCV/riscv-inline-asm.c b/clang/test/CodeGen/RISCV/riscv-inline-asm.c
index f2031e0adcbcb..02cd27ed92def 100644
--- a/clang/test/CodeGen/RISCV/riscv-inline-asm.c
+++ b/clang/test/CodeGen/RISCV/riscv-inline-asm.c
@@ -86,6 +86,9 @@ void test_f(void) {
 // CHECK: [[FLT_ARG:%[a-zA-Z_0-9]+]] = load double, ptr @d
 // CHECK: call void asm sideeffect "", "f"(double [[FLT_ARG]])
   asm volatile ("" :: "f"(d));
+// CHECK: [[FLT_ARG:%[a-zA-Z_0-9]+]] = load bfloat, ptr @bf
+// CHECK: call void asm sideeffect "", "f"(bfloat [[FLT_ARG]])
+  asm volatile ("" :: "f"(bf));
 }
 
 void test_A(int *p) {
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 7e62957529fea..c5b360052cdbb 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -25215,6 +25215,8 @@ RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
           return std::make_pair(0U, &RISCV::FPR16RegClass);
         if (Subtarget.hasStdExtZhinxmin())
           return std::make_pair(0U, &RISCV::GPRF16NoX0RegClass);
+      } else if (VT == MVT::bf16 && Subtarget.hasStdExtZfbfmin()) {
+        return std::make_pair(0U, &RISCV::FPR16RegClass);
       } else if (VT == MVT::f32) {
         if (Subtarget.hasStdExtF())
           return std::make_pair(0U, &RISCV::FPR32RegClass);