[clang] [llvm] [AArch64][SVE] Improve fixed-length addressing modes. (PR #129732)

[Ricardo Jesus via cfe-commits]

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@@ -405,6 +405,17 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo {
     return MinSVEVectorSizeInBits;
   }
 
+  // Return the known bit length of SVE data registers. A value of 0 means the
+  // length is unkown beyond what's implied by the architecture.
+  unsigned getSVEVectorSizeInBits() const {
+    assert(isSVEorStreamingSVEAvailable() &&
+           "Tried to get SVE vector length without SVE support!");
+    if (MaxSVEVectorSizeInBits &&
+        MinSVEVectorSizeInBits == MaxSVEVectorSizeInBits)
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rj-jesus wrote:

Thanks very much for the suggestion; that looks much better.
Should we let through the case `!MinSVEVectorSizeInBits && MaxSVEVectorSizeInBits == 128` too?

https://github.com/llvm/llvm-project/pull/129732