[clang] [llvm] [RISCV] Assembler support for XRivosVizip (PR #127694)

[Philip Reames via cfe-commits]

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@@ -0,0 +1,27 @@
+//===-- RISCVInstrInfoXRivos.td ----------------------------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the vendor extensions defined by Rivos Inc.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// XRivosVizip
+//===----------------------------------------------------------------------===//
+
+
+let Predicates = [HasVendorXRivosVizip], DecoderNamespace = "XRivos",
+  Constraints = "@earlyclobber $vd", RVVConstraint = Vrgather,
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preames wrote:

Two comments on this line.

1) I'm copying the existing structure for the earlycobber, but as far as I can tell, this has no effect.  This has to be placed on the pseudo to have any impact on codegen, and has no relevance for the MC layer.  

2) The use of Vrgather for the RVVConstraint type translates as an overlap check for vs2, vs1, and mask register (if any).  I had to fix an ambiguity in the specification document to make it clear overlap with the mask register was disallowed.  The use of instruction names as keys appears to imply that there's more meaning beyond the implied registers to check, but the code doesn't actually seem to reflect that.  I could add a VZip constraint type, but I'd rather move forward with this and then restructure this enum in terms of the registers being checked.  

https://github.com/llvm/llvm-project/pull/127694