[clang] [llvm] [RISCV] Assembler support for XRivosVizip (PR #127694)
Philip Reames via cfe-commits
cfe-commits at lists.llvm.org
Fri Feb 21 12:29:37 PST 2025
https://github.com/preames updated https://github.com/llvm/llvm-project/pull/127694
>From 81e50773d34f788df750bf6d4a4cd8c727a6b148 Mon Sep 17 00:00:00 2001
From: Philip Reames <preames at rivosinc.com>
Date: Wed, 22 Jan 2025 12:54:24 -0800
Subject: [PATCH 1/3] [RISCV] Assembler support for XRivosVizip
This implements assembler support for the XRivosVizip custom/vendor
extension from Rivos Inc. which is defined in:
https://github.com/rivosinc/rivos-custom-extensions
(See src/xrivosvizip.adoc)
Codegen support will follow in a separate change.
---
.../Driver/print-supported-extensions-riscv.c | 1 +
.../RISCV/Disassembler/RISCVDisassembler.cpp | 2 ++
llvm/lib/Target/RISCV/RISCVFeatures.td | 9 ++++++
llvm/lib/Target/RISCV/RISCVInstrInfo.td | 1 +
llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td | 27 +++++++++++++++++
llvm/test/MC/RISCV/xrivosvizip-valid.s | 30 +++++++++++++++++++
.../TargetParser/RISCVISAInfoTest.cpp | 1 +
7 files changed, 71 insertions(+)
create mode 100644 llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td
create mode 100644 llvm/test/MC/RISCV/xrivosvizip-valid.s
diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c
index 3443ff0b69de9..57b6a46677591 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -202,6 +202,7 @@
// CHECK-NEXT: xqcilo 0.2 'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)
// CHECK-NEXT: xqcilsm 0.2 'Xqcilsm' (Qualcomm uC Load Store Multiple Extension)
// CHECK-NEXT: xqcisls 0.2 'Xqcisls' (Qualcomm uC Scaled Load Store Extension)
+// CHECK-NEXT: xrivosvizip 0.1 'XRivosVizip' (Rivos Vector Register Zips)
// CHECK-EMPTY:
// CHECK-NEXT: Supported Profiles
// CHECK-NEXT: rva20s64
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index 01648ec0cbe9e..aef470b331cf1 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -721,6 +721,8 @@ DecodeStatus RISCVDisassembler::getInstruction32(MCInst &MI, uint64_t &Size,
"Qualcomm uC Conditional Move custom opcode table");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXqciint, DecoderTableXqciint32,
"Qualcomm uC Interrupts custom opcode table");
+ TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXRivosVizip, DecoderTableXRivos32,
+ "Rivos custom opcode table");
TRY_TO_DECODE(true, DecoderTable32, "RISCV32 table");
return MCDisassembler::Fail;
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 51aa8d7d307e4..8380d4474d6da 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1333,6 +1333,15 @@ def HasVendorXqcilo
AssemblerPredicate<(all_of FeatureVendorXqcilo),
"'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)">;
+// Rivos Extension(s)
+
+def FeatureVendorXRivosVizip
+ : RISCVExperimentalExtension<0, 1, "Rivos Vector Register Zips">;
+def HasVendorXRivosVizip
+ : Predicate<"Subtarget->hasVendorXRivosVizip()">,
+ AssemblerPredicate<(all_of FeatureVendorXRivosVizip),
+ "'XRivosVizip' (Rivos Vector Register Zips)">;
+
//===----------------------------------------------------------------------===//
// LLVM specific features and extensions
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index fde7dc89dd693..a962e64581797 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -2148,6 +2148,7 @@ include "RISCVInstrInfoXCV.td"
include "RISCVInstrInfoXwch.td"
include "RISCVInstrInfoXqci.td"
include "RISCVInstrInfoXMips.td"
+include "RISCVInstrInfoXRivos.td"
//===----------------------------------------------------------------------===//
// Global ISel
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td
new file mode 100644
index 0000000000000..055fdfe5c1f56
--- /dev/null
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td
@@ -0,0 +1,27 @@
+//===-- RISCVInstrInfoXRivos.td --------------------------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the vendor extensions defined by Rivos Inc.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// XRivosVizip
+//===----------------------------------------------------------------------===//
+
+
+let Predicates = [HasVendorXRivosVizip], hasSideEffects = 0,
+ mayLoad = 0, mayStore = 0, isCodeGenOnly = 0, DecoderNamespace = "XRivos",
+ Inst<6-0> = OPC_CUSTOM_2.Value in {
+defm RV_VZIPEVEN_V : VALU_IV_V<"rv.vzipeven", 0b001100>;
+defm RV_VZIPODD_V : VALU_IV_V<"rv.vzipodd", 0b011100>;
+defm RV_VZIP2A_V : VALU_IV_V<"rv.vzip2a", 0b000100>;
+defm RV_VZIP2B_V : VALU_IV_V<"rv.vzip2b", 0b010100>;
+defm RV_VUNZIP2A_V : VALU_IV_V<"rv.vunzip2a", 0b001000>;
+defm RV_VUNZIP2B_V : VALU_IV_V<"rv.vunzip2b", 0b011000>;
+}
diff --git a/llvm/test/MC/RISCV/xrivosvizip-valid.s b/llvm/test/MC/RISCV/xrivosvizip-valid.s
new file mode 100644
index 0000000000000..ae339fbfca57d
--- /dev/null
+++ b/llvm/test/MC/RISCV/xrivosvizip-valid.s
@@ -0,0 +1,30 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xrivosvizip -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-xrivosvizip < %s \
+# RUN: | llvm-objdump --mattr=+experimental-xrivosvizip -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-xrivosvizip -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-xrivosvizip < %s \
+# RUN: | llvm-objdump --mattr=+experimental-xrivosvizip -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: rv.vzipeven.vv v1, v2, v3
+# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x32]
+rv.vzipeven.vv v1, v2, v3
+# CHECK-ASM-AND-OBJ: rv.vzipodd.vv v1, v2, v3
+# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x72]
+rv.vzipodd.vv v1, v2, v3
+# CHECK-ASM-AND-OBJ: rv.vzip2a.vv v1, v2, v3
+# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x12]
+rv.vzip2a.vv v1, v2, v3
+# CHECK-ASM-AND-OBJ: rv.vzip2b.vv v1, v2, v3
+# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x52]
+rv.vzip2b.vv v1, v2, v3
+# CHECK-ASM-AND-OBJ: rv.vunzip2a.vv v1, v2, v3
+# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x22]
+rv.vunzip2a.vv v1, v2, v3
+# CHECK-ASM-AND-OBJ: rv.vunzip2b.vv v1, v2, v3
+# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x62]
+rv.vunzip2b.vv v1, v2, v3
+
diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
index 7ebfcf915a7c5..44b04dd0afe0f 100644
--- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
@@ -1128,6 +1128,7 @@ Experimental extensions
xqcilo 0.2
xqcilsm 0.2
xqcisls 0.2
+ xrivosvizip 0.1
Supported Profiles
rva20s64
>From bdd60bbac1518247c66dad439714aede7465d7d5 Mon Sep 17 00:00:00 2001
From: Philip Reames <preames at rivosinc.com>
Date: Thu, 20 Feb 2025 12:12:35 -0800
Subject: [PATCH 2/3] Address review comment
---
llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td
index 055fdfe5c1f56..f33dc0680e659 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td
@@ -1,4 +1,4 @@
-//===-- RISCVInstrInfoXRivos.td --------------------------*- tablegen -*-===//
+//===-- RISCVInstrInfoXRivos.td ----------------------------*- tablegen -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
@@ -15,8 +15,7 @@
//===----------------------------------------------------------------------===//
-let Predicates = [HasVendorXRivosVizip], hasSideEffects = 0,
- mayLoad = 0, mayStore = 0, isCodeGenOnly = 0, DecoderNamespace = "XRivos",
+let Predicates = [HasVendorXRivosVizip], DecoderNamespace = "XRivos",
Inst<6-0> = OPC_CUSTOM_2.Value in {
defm RV_VZIPEVEN_V : VALU_IV_V<"rv.vzipeven", 0b001100>;
defm RV_VZIPODD_V : VALU_IV_V<"rv.vzipodd", 0b011100>;
>From f7ebf19e50f0fad8871f683b3869b796670abfc0 Mon Sep 17 00:00:00 2001
From: Philip Reames <preames at rivosinc.com>
Date: Fri, 21 Feb 2025 11:33:30 -0800
Subject: [PATCH 3/3] Add missing overlap check, tests for same, and tests for
masked forms
---
llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td | 1 +
llvm/test/MC/RISCV/xrivosvizip-invalid.s | 10 +++++++
llvm/test/MC/RISCV/xrivosvizip-valid.s | 29 +++++++++++++++++++
3 files changed, 40 insertions(+)
create mode 100644 llvm/test/MC/RISCV/xrivosvizip-invalid.s
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td
index f33dc0680e659..873fa150755ba 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td
@@ -16,6 +16,7 @@
let Predicates = [HasVendorXRivosVizip], DecoderNamespace = "XRivos",
+ Constraints = "@earlyclobber $vd", RVVConstraint = Vrgather,
Inst<6-0> = OPC_CUSTOM_2.Value in {
defm RV_VZIPEVEN_V : VALU_IV_V<"rv.vzipeven", 0b001100>;
defm RV_VZIPODD_V : VALU_IV_V<"rv.vzipodd", 0b011100>;
diff --git a/llvm/test/MC/RISCV/xrivosvizip-invalid.s b/llvm/test/MC/RISCV/xrivosvizip-invalid.s
new file mode 100644
index 0000000000000..5a36c7757849c
--- /dev/null
+++ b/llvm/test/MC/RISCV/xrivosvizip-invalid.s
@@ -0,0 +1,10 @@
+# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-xrivosvizip < %s 2>&1 | \
+# RUN: FileCheck %s
+
+# Disallowed source/dest overlap cases
+# CHECK: error: the destination vector register group cannot overlap the source vector register group
+rv.vzipeven.vv v2, v2, v3
+# CHECK: error: the destination vector register group cannot overlap the source vector register group
+rv.vzipeven.vv v3, v2, v3
+# CHECK: error: the destination vector register group cannot overlap the mask register
+rv.vzipeven.vv v0, v2, v3, v0.t
diff --git a/llvm/test/MC/RISCV/xrivosvizip-valid.s b/llvm/test/MC/RISCV/xrivosvizip-valid.s
index ae339fbfca57d..1447e0a950a2c 100644
--- a/llvm/test/MC/RISCV/xrivosvizip-valid.s
+++ b/llvm/test/MC/RISCV/xrivosvizip-valid.s
@@ -12,19 +12,48 @@
# CHECK-ASM-AND-OBJ: rv.vzipeven.vv v1, v2, v3
# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x32]
rv.vzipeven.vv v1, v2, v3
+# CHECK-ASM-AND-OBJ: rv.vzipeven.vv v1, v2, v3, v0.t
+# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x30]
+rv.vzipeven.vv v1, v2, v3, v0.t
# CHECK-ASM-AND-OBJ: rv.vzipodd.vv v1, v2, v3
# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x72]
rv.vzipodd.vv v1, v2, v3
+# CHECK-ASM-AND-OBJ: rv.vzipodd.vv v1, v2, v3, v0.t
+# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x70]
+rv.vzipodd.vv v1, v2, v3, v0.t
+
# CHECK-ASM-AND-OBJ: rv.vzip2a.vv v1, v2, v3
# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x12]
rv.vzip2a.vv v1, v2, v3
+# CHECK-ASM-AND-OBJ: rv.vzip2a.vv v1, v2, v3, v0.t
+# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x10]
+rv.vzip2a.vv v1, v2, v3, v0.t
# CHECK-ASM-AND-OBJ: rv.vzip2b.vv v1, v2, v3
# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x52]
rv.vzip2b.vv v1, v2, v3
+# CHECK-ASM-AND-OBJ: rv.vzip2b.vv v1, v2, v3, v0.t
+# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x50]
+rv.vzip2b.vv v1, v2, v3, v0.t
+
# CHECK-ASM-AND-OBJ: rv.vunzip2a.vv v1, v2, v3
# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x22]
rv.vunzip2a.vv v1, v2, v3
+# CHECK-ASM-AND-OBJ: rv.vunzip2a.vv v1, v2, v3, v0.t
+# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x20]
+rv.vunzip2a.vv v1, v2, v3, v0.t
# CHECK-ASM-AND-OBJ: rv.vunzip2b.vv v1, v2, v3
# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x62]
rv.vunzip2b.vv v1, v2, v3
+# CHECK-ASM-AND-OBJ: rv.vunzip2b.vv v1, v2, v3, v0.t
+# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x60]
+rv.vunzip2b.vv v1, v2, v3, v0.t
+
+# Overlap between source registers *is* allowed
+
+# CHECK-ASM-AND-OBJ: rv.vzipeven.vv v1, v2, v2
+# CHECK-ASM: encoding: [0xdb,0x00,0x21,0x32]
+rv.vzipeven.vv v1, v2, v2
+# CHECK-ASM-AND-OBJ: rv.vzipeven.vv v1, v2, v0, v0.t
+# CHECK-ASM: encoding: [0xdb,0x00,0x20,0x30]
+rv.vzipeven.vv v1, v2, v0, v0.t
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