[clang] [llvm] [RISC-V] Add support for MIPS P8700 CPU (PR #117865)

[Craig Topper via cfe-commits]

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@@ -298,6 +298,15 @@ class RISCVInstrInfo : public RISCVGenInstrInfo {
 
   unsigned getTailDuplicateSize(CodeGenOptLevel OptLevel) const override;
 
+  /// Return true if pairing the given load or store may be paired with another.
+  static bool isPairableLdStInstOpc(unsigned Opc);
+
+  static bool isLdStSafeToPair(const MachineInstr &LdSt,
+                               const TargetRegisterInfo *TRI);
+
+  std::optional<std::pair<unsigned, unsigned>>
+  isRVVSpillForZvlsseg(unsigned Opcode) const;
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topperc wrote:

This looks like a bad merge. `isRVVSpillForZvlsseg` was deleted at some point in the past.

https://github.com/llvm/llvm-project/pull/117865