[clang] [llvm] [BPF] Add load-acquire and store-release instructions under -mcpu=v4 (PR #108636)

[Peilin Ye via cfe-commits]

peilin-ye wrote:

@yonghong-song Hi Yonghong, about my earlier question:

> However, I wonder how do I generate a sign-extending (sext), acquiring ATOMIC_LOAD in SelectionDAG?

After more digging, I found this in `llvm/include/llvm/CodeGen/TargetLowering.h`:

```cpp
  /// Returns how the platform's atomic operations are extended (ZERO_EXTEND,
  /// SIGN_EXTEND, or ANY_EXTEND).
  virtual ISD::NodeType getExtendForAtomicOps() const {
    return ISD::ZERO_EXTEND;
  }
```

If I override it in `class BPFTargetLowering`:

```diff
--- a/llvm/lib/Target/BPF/BPFISelLowering.h
+++ b/llvm/lib/Target/BPF/BPFISelLowering.h
@@ -46,6 +46,10 @@ public:
   // with the given GlobalAddress is legal.
   bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
 
+  ISD::NodeType getExtendForAtomicOps() const override {
+    return ISD::SIGN_EXTEND;
+  }
+
   BPFTargetLowering::ConstraintType
   getConstraintType(StringRef Constraint) const override;
```
I can then get a `sext` sub-word `AtomicLoad` SelectionDAG node:
```
Optimized legalized selection DAG: %bb.0 'bar:entry'
SelectionDAG has 8 nodes:
  t0: ch,glue = EntryToken
    t2: i64,ch = CopyFromReg t0, Register:i64 %0
  t8: i32,ch = AtomicLoad<(load acquire (s8) from %ir.ptr), sext from i8> t0, t2, demo.bpf.c:3:12
    t12: i64 = sign_extend t8, demo.bpf.c:3:12
  t6: ch,glue = CopyToReg t8:1, Register:i64 $r0, t12, demo.bpf.c:3:5
  t7: ch = BPFISD::RET_GLUE t6, Register:i64 $r0, t6:1, demo.bpf.c:3:5
```
...but now I can't have `zext` :-)
- - -
Looks like we can't have both `sext` and `zext` sub-word atomic load, unless we change `getExtendForAtomicOps()` and how it's used.

https://github.com/llvm/llvm-project/pull/108636