[clang] [llvm] [BPF] Add load-acquire and store-release instructions under -mcpu=v4 (PR #108636)

[Peilin Ye via cfe-commits]

peilin-ye wrote:

Hi @arsenm, I'm trying to match `atomic_load_zext_{8,16}` in BPF backend but it doesn't work:
```
fatal error: error in backend: Cannot select: t8: i32,ch = AtomicLoad<(load acquire (s8) from %ir.ptr), zext from i8> t0, t2, demo.bpf.c:3:12
  t2: i64,ch = CopyFromReg t0, Register:i64 %0
    t1: i64 = Register %0
...
```
After some digging, I think it is due to this TableGen (`llvm/utils/TableGen/CodeGenDAGPatterns.cpp`) change in commit 1ee6ce9bad4d ("GlobalISel: Allow forming atomic/volatile G_ZEXTLOAD"):
```diff
@@ -1105,6 +1109,10 @@ std::string TreePredicateFn::getPredCode() const {
     Code += "if (isReleaseOrStronger(cast<AtomicSDNode>(N)->getMergedOrdering())) "
             "return false;\n";
 
+  // TODO: Handle atomic sextload/zextload normally when ATOMIC_LOAD is removed.
+  if (isAtomic() && (isZeroExtLoad() || isSignExtLoad()))
+    Code += "return false;\n";
+
   if (isLoad() || isStore()) {
     StringRef SDNodeName = isLoad() ? "LoadSDNode" : "StoreSDNode";
```
So I'm having this in `BPFGenDAGISel.inc`:
```cpp
  case 34: {
    // Predicate_atomic_load_zext
    SDNode *N = Node;
    (void)N;
return false;
return true;

  }
```
It unconditionally returns `false`, so nothing would match `atomic_load_zext_{8,16}`.
- - -
Could you please shed some light on how to match `atomic_load_{s,z}ext_{8,16}`? 
 Should I learn about GlobalISel?  I'm aware that there's `atomic_load_az_{8,16}` (used by AArch64), but I need the `*_zext_*` and `*_sext_*` versions here.

https://github.com/llvm/llvm-project/pull/108636