[clang] [llvm] [BPF] Add load-acquire and store-release instructions under -mcpu=v4 (PR #108636)

[via cfe-commits]

eddyz87 wrote:

> @eddyz87, do my changes to BPFMISimplifyPatchable.cpp still look good to you? Now that load-acquires are STX insns, I wanted to make sure that BPFMISimplifyPatchable::checkADDrr() can still handle them correctly for CO-RE.

The `checkADDrr()` change looks ok.

> I'll add tests to llvm/test/CodeGen/BPF/CORE/ later, like what you did in commit https://github.com/llvm/llvm-project/commit/08d92dedd26c66bd203cc3b45f982d7aeb214995 ("[BPF] Fix in/out argument constraints for CORE_MEM instructions").

:+1: 

Also, commit message says:

> For example:
>
>     long foo(long *ptr) {
>         return __atomic_load_n(ptr, __ATOMIC_ACQUIRE);
>     }
>
> foo() can be compiled to:
>
>     db 10 00 00 10 00 00 00  r0 = load_acquire((u64 *)(r1 + 0x0))
>     95 00 00 00 00 00 00 00  exit
>
>     opcode (0xdb): BPF_ATOMIC | BPF_DW | BPF_STX
>     imm (0x00000010): BPF_LOAD_ACQ

Do we want to use `LDX` for this instruction? e.g.:

     opcode (0x3e): BPF_ATOMIC | BPF_DW | BPF_LDX
     imm (0x00000010): BPF_LOAD_ACQ

https://github.com/llvm/llvm-project/pull/108636