[clang] [llvm] [HLSL] Implement `WaveReadLaneAt` intrinsic for spirv backend (PR #111010)

[Nathan Gauër via cfe-commits]

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@@ -2653,6 +2653,21 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg,
         .addUse(GR.getSPIRVTypeID(ResType))
         .addUse(GR.getOrCreateConstInt(3, I, IntTy, TII));
   }
+  case Intrinsic::spv_wave_read_lane_at: {
+    assert(I.getNumOperands() == 4);
+    assert(I.getOperand(2).isReg());
+    assert(I.getOperand(3).isReg());
+
+    // Defines the execution scope currently 2 for group, see scope table
+    SPIRVType *IntTy = GR.getOrCreateSPIRVIntegerType(32, I, TII);
+    return BuildMI(BB, I, I.getDebugLoc(),
+                   TII.get(SPIRV::OpGroupNonUniformShuffle))
+        .addDef(ResVReg)
+        .addUse(GR.getSPIRVTypeID(ResType))
+        .addUse(I.getOperand(2).getReg())
+        .addUse(I.getOperand(3).getReg())
+        .addUse(GR.getOrCreateConstInt(2, I, IntTy, TII));
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Keenuts wrote:

Looks like the correct value is 3? (cross-lane interaction, not cross-wave).
For the `OpGroupNonUniformElect`, the value MUST be 3 (spec)
DXC also generates both with a scope of 3.

https://github.com/llvm/llvm-project/pull/111010