[clang] [llvm] [WIP] Add initial support for arc hyperbolic intrinsics (PR #106766)
Simon Pilgrim via cfe-commits
cfe-commits at lists.llvm.org
Fri Aug 30 10:56:50 PDT 2024
https://github.com/RKSimon updated https://github.com/llvm/llvm-project/pull/106766
>From 64f9eecea8e3b5cbdd53b0a6f494e1a7c9f7c781 Mon Sep 17 00:00:00 2001
From: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: Fri, 30 Aug 2024 18:34:27 +0100
Subject: [PATCH] [WIP] Add initial support for arc hyperbolic intrinsics
---
clang/include/clang/Basic/Builtins.td | 18 ++---
clang/lib/CodeGen/CGBuiltin.cpp | 33 +++++++++
llvm/include/llvm/CodeGen/BasicTTIImpl.h | 9 +++
llvm/include/llvm/CodeGen/ISDOpcodes.h | 6 ++
llvm/include/llvm/IR/Intrinsics.td | 15 ++++
llvm/include/llvm/IR/RuntimeLibcalls.def | 15 ++++
llvm/include/llvm/Support/TargetOpcodes.def | 9 +++
llvm/include/llvm/Target/GenericOpcodes.td | 21 ++++++
.../Target/GlobalISel/SelectionDAGCompat.td | 3 +
.../include/llvm/Target/TargetSelectionDAG.td | 3 +
llvm/lib/Analysis/VectorUtils.cpp | 3 +
llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 6 ++
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 20 ++++++
.../SelectionDAG/LegalizeFloatTypes.cpp | 70 ++++++++++++++++++-
llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h | 6 ++
.../SelectionDAG/LegalizeVectorOps.cpp | 3 +
.../SelectionDAG/LegalizeVectorTypes.cpp | 9 +++
.../lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 3 +
.../SelectionDAG/SelectionDAGBuilder.cpp | 24 +++++++
.../SelectionDAG/SelectionDAGDumper.cpp | 6 ++
llvm/lib/CodeGen/TargetLoweringBase.cpp | 17 +++--
.../Target/AArch64/AArch64ISelLowering.cpp | 25 +++----
llvm/lib/Target/X86/X86ISelLowering.cpp | 3 +
23 files changed, 297 insertions(+), 30 deletions(-)
diff --git a/clang/include/clang/Basic/Builtins.td b/clang/include/clang/Basic/Builtins.td
index 8668b25661dec8..50e3da1f8c3849 100644
--- a/clang/include/clang/Basic/Builtins.td
+++ b/clang/include/clang/Basic/Builtins.td
@@ -90,11 +90,11 @@ def AcosF16F128 : Builtin, F16F128MathTemplate {
let Prototype = "T(T)";
}
-def AcoshF128 : Builtin {
- let Spellings = ["__builtin_acoshf128"];
+def AcoshF16F128 : Builtin, F16F128MathTemplate {
+ let Spellings = ["__builtin_acosh"];
let Attributes = [FunctionWithBuiltinPrefix, NoThrow,
ConstIgnoringErrnoAndExceptions];
- let Prototype = "__float128(__float128)";
+ let Prototype = "T(T)";
}
def AsinF16F128 : Builtin, F16F128MathTemplate {
@@ -104,11 +104,11 @@ def AsinF16F128 : Builtin, F16F128MathTemplate {
let Prototype = "T(T)";
}
-def AsinhF128 : Builtin {
- let Spellings = ["__builtin_asinhf128"];
+def AsinhF16F128 : Builtin, F16F128MathTemplate {
+ let Spellings = ["__builtin_asinh"];
let Attributes = [FunctionWithBuiltinPrefix, NoThrow,
ConstIgnoringErrnoAndExceptions];
- let Prototype = "__float128(__float128)";
+ let Prototype = "T(T)";
}
def AtanF16F128 : Builtin, F16F128MathTemplate {
@@ -118,11 +118,11 @@ def AtanF16F128 : Builtin, F16F128MathTemplate {
let Prototype = "T(T)";
}
-def AtanhF128 : Builtin {
- let Spellings = ["__builtin_atanhf128"];
+def AtanhF16F128 : Builtin, F16F128MathTemplate {
+ let Spellings = ["__builtin_atanh"];
let Attributes = [FunctionWithBuiltinPrefix, NoThrow,
ConstIgnoringErrnoAndExceptions];
- let Prototype = "__float128(__float128)";
+ let Prototype = "T(T)";
}
def CbrtF128 : Builtin {
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index c9f21f9ded24f4..8247cfbfa284cc 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -2670,6 +2670,17 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl GD, unsigned BuiltinID,
return RValue::get(emitUnaryMaybeConstrainedFPBuiltin(
*this, E, Intrinsic::acos, Intrinsic::experimental_constrained_acos));
+ case Builtin::BIacosh:
+ case Builtin::BIacoshf:
+ case Builtin::BIacoshl:
+ case Builtin::BI__builtin_acosh:
+ case Builtin::BI__builtin_acoshf:
+ case Builtin::BI__builtin_acoshf16:
+ case Builtin::BI__builtin_acoshl:
+ case Builtin::BI__builtin_acoshf128:
+ return RValue::get(emitUnaryMaybeConstrainedFPBuiltin(
+ *this, E, Intrinsic::acosh, Intrinsic::experimental_constrained_acosh));
+
case Builtin::BIasin:
case Builtin::BIasinf:
case Builtin::BIasinl:
@@ -2681,6 +2692,17 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl GD, unsigned BuiltinID,
return RValue::get(emitUnaryMaybeConstrainedFPBuiltin(
*this, E, Intrinsic::asin, Intrinsic::experimental_constrained_asin));
+ case Builtin::BIasinh:
+ case Builtin::BIasinhf:
+ case Builtin::BIasinhl:
+ case Builtin::BI__builtin_asinh:
+ case Builtin::BI__builtin_asinhf:
+ case Builtin::BI__builtin_asinhf16:
+ case Builtin::BI__builtin_asinhl:
+ case Builtin::BI__builtin_asinhf128:
+ return RValue::get(emitUnaryMaybeConstrainedFPBuiltin(
+ *this, E, Intrinsic::asinh, Intrinsic::experimental_constrained_asinh));
+
case Builtin::BIatan:
case Builtin::BIatanf:
case Builtin::BIatanl:
@@ -2692,6 +2714,17 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl GD, unsigned BuiltinID,
return RValue::get(emitUnaryMaybeConstrainedFPBuiltin(
*this, E, Intrinsic::atan, Intrinsic::experimental_constrained_atan));
+ case Builtin::BIatanh:
+ case Builtin::BIatanhf:
+ case Builtin::BIatanhl:
+ case Builtin::BI__builtin_atanh:
+ case Builtin::BI__builtin_atanhf:
+ case Builtin::BI__builtin_atanhf16:
+ case Builtin::BI__builtin_atanhl:
+ case Builtin::BI__builtin_atanhf128:
+ return RValue::get(emitUnaryMaybeConstrainedFPBuiltin(
+ *this, E, Intrinsic::atanh, Intrinsic::experimental_constrained_atanh));
+
case Builtin::BIceil:
case Builtin::BIceilf:
case Builtin::BIceill:
diff --git a/llvm/include/llvm/CodeGen/BasicTTIImpl.h b/llvm/include/llvm/CodeGen/BasicTTIImpl.h
index 47323ca067a435..4f6a48bd99f03b 100644
--- a/llvm/include/llvm/CodeGen/BasicTTIImpl.h
+++ b/llvm/include/llvm/CodeGen/BasicTTIImpl.h
@@ -1996,6 +1996,15 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase<T> {
case Intrinsic::tanh:
ISD = ISD::FTANH;
break;
+ case Intrinsic::asinh:
+ ISD = ISD::FASINH;
+ break;
+ case Intrinsic::acosh:
+ ISD = ISD::FACOSH;
+ break;
+ case Intrinsic::atanh:
+ ISD = ISD::FATANH;
+ break;
case Intrinsic::exp:
ISD = ISD::FEXP;
break;
diff --git a/llvm/include/llvm/CodeGen/ISDOpcodes.h b/llvm/include/llvm/CodeGen/ISDOpcodes.h
index 187d624f0a73b9..dde7e5ef923e73 100644
--- a/llvm/include/llvm/CodeGen/ISDOpcodes.h
+++ b/llvm/include/llvm/CodeGen/ISDOpcodes.h
@@ -428,6 +428,9 @@ enum NodeType {
STRICT_FSINH,
STRICT_FCOSH,
STRICT_FTANH,
+ STRICT_FASINH,
+ STRICT_FACOSH,
+ STRICT_FATANH,
STRICT_FEXP,
STRICT_FEXP2,
STRICT_FLOG,
@@ -990,6 +993,9 @@ enum NodeType {
FSINH,
FCOSH,
FTANH,
+ FASINH,
+ FACOSH,
+ FATANH,
FPOW,
FPOWI,
/// FLDEXP - ldexp, inspired by libm (op0 * 2**op1).
diff --git a/llvm/include/llvm/IR/Intrinsics.td b/llvm/include/llvm/IR/Intrinsics.td
index 232d6be1073f49..0478964cca56ee 100644
--- a/llvm/include/llvm/IR/Intrinsics.td
+++ b/llvm/include/llvm/IR/Intrinsics.td
@@ -1024,6 +1024,9 @@ let IntrProperties = [IntrNoMem, IntrSpeculatable, IntrWillReturn] in {
def int_sin : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
def int_cos : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
def int_tan : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
+ def int_asinh : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
+ def int_acosh : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
+ def int_atanh : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
def int_sinh : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
def int_cosh : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
def int_tanh : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
@@ -1242,6 +1245,18 @@ let IntrProperties = [IntrInaccessibleMemOnly, IntrWillReturn, IntrStrictFP] in
[ LLVMMatchType<0>,
llvm_metadata_ty,
llvm_metadata_ty ]>;
+ def int_experimental_constrained_asinh : DefaultAttrsIntrinsic<[ llvm_anyfloat_ty ],
+ [ LLVMMatchType<0>,
+ llvm_metadata_ty,
+ llvm_metadata_ty ]>;
+ def int_experimental_constrained_acosh : DefaultAttrsIntrinsic<[ llvm_anyfloat_ty ],
+ [ LLVMMatchType<0>,
+ llvm_metadata_ty,
+ llvm_metadata_ty ]>;
+ def int_experimental_constrained_atanh : DefaultAttrsIntrinsic<[ llvm_anyfloat_ty ],
+ [ LLVMMatchType<0>,
+ llvm_metadata_ty,
+ llvm_metadata_ty ]>;
def int_experimental_constrained_sinh : DefaultAttrsIntrinsic<[ llvm_anyfloat_ty ],
[ LLVMMatchType<0>,
llvm_metadata_ty,
diff --git a/llvm/include/llvm/IR/RuntimeLibcalls.def b/llvm/include/llvm/IR/RuntimeLibcalls.def
index c3d5ef9f4e4f82..12831fca3e1463 100644
--- a/llvm/include/llvm/IR/RuntimeLibcalls.def
+++ b/llvm/include/llvm/IR/RuntimeLibcalls.def
@@ -232,6 +232,21 @@ HANDLE_LIBCALL(ATAN_F64, "atan")
HANDLE_LIBCALL(ATAN_F80, "atanl")
HANDLE_LIBCALL(ATAN_F128,"atanl")
HANDLE_LIBCALL(ATAN_PPCF128, "atanl")
+HANDLE_LIBCALL(ASINH_F32, "asinhf")
+HANDLE_LIBCALL(ASINH_F64, "asinh")
+HANDLE_LIBCALL(ASINH_F80, "asinhl")
+HANDLE_LIBCALL(ASINH_F128, "asinhl")
+HANDLE_LIBCALL(ASINH_PPCF128, "asinhl")
+HANDLE_LIBCALL(ACOSH_F32, "acoshf")
+HANDLE_LIBCALL(ACOSH_F64, "acosh")
+HANDLE_LIBCALL(ACOSH_F80, "acoshl")
+HANDLE_LIBCALL(ACOSH_F128, "acoshl")
+HANDLE_LIBCALL(ACOSH_PPCF128, "acoshl")
+HANDLE_LIBCALL(ATANH_F32, "atanhf")
+HANDLE_LIBCALL(ATANH_F64, "atanh")
+HANDLE_LIBCALL(ATANH_F80, "atanhl")
+HANDLE_LIBCALL(ATANH_F128, "atanhl")
+HANDLE_LIBCALL(ATANH_PPCF128, "atanhl")
HANDLE_LIBCALL(SINCOS_F32, nullptr)
HANDLE_LIBCALL(SINCOS_F64, nullptr)
HANDLE_LIBCALL(SINCOS_F80, nullptr)
diff --git a/llvm/include/llvm/Support/TargetOpcodes.def b/llvm/include/llvm/Support/TargetOpcodes.def
index 635c265a433631..c167c7fc72a8f0 100644
--- a/llvm/include/llvm/Support/TargetOpcodes.def
+++ b/llvm/include/llvm/Support/TargetOpcodes.def
@@ -808,6 +808,15 @@ HANDLE_TARGET_OPCODE(G_FASIN)
/// Floating point arctangent.
HANDLE_TARGET_OPCODE(G_FATAN)
+/// Floating point hyperbolic arccosine.
+HANDLE_TARGET_OPCODE(G_FACOSH)
+
+/// Floating point hyperbolic arcsine.
+HANDLE_TARGET_OPCODE(G_FASINH)
+
+/// Floating point hyperbolic arctangent.
+HANDLE_TARGET_OPCODE(G_FATANH)
+
/// Floating point hyperbolic cosine.
HANDLE_TARGET_OPCODE(G_FCOSH)
diff --git a/llvm/include/llvm/Target/GenericOpcodes.td b/llvm/include/llvm/Target/GenericOpcodes.td
index 36a0a087ba457c..0e84eb66442995 100644
--- a/llvm/include/llvm/Target/GenericOpcodes.td
+++ b/llvm/include/llvm/Target/GenericOpcodes.td
@@ -1057,6 +1057,27 @@ def G_FTANH : GenericInstruction {
let hasSideEffects = false;
}
+// Floating point hyperbolic arccosine of a value.
+def G_FACOSH : GenericInstruction {
+ let OutOperandList = (outs type0:$dst);
+ let InOperandList = (ins type0:$src1);
+ let hasSideEffects = false;
+}
+
+// Floating point hyperbolic arcsine of a value.
+def G_FASINH : GenericInstruction {
+ let OutOperandList = (outs type0:$dst);
+ let InOperandList = (ins type0:$src1);
+ let hasSideEffects = false;
+}
+
+// Floating point hyperbolic arctangent of a value.
+def G_FATANH : GenericInstruction {
+ let OutOperandList = (outs type0:$dst);
+ let InOperandList = (ins type0:$src1);
+ let hasSideEffects = false;
+}
+
// Floating point square root of a value.
// This returns NaN for negative nonzero values.
// NOTE: Unlike libm sqrt(), this never sets errno. In all other respects it's
diff --git a/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td b/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
index 72d155b483cf2b..9e103ec1ea2639 100644
--- a/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
+++ b/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
@@ -155,6 +155,9 @@ def : GINodeEquiv<G_FATAN, fatan>;
def : GINodeEquiv<G_FCOSH, fcosh>;
def : GINodeEquiv<G_FSINH, fsinh>;
def : GINodeEquiv<G_FTANH, ftanh>;
+def : GINodeEquiv<G_FACOSH, facosh>;
+def : GINodeEquiv<G_FASINH, fasinh>;
+def : GINodeEquiv<G_FATANH, fatanh>;
def : GINodeEquiv<G_FABS, fabs>;
def : GINodeEquiv<G_FSQRT, fsqrt>;
def : GINodeEquiv<G_FFLOOR, ffloor>;
diff --git a/llvm/include/llvm/Target/TargetSelectionDAG.td b/llvm/include/llvm/Target/TargetSelectionDAG.td
index dd79002dcbdb48..c846fae0c1bc96 100644
--- a/llvm/include/llvm/Target/TargetSelectionDAG.td
+++ b/llvm/include/llvm/Target/TargetSelectionDAG.td
@@ -537,6 +537,9 @@ def fatan : SDNode<"ISD::FATAN" , SDTFPUnaryOp>;
def fsinh : SDNode<"ISD::FSINH" , SDTFPUnaryOp>;
def fcosh : SDNode<"ISD::FCOSH" , SDTFPUnaryOp>;
def ftanh : SDNode<"ISD::FTANH" , SDTFPUnaryOp>;
+def fasinh : SDNode<"ISD::FASINH" , SDTFPUnaryOp>;
+def facosh : SDNode<"ISD::FACOSH" , SDTFPUnaryOp>;
+def fatanh : SDNode<"ISD::FATANH" , SDTFPUnaryOp>;
def fexp2 : SDNode<"ISD::FEXP2" , SDTFPUnaryOp>;
def fexp10 : SDNode<"ISD::FEXP10" , SDTFPUnaryOp>;
def fpow : SDNode<"ISD::FPOW" , SDTFPBinOp>;
diff --git a/llvm/lib/Analysis/VectorUtils.cpp b/llvm/lib/Analysis/VectorUtils.cpp
index 32ce34114b2f50..faa1b86ebbe9be 100644
--- a/llvm/lib/Analysis/VectorUtils.cpp
+++ b/llvm/lib/Analysis/VectorUtils.cpp
@@ -72,6 +72,9 @@ bool llvm::isTriviallyVectorizable(Intrinsic::ID ID) {
case Intrinsic::sin:
case Intrinsic::cos:
case Intrinsic::tan:
+ case Intrinsic::asinh:
+ case Intrinsic::acosh:
+ case Intrinsic::atanh:
case Intrinsic::sinh:
case Intrinsic::cosh:
case Intrinsic::tanh:
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index b290d7fb4ce4a1..bedb9d2d5e2787 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -1885,6 +1885,12 @@ unsigned IRTranslator::getSimpleIntrinsicOpcode(Intrinsic::ID ID) {
return TargetOpcode::G_FASIN;
case Intrinsic::atan:
return TargetOpcode::G_FATAN;
+ case Intrinsic::acosh:
+ return TargetOpcode::G_FACOSH;
+ case Intrinsic::asinh:
+ return TargetOpcode::G_FASINH;
+ case Intrinsic::atanh:
+ return TargetOpcode::G_FATANH;
case Intrinsic::bswap:
return TargetOpcode::G_BSWAP;
case Intrinsic::bitreverse:
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index f5fbc01cd95e96..86feb296bc2145 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -4616,6 +4616,20 @@ void SelectionDAGLegalize::ConvertNodeToLibcall(SDNode *Node) {
case ISD::STRICT_FTANH:
ExpandFPLibCall(Node, RTLIB::TANH_F32, RTLIB::TANH_F64, RTLIB::TANH_F80,
RTLIB::TANH_F128, RTLIB::TANH_PPCF128, Results);
+ case ISD::FASINH:
+ case ISD::STRICT_FASINH:
+ ExpandFPLibCall(Node, RTLIB::ASINH_F32, RTLIB::ASINH_F64, RTLIB::ASINH_F80,
+ RTLIB::ASINH_F128, RTLIB::ASINH_PPCF128, Results);
+ break;
+ case ISD::FACOSH:
+ case ISD::STRICT_FACOSH:
+ ExpandFPLibCall(Node, RTLIB::ACOSH_F32, RTLIB::ACOSH_F64, RTLIB::ACOSH_F80,
+ RTLIB::ACOSH_F128, RTLIB::ACOSH_PPCF128, Results);
+ break;
+ case ISD::FATANH:
+ case ISD::STRICT_FATANH:
+ ExpandFPLibCall(Node, RTLIB::ATANH_F32, RTLIB::ATANH_F64, RTLIB::ATANH_F80,
+ RTLIB::ATANH_F128, RTLIB::ATANH_PPCF128, Results);
break;
case ISD::FSINCOS:
// Expand into sincos libcall.
@@ -5599,6 +5613,9 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
case ISD::FSINH:
case ISD::FCOSH:
case ISD::FTANH:
+ case ISD::FASINH:
+ case ISD::FACOSH:
+ case ISD::FATANH:
case ISD::FLOG:
case ISD::FLOG2:
case ISD::FLOG10:
@@ -5630,6 +5647,9 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
case ISD::STRICT_FSINH:
case ISD::STRICT_FCOSH:
case ISD::STRICT_FTANH:
+ case ISD::STRICT_FASINH:
+ case ISD::STRICT_FACOSH:
+ case ISD::STRICT_FATANH:
case ISD::STRICT_FLOG:
case ISD::STRICT_FLOG2:
case ISD::STRICT_FLOG10:
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
index b5c80005a0ecc1..bd66070230d249 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
@@ -84,6 +84,12 @@ void DAGTypeLegalizer::SoftenFloatResult(SDNode *N, unsigned ResNo) {
case ISD::FASIN: R = SoftenFloatRes_FASIN(N); break;
case ISD::STRICT_FATAN:
case ISD::FATAN: R = SoftenFloatRes_FATAN(N); break;
+ case ISD::STRICT_FACOSH:
+ case ISD::FACOSH: R = SoftenFloatRes_FACOSH(N); break;
+ case ISD::STRICT_FASINH:
+ case ISD::FASINH: R = SoftenFloatRes_FASINH(N); break;
+ case ISD::STRICT_FATANH:
+ case ISD::FATANH: R = SoftenFloatRes_FATANH(N); break;
case ISD::FCBRT: R = SoftenFloatRes_FCBRT(N); break;
case ISD::STRICT_FCEIL:
case ISD::FCEIL: R = SoftenFloatRes_FCEIL(N); break;
@@ -354,18 +360,39 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FACOS(SDNode *N) {
RTLIB::ACOS_F80, RTLIB::ACOS_F128, RTLIB::ACOS_PPCF128));
}
+SDValue DAGTypeLegalizer::SoftenFloatRes_FACOSH(SDNode *N) {
+ return SoftenFloatRes_Unary(
+ N,
+ GetFPLibCall(N->getValueType(0), RTLIB::ACOSH_F32, RTLIB::ACOSH_F64,
+ RTLIB::ACOSH_F80, RTLIB::ACOSH_F128, RTLIB::ACOSH_PPCF128));
+}
+
SDValue DAGTypeLegalizer::SoftenFloatRes_FASIN(SDNode *N) {
return SoftenFloatRes_Unary(
N, GetFPLibCall(N->getValueType(0), RTLIB::ASIN_F32, RTLIB::ASIN_F64,
RTLIB::ASIN_F80, RTLIB::ASIN_F128, RTLIB::ASIN_PPCF128));
}
+SDValue DAGTypeLegalizer::SoftenFloatRes_FASINH(SDNode *N) {
+ return SoftenFloatRes_Unary(
+ N,
+ GetFPLibCall(N->getValueType(0), RTLIB::ASINH_F32, RTLIB::ASINH_F64,
+ RTLIB::ASINH_F80, RTLIB::ASINH_F128, RTLIB::ASINH_PPCF128));
+}
+
SDValue DAGTypeLegalizer::SoftenFloatRes_FATAN(SDNode *N) {
return SoftenFloatRes_Unary(
N, GetFPLibCall(N->getValueType(0), RTLIB::ATAN_F32, RTLIB::ATAN_F64,
RTLIB::ATAN_F80, RTLIB::ATAN_F128, RTLIB::ATAN_PPCF128));
}
+SDValue DAGTypeLegalizer::SoftenFloatRes_FATANH(SDNode *N) {
+ return SoftenFloatRes_Unary(
+ N,
+ GetFPLibCall(N->getValueType(0), RTLIB::ATANH_F32, RTLIB::ATANH_F64,
+ RTLIB::ATANH_F80, RTLIB::ATANH_F128, RTLIB::ATANH_PPCF128));
+}
+
SDValue DAGTypeLegalizer::SoftenFloatRes_FCBRT(SDNode *N) {
return SoftenFloatRes_Unary(N, GetFPLibCall(N->getValueType(0),
RTLIB::CBRT_F32,
@@ -1430,6 +1457,12 @@ void DAGTypeLegalizer::ExpandFloatResult(SDNode *N, unsigned ResNo) {
case ISD::FASIN: ExpandFloatRes_FASIN(N, Lo, Hi); break;
case ISD::STRICT_FATAN:
case ISD::FATAN: ExpandFloatRes_FATAN(N, Lo, Hi); break;
+ case ISD::STRICT_FACOSH:
+ case ISD::FACOSH: ExpandFloatRes_FACOSH(N, Lo, Hi); break;
+ case ISD::STRICT_FASINH:
+ case ISD::FASINH: ExpandFloatRes_FASINH(N, Lo, Hi); break;
+ case ISD::STRICT_FATANH:
+ case ISD::FATANH: ExpandFloatRes_FATANH(N, Lo, Hi); break;
case ISD::FCBRT: ExpandFloatRes_FCBRT(N, Lo, Hi); break;
case ISD::STRICT_FCEIL:
case ISD::FCEIL: ExpandFloatRes_FCEIL(N, Lo, Hi); break;
@@ -1478,7 +1511,7 @@ void DAGTypeLegalizer::ExpandFloatResult(SDNode *N, unsigned ResNo) {
case ISD::STRICT_FSIN:
case ISD::FSIN: ExpandFloatRes_FSIN(N, Lo, Hi); break;
case ISD::STRICT_FSINH:
- case ISD::FSINH: ExpandFloatRes_FSINH(N, Lo, Hi); break;
+ case ISD::FSINH: ExpandFloatRes_FSINH(N, Lo, Hi); break;
case ISD::STRICT_FSQRT:
case ISD::FSQRT: ExpandFloatRes_FSQRT(N, Lo, Hi); break;
case ISD::STRICT_FSUB:
@@ -1486,7 +1519,7 @@ void DAGTypeLegalizer::ExpandFloatResult(SDNode *N, unsigned ResNo) {
case ISD::STRICT_FTAN:
case ISD::FTAN: ExpandFloatRes_FTAN(N, Lo, Hi); break;
case ISD::STRICT_FTANH:
- case ISD::FTANH: ExpandFloatRes_FTANH(N, Lo, Hi); break;
+ case ISD::FTANH: ExpandFloatRes_FTANH(N, Lo, Hi); break;
case ISD::STRICT_FTRUNC:
case ISD::FTRUNC: ExpandFloatRes_FTRUNC(N, Lo, Hi); break;
case ISD::LOAD: ExpandFloatRes_LOAD(N, Lo, Hi); break;
@@ -1613,6 +1646,15 @@ void DAGTypeLegalizer::ExpandFloatRes_FACOS(SDNode *N, SDValue &Lo,
Lo, Hi);
}
+void DAGTypeLegalizer::ExpandFloatRes_FACOSH(SDNode *N, SDValue &Lo,
+ SDValue &Hi) {
+ ExpandFloatRes_Unary(N,
+ GetFPLibCall(N->getValueType(0), RTLIB::ACOSH_F32,
+ RTLIB::ACOSH_F64, RTLIB::ACOSH_F80,
+ RTLIB::ACOSH_F128, RTLIB::ACOSH_PPCF128),
+ Lo, Hi);
+}
+
void DAGTypeLegalizer::ExpandFloatRes_FASIN(SDNode *N, SDValue &Lo,
SDValue &Hi) {
ExpandFloatRes_Unary(N,
@@ -1622,6 +1664,15 @@ void DAGTypeLegalizer::ExpandFloatRes_FASIN(SDNode *N, SDValue &Lo,
Lo, Hi);
}
+void DAGTypeLegalizer::ExpandFloatRes_FASINH(SDNode *N, SDValue &Lo,
+ SDValue &Hi) {
+ ExpandFloatRes_Unary(N,
+ GetFPLibCall(N->getValueType(0), RTLIB::ASINH_F32,
+ RTLIB::ASINH_F64, RTLIB::ASINH_F80,
+ RTLIB::ASINH_F128, RTLIB::ASINH_PPCF128),
+ Lo, Hi);
+}
+
void DAGTypeLegalizer::ExpandFloatRes_FATAN(SDNode *N, SDValue &Lo,
SDValue &Hi) {
ExpandFloatRes_Unary(N,
@@ -1631,6 +1682,15 @@ void DAGTypeLegalizer::ExpandFloatRes_FATAN(SDNode *N, SDValue &Lo,
Lo, Hi);
}
+void DAGTypeLegalizer::ExpandFloatRes_FATANH(SDNode *N, SDValue &Lo,
+ SDValue &Hi) {
+ ExpandFloatRes_Unary(N,
+ GetFPLibCall(N->getValueType(0), RTLIB::ATANH_F32,
+ RTLIB::ATANH_F64, RTLIB::ATANH_F80,
+ RTLIB::ATANH_F128, RTLIB::ATANH_PPCF128),
+ Lo, Hi);
+}
+
void DAGTypeLegalizer::ExpandFloatRes_FCBRT(SDNode *N, SDValue &Lo,
SDValue &Hi) {
ExpandFloatRes_Unary(N, GetFPLibCall(N->getValueType(0), RTLIB::CBRT_F32,
@@ -2642,6 +2702,9 @@ void DAGTypeLegalizer::PromoteFloatResult(SDNode *N, unsigned ResNo) {
case ISD::FACOS:
case ISD::FASIN:
case ISD::FATAN:
+ case ISD::FACOSH:
+ case ISD::FASINH:
+ case ISD::FATANH:
case ISD::FCBRT:
case ISD::FCEIL:
case ISD::FCOS:
@@ -3085,6 +3148,9 @@ void DAGTypeLegalizer::SoftPromoteHalfResult(SDNode *N, unsigned ResNo) {
case ISD::FACOS:
case ISD::FASIN:
case ISD::FATAN:
+ case ISD::FACOSH:
+ case ISD::FASINH:
+ case ISD::FATANH:
case ISD::FCBRT:
case ISD::FCEIL:
case ISD::FCOS:
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
index f15e3d7fd1eb63..7c9919ca8b519b 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
@@ -567,6 +567,9 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
SDValue SoftenFloatRes_FACOS(SDNode *N);
SDValue SoftenFloatRes_FASIN(SDNode *N);
SDValue SoftenFloatRes_FATAN(SDNode *N);
+ SDValue SoftenFloatRes_FACOSH(SDNode *N);
+ SDValue SoftenFloatRes_FASINH(SDNode *N);
+ SDValue SoftenFloatRes_FATANH(SDNode *N);
SDValue SoftenFloatRes_FMINNUM(SDNode *N);
SDValue SoftenFloatRes_FMAXNUM(SDNode *N);
SDValue SoftenFloatRes_FMINIMUMNUM(SDNode *N);
@@ -661,6 +664,9 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
void ExpandFloatRes_FACOS (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandFloatRes_FASIN (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandFloatRes_FATAN (SDNode *N, SDValue &Lo, SDValue &Hi);
+ void ExpandFloatRes_FACOSH (SDNode *N, SDValue &Lo, SDValue &Hi);
+ void ExpandFloatRes_FASINH (SDNode *N, SDValue &Lo, SDValue &Hi);
+ void ExpandFloatRes_FATANH (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandFloatRes_FMINNUM (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandFloatRes_FMAXNUM (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandFloatRes_FMINIMUMNUM(SDNode *N, SDValue &Lo, SDValue &Hi);
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
index 87221c14433ab5..ff92e6d03d2d70 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
@@ -411,6 +411,9 @@ SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
case ISD::FSINH:
case ISD::FCOSH:
case ISD::FTANH:
+ case ISD::FASINH:
+ case ISD::FACOSH:
+ case ISD::FATANH:
case ISD::FLDEXP:
case ISD::FPOWI:
case ISD::FPOW:
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index ae994d492d57e6..a1124edb8ff79f 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -88,6 +88,9 @@ void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
case ISD::FACOS:
case ISD::FASIN:
case ISD::FATAN:
+ case ISD::FACOSH:
+ case ISD::FASINH:
+ case ISD::FATANH:
case ISD::FCEIL:
case ISD::FCOS:
case ISD::FCOSH:
@@ -1195,6 +1198,9 @@ void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
case ISD::FACOS:
case ISD::FASIN:
case ISD::FATAN:
+ case ISD::FACOSH:
+ case ISD::FASINH:
+ case ISD::FATANH:
case ISD::FCEIL:
case ISD::VP_FCEIL:
case ISD::FCOS:
@@ -4659,6 +4665,9 @@ void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
case ISD::FACOS:
case ISD::FASIN:
case ISD::FATAN:
+ case ISD::FACOSH:
+ case ISD::FASINH:
+ case ISD::FATANH:
case ISD::FCEIL:
case ISD::FCOS:
case ISD::FCOSH:
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 7f57b6db40ef49..169f30cfdab9bb 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -5433,6 +5433,9 @@ bool SelectionDAG::isKnownNeverNaN(SDValue Op, bool SNaN, unsigned Depth) const
case ISD::FSINH:
case ISD::FCOSH:
case ISD::FTANH:
+ case ISD::FASINH:
+ case ISD::FACOSH:
+ case ISD::FATANH:
case ISD::FMA:
case ISD::FMAD: {
if (SNaN)
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 4b326ba76f97f2..42f23e8f39b9a0 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -6803,6 +6803,9 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I,
case Intrinsic::sinh:
case Intrinsic::cosh:
case Intrinsic::tanh:
+ case Intrinsic::asinh:
+ case Intrinsic::acosh:
+ case Intrinsic::atanh:
case Intrinsic::exp10:
case Intrinsic::floor:
case Intrinsic::ceil:
@@ -6827,6 +6830,9 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I,
case Intrinsic::sinh: Opcode = ISD::FSINH; break;
case Intrinsic::cosh: Opcode = ISD::FCOSH; break;
case Intrinsic::tanh: Opcode = ISD::FTANH; break;
+ case Intrinsic::asinh: Opcode = ISD::FASINH; break;
+ case Intrinsic::acosh: Opcode = ISD::FACOSH; break;
+ case Intrinsic::atanh: Opcode = ISD::FATANH; break;
case Intrinsic::exp10: Opcode = ISD::FEXP10; break;
case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
@@ -9373,6 +9379,24 @@ void SelectionDAGBuilder::visitCall(const CallInst &I) {
if (visitUnaryFloatCall(I, ISD::FTANH))
return;
break;
+ case LibFunc_asinh:
+ case LibFunc_asinhf:
+ case LibFunc_asinhl:
+ if (visitUnaryFloatCall(I, ISD::FASINH))
+ return;
+ break;
+ case LibFunc_acosh:
+ case LibFunc_acoshf:
+ case LibFunc_acoshl:
+ if (visitUnaryFloatCall(I, ISD::FACOSH))
+ return;
+ break;
+ case LibFunc_atanh:
+ case LibFunc_atanhf:
+ case LibFunc_atanhl:
+ if (visitUnaryFloatCall(I, ISD::FATANH))
+ return;
+ break;
case LibFunc_sqrt:
case LibFunc_sqrtf:
case LibFunc_sqrtl:
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
index a253d1a0e20170..4efdeb495a2f4c 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
@@ -228,6 +228,12 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const {
case ISD::STRICT_FCOSH: return "strict_fcosh";
case ISD::FTANH: return "ftanh";
case ISD::STRICT_FTANH: return "strict_ftanh";
+ case ISD::FASINH: return "fasinh";
+ case ISD::STRICT_FASINH: return "strict_fasinh";
+ case ISD::FACOSH: return "facosh";
+ case ISD::STRICT_FACOSH: return "strict_facosh";
+ case ISD::FATANH: return "fatanh";
+ case ISD::STRICT_FATANH: return "strict_fatanh";
case ISD::FTRUNC: return "ftrunc";
case ISD::STRICT_FTRUNC: return "strict_ftrunc";
case ISD::FFLOOR: return "ffloor";
diff --git a/llvm/lib/CodeGen/TargetLoweringBase.cpp b/llvm/lib/CodeGen/TargetLoweringBase.cpp
index 35d6304cf9b400..e424d395c1a4d1 100644
--- a/llvm/lib/CodeGen/TargetLoweringBase.cpp
+++ b/llvm/lib/CodeGen/TargetLoweringBase.cpp
@@ -776,7 +776,8 @@ void TargetLoweringBase::initActions() {
ISD::SIGN_EXTEND_VECTOR_INREG, ISD::ZERO_EXTEND_VECTOR_INREG,
ISD::SPLAT_VECTOR, ISD::LRINT, ISD::LLRINT, ISD::LROUND,
ISD::LLROUND, ISD::FTAN, ISD::FACOS, ISD::FASIN, ISD::FATAN,
- ISD::FCOSH, ISD::FSINH, ISD::FTANH},
+ ISD::FCOSH, ISD::FSINH, ISD::FTANH, ISD::FACOSH, ISD::FASINH,
+ ISD::FATANH},
VT, Expand);
// Constrained floating-point operations default to expand.
@@ -831,11 +832,12 @@ void TargetLoweringBase::initActions() {
Expand);
// These library functions default to expand.
- setOperationAction({ISD::FCBRT, ISD::FLOG, ISD::FLOG2, ISD::FLOG10,
- ISD::FEXP, ISD::FEXP2, ISD::FEXP10, ISD::FFLOOR,
- ISD::FNEARBYINT, ISD::FCEIL, ISD::FRINT, ISD::FTRUNC,
- ISD::FROUNDEVEN, ISD::FTAN, ISD::FACOS, ISD::FASIN,
- ISD::FATAN, ISD::FCOSH, ISD::FSINH, ISD::FTANH},
+ setOperationAction({ISD::FCBRT, ISD::FLOG, ISD::FLOG2, ISD::FLOG10,
+ ISD::FEXP, ISD::FEXP2, ISD::FEXP10, ISD::FFLOOR,
+ ISD::FNEARBYINT, ISD::FCEIL, ISD::FRINT, ISD::FTRUNC,
+ ISD::FROUNDEVEN, ISD::FTAN, ISD::FACOS, ISD::FASIN,
+ ISD::FATAN, ISD::FCOSH, ISD::FSINH, ISD::FTANH,
+ ISD::FACOSH, ISD::FASINH, ISD::FATANH},
{MVT::f32, MVT::f64, MVT::f128}, Expand);
// FIXME: Query RuntimeLibCalls to make the decision.
@@ -843,7 +845,8 @@ void TargetLoweringBase::initActions() {
{MVT::f32, MVT::f64, MVT::f128}, LibCall);
setOperationAction({ISD::FTAN, ISD::FACOS, ISD::FASIN, ISD::FATAN, ISD::FCOSH,
- ISD::FSINH, ISD::FTANH},
+ ISD::FSINH, ISD::FTANH, ISD::FACOSH, ISD::FASINH,
+ ISD::FATANH},
MVT::f16, Promote);
// Default ISD::TRAP to expand (which turns it into abort).
setOperationAction(ISD::TRAP, MVT::Other, Expand);
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 28ad0abf25703b..50fd1432d07b5b 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -732,18 +732,19 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
setOperationAction(ISD::FCOPYSIGN, MVT::bf16, Promote);
}
- for (auto Op : {ISD::FREM, ISD::FPOW, ISD::FPOWI,
- ISD::FCOS, ISD::FSIN, ISD::FSINCOS,
- ISD::FACOS, ISD::FASIN, ISD::FATAN,
- ISD::FCOSH, ISD::FSINH, ISD::FTANH,
- ISD::FTAN, ISD::FEXP, ISD::FEXP2,
- ISD::FEXP10, ISD::FLOG, ISD::FLOG2,
- ISD::FLOG10, ISD::STRICT_FREM, ISD::STRICT_FPOW,
- ISD::STRICT_FPOWI, ISD::STRICT_FCOS, ISD::STRICT_FSIN,
- ISD::STRICT_FACOS, ISD::STRICT_FASIN, ISD::STRICT_FATAN,
- ISD::STRICT_FCOSH, ISD::STRICT_FSINH, ISD::STRICT_FTANH,
- ISD::STRICT_FEXP, ISD::STRICT_FEXP2, ISD::STRICT_FLOG,
- ISD::STRICT_FLOG2, ISD::STRICT_FLOG10, ISD::STRICT_FTAN}) {
+ for (auto Op : {ISD::FREM, ISD::FPOW, ISD::FPOWI,
+ ISD::FCOS, ISD::FSIN, ISD::FSINCOS,
+ ISD::FACOS, ISD::FASIN, ISD::FATAN,
+ ISD::FCOSH, ISD::FSINH, ISD::FTANH,
+ ISD::FTAN, ISD::FEXP, ISD::FEXP2,
+ ISD::FEXP10, ISD::FLOG, ISD::FLOG2,
+ ISD::FLOG10, ISD::STRICT_FREM, ISD::STRICT_FPOW,
+ ISD::STRICT_FPOWI, ISD::STRICT_FCOS, ISD::STRICT_FSIN,
+ ISD::STRICT_FACOS, ISD::STRICT_FASIN, ISD::STRICT_FATAN,
+ ISD::STRICT_FCOSH, ISD::STRICT_FSINH, ISD::STRICT_FTANH,
+ ISD::STRICT_FACOSH, ISD::STRICT_FASINH, ISD::STRICT_FATANH,
+ ISD::STRICT_FEXP, ISD::STRICT_FEXP2, ISD::STRICT_FLOG,
+ ISD::STRICT_FLOG2, ISD::STRICT_FLOG10, ISD::STRICT_FTAN}) {
setOperationAction(Op, MVT::f16, Promote);
setOperationAction(Op, MVT::v4f16, Expand);
setOperationAction(Op, MVT::v8f16, Expand);
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index f011249d295040..f799a35968363b 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -2478,8 +2478,11 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
// clang-format off
for (ISD::NodeType Op :
{ISD::FACOS, ISD::STRICT_FACOS,
+ ISD::FACOSH, ISD::STRICT_FACOSH,
ISD::FASIN, ISD::STRICT_FASIN,
+ ISD::FASINH, ISD::STRICT_FASINH,
ISD::FATAN, ISD::STRICT_FATAN,
+ ISD::FATANH, ISD::STRICT_FATANH,
ISD::FCEIL, ISD::STRICT_FCEIL,
ISD::FCOS, ISD::STRICT_FCOS,
ISD::FCOSH, ISD::STRICT_FCOSH,
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