[clang] [llvm] [WIP] Add initial support for arc hyperbolic intrinsics (PR #106766)

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<!--LLVM CODE FORMAT COMMENT: {clang-format}-->


:warning: C/C++ code formatter, clang-format found issues in your code. :warning:

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``````````bash
git-clang-format --diff 5500e21942f7047344b6fee62d3e08c0ba2f9182 6567d4b48c492a054fcbbfb0f0826d32bbb29404 --extensions cpp,h -- clang/lib/CodeGen/CGBuiltin.cpp llvm/include/llvm/CodeGen/BasicTTIImpl.h llvm/include/llvm/CodeGen/ISDOpcodes.h llvm/lib/Analysis/VectorUtils.cpp llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp llvm/lib/CodeGen/TargetLoweringBase.cpp llvm/lib/Target/AArch64/AArch64ISelLowering.cpp llvm/lib/Target/X86/X86ISelLowering.cpp
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View the diff from clang-format here.
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``````````diff
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 0a683b13dd..70a0bacfcb 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -2675,11 +2675,12 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl GD, unsigned BuiltinID,
     case Builtin::BIacoshl:
     case Builtin::BI__builtin_acosh:
     case Builtin::BI__builtin_acoshf:
-    //case Builtin::BI__builtin_acoshf16:
+    // case Builtin::BI__builtin_acoshf16:
     case Builtin::BI__builtin_acoshl:
     case Builtin::BI__builtin_acoshf128:
       return RValue::get(emitUnaryMaybeConstrainedFPBuiltin(
-          *this, E, Intrinsic::acosh, Intrinsic::experimental_constrained_acosh));
+          *this, E, Intrinsic::acosh,
+          Intrinsic::experimental_constrained_acosh));
 
     case Builtin::BIasin:
     case Builtin::BIasinf:
@@ -2697,11 +2698,12 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl GD, unsigned BuiltinID,
     case Builtin::BIasinhl:
     case Builtin::BI__builtin_asinh:
     case Builtin::BI__builtin_asinhf:
-    //case Builtin::BI__builtin_asinhf16:
+    // case Builtin::BI__builtin_asinhf16:
     case Builtin::BI__builtin_asinhl:
     case Builtin::BI__builtin_asinhf128:
       return RValue::get(emitUnaryMaybeConstrainedFPBuiltin(
-          *this, E, Intrinsic::asinh, Intrinsic::experimental_constrained_asinh));
+          *this, E, Intrinsic::asinh,
+          Intrinsic::experimental_constrained_asinh));
 
     case Builtin::BIatan:
     case Builtin::BIatanf:
@@ -2719,11 +2721,12 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl GD, unsigned BuiltinID,
     case Builtin::BIatanhl:
     case Builtin::BI__builtin_atanh:
     case Builtin::BI__builtin_atanhf:
-    //case Builtin::BI__builtin_atanhf16:
+    // case Builtin::BI__builtin_atanhf16:
     case Builtin::BI__builtin_atanhl:
     case Builtin::BI__builtin_atanhf128:
       return RValue::get(emitUnaryMaybeConstrainedFPBuiltin(
-          *this, E, Intrinsic::atanh, Intrinsic::experimental_constrained_atanh));
+          *this, E, Intrinsic::atanh,
+          Intrinsic::experimental_constrained_atanh));
 
     case Builtin::BIceil:
     case Builtin::BIceilf:
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
index bd66070230..4bf40d542e 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
@@ -1647,7 +1647,7 @@ void DAGTypeLegalizer::ExpandFloatRes_FACOS(SDNode *N, SDValue &Lo,
 }
 
 void DAGTypeLegalizer::ExpandFloatRes_FACOSH(SDNode *N, SDValue &Lo,
-                                            SDValue &Hi) {
+                                             SDValue &Hi) {
   ExpandFloatRes_Unary(N,
                        GetFPLibCall(N->getValueType(0), RTLIB::ACOSH_F32,
                                     RTLIB::ACOSH_F64, RTLIB::ACOSH_F80,
diff --git a/llvm/lib/CodeGen/TargetLoweringBase.cpp b/llvm/lib/CodeGen/TargetLoweringBase.cpp
index e424d395c1..59de43c03e 100644
--- a/llvm/lib/CodeGen/TargetLoweringBase.cpp
+++ b/llvm/lib/CodeGen/TargetLoweringBase.cpp
@@ -771,14 +771,27 @@ void TargetLoweringBase::initActions() {
 
     // These operations default to expand for vector types.
     if (VT.isVector())
-      setOperationAction(
-          {ISD::FCOPYSIGN, ISD::SIGN_EXTEND_INREG, ISD::ANY_EXTEND_VECTOR_INREG,
-           ISD::SIGN_EXTEND_VECTOR_INREG, ISD::ZERO_EXTEND_VECTOR_INREG,
-           ISD::SPLAT_VECTOR, ISD::LRINT, ISD::LLRINT, ISD::LROUND,
-           ISD::LLROUND, ISD::FTAN, ISD::FACOS, ISD::FASIN, ISD::FATAN,
-           ISD::FCOSH, ISD::FSINH, ISD::FTANH, ISD::FACOSH, ISD::FASINH,
-           ISD::FATANH},
-          VT, Expand);
+      setOperationAction({ISD::FCOPYSIGN,
+                          ISD::SIGN_EXTEND_INREG,
+                          ISD::ANY_EXTEND_VECTOR_INREG,
+                          ISD::SIGN_EXTEND_VECTOR_INREG,
+                          ISD::ZERO_EXTEND_VECTOR_INREG,
+                          ISD::SPLAT_VECTOR,
+                          ISD::LRINT,
+                          ISD::LLRINT,
+                          ISD::LROUND,
+                          ISD::LLROUND,
+                          ISD::FTAN,
+                          ISD::FACOS,
+                          ISD::FASIN,
+                          ISD::FATAN,
+                          ISD::FCOSH,
+                          ISD::FSINH,
+                          ISD::FTANH,
+                          ISD::FACOSH,
+                          ISD::FASINH,
+                          ISD::FATANH},
+                         VT, Expand);
 
       // Constrained floating-point operations default to expand.
 #define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN)               \

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https://github.com/llvm/llvm-project/pull/106766