[clang] [llvm] [RISCV] Add Hazard3 Core as taped out for RP2350 (PR #102452)

[Sam Elliott via cfe-commits]

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@@ -108,6 +108,7 @@ Changes to the RISC-V Backend
   fill value) rather than NOPs.
 * Added Syntacore SCR4 and SCR5 CPUs: ``-mcpu=syntacore-scr4/5-rv32/64``
 * ``-mcpu=sifive-p470`` was added.
+* Added Hazard3 CPU: ``-mcpu=hazard3`` (32-bit only).
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lenary wrote:

Definitely does. Well spotted, thanks.

https://github.com/llvm/llvm-project/pull/102452