[clang] [llvm] [RISCV] Add vector and vector crypto to SiFiveP400 scheduler model (PR #102155)

[Michael Maitland via cfe-commits]

michaelmaitland wrote:

@camel-cdr

> Are the vrgather.vv numbers correct?

According to llvm-exegisis, our micro-architecture spec, and llvm-mca reports, we believe these numbers are correct.

> Usually LMUL>1 vrgather is implemented by applying a LMUL=1 vrgather LMUL^2 times. Since the LMUL=1 vrgather.vv takes a single cycle, I would've expected a 4 cycle LMUL=2 vrgather.vv instead of 12.

We don't think using the approach you present here agrees with what we see in llvm-exegisis. We think the approach we take is a good representation.

> Oh, and did you use upstream llvm-exegesis? I didn't managed to get it to work last time I tried.

This is a question for @mshockwave.

https://github.com/llvm/llvm-project/pull/102155