[clang] [llvm] [RISCV] Add vector and vector crypto to SiFiveP400 scheduler model (PR #102155)

[Michael Maitland via cfe-commits]

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@@ -45,6 +154,13 @@ defvar SiFiveP400FloatArith  = SiFiveP400FEXQ0;
 defvar SiFiveP400F2I      = SiFiveP400FEXQ0;
 def SiFiveP400FloatDiv    : ProcResource<1>;
 
+// Vector pipeline
+def SiFiveP400VEXQ0        : ProcResource<1>;
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michaelmaitland wrote:

There is an issue queue in front of the vector ALU (purple). Vector loads go through the load/store dispatch buffer (green). Vector divisions are non blocking to other vector ALU operations.

We think it is okay to model VLD/VST/VDiv/VFloatDiv as standalone resources.

https://github.com/llvm/llvm-project/pull/102155