[clang] [llvm] [RISCV][MC] Support experimental extensions Zvbc32e and Zvkgs (PR #103709)

[Craig Topper via cfe-commits]

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@@ -762,6 +773,14 @@ def HasStdExtZvkg : Predicate<"Subtarget->hasStdExtZvkg()">,
                     AssemblerPredicate<(all_of FeatureStdExtZvkg),
                         "'Zvkg' (Vector GCM instructions for Cryptography)">;
 
+def FeatureStdExtZvkgs
+    : RISCVExperimentalExtension<"zvkgs", 0, 7,
+                                 "'Zvkgs' (Vector-Scalar GCM instructions for Cryptography)",
+                                 [FeatureStdExtZvkg]>;
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topperc wrote:

The spec is largely written for the hardware design. How a toolchain -march string should work is probably not being thought about. So what the spec is saying is that if your hardware implements Zvkgs it must also implement Zvkg.

https://github.com/llvm/llvm-project/pull/103709