[clang] [llvm] [RISCV] Add processor definition for SpacemiT-X60 (PR #94564)

[Philip Reames via cfe-commits]

================
@@ -381,3 +381,20 @@ def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu",
                                             TuneZExtHFusion,
                                             TuneZExtWFusion,
                                             TuneShiftedZExtWFusion]>;
+
+def SPACEMIT_X60 : RISCVProcessorModel<"spacemit-x60",
+                                       NoSchedModel,
+                                       !listconcat(RVA22S64Features,
+                                       [FeatureStdExtV,
+                                        FeatureStdExtSvnapot,
+                                        FeatureStdExtZbc,
+                                        FeatureStdExtZbkc,
+                                        FeatureStdExtZfh,
+                                        FeatureStdExtZicond,
----------------
preames wrote:

> The supported extensions are listed in 2.1.2 of this [document](https://developer.spacemit.com/#/documentation?token=BWbGwbx7liGW21kq9lucSA6Vnpb), including zicond. I

@sunshaoce  We should adjust the patch description to reference this document.  If you have anything you think is supported which is not on the documented list, please highlight it so that @zqb-all can clarify docs.

@zqb-all Thanks!

https://github.com/llvm/llvm-project/pull/94564