[clang] [llvm] [RISCV] Add processor definition for SpacemiT-X60 (PR #94564)

[Mark Zhuang via cfe-commits]

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@@ -381,3 +381,20 @@ def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu",
                                             TuneZExtHFusion,
                                             TuneZExtWFusion,
                                             TuneShiftedZExtWFusion]>;
+
+def SPACEMIT_X60 : RISCVProcessorModel<"spacemit-x60",
+                                       NoSchedModel,
+                                       !listconcat(RVA22S64Features,
+                                       [FeatureStdExtV,
+                                        FeatureStdExtSvnapot,
+                                        FeatureStdExtZbc,
+                                        FeatureStdExtZbkc,
+                                        FeatureStdExtZfh,
+                                        FeatureStdExtZicond,
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zqb-all wrote:

Thanks for your review, it really is more reliable to add support based on document. The supported extensions are listed in 2.1.2 of this [document](https://developer.spacemit.com/#/documentation?token=BWbGwbx7liGW21kq9lucSA6Vnpb), including zicond. If you have any questions about other extensions, please let me know so that I can confirm and update the document. Finally, we can review this patch based on the document. 

https://github.com/llvm/llvm-project/pull/94564