[clang] [llvm] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1 instructions. (PR #83896)

[Craig Topper via cfe-commits]

topperc wrote:

> > > Hi @topperc, can you add instruction alias for cflush and cdiscard instructions when the rs1 is X0 to `sf.cflush.d.l1` and `sf.cflush.d.l1` respectively, as this register is optional according to spec?
> > 
> > 
> > x0 has special meaning, but the spec never says it is "optional".
> 
> Possibly I am mistaken here but this is what I inferred from the below text in the mannual - rs1 is optional, so if a user does not specify it then by default it will be X0. Apologies if I am missing something here but just wanted to be clear.
> 
> From the mannual - `Opcode 0xFC000073, with **optional** rs1 field in bits [19:15]`

I think i had a bad copy of the file. There are several iterations. And one of the copies I had doesn't have the "optional" text on cflush.d.l1.

https://github.com/llvm/llvm-project/pull/83896