[clang] [llvm] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1 instructions. (PR #83896)

[Garvit Gupta via cfe-commits]

quic-garvgupt wrote:

> > Also, I think we might need to update the extensions in the `RISCVProcessors.td` file under SIFIVE_S76 microcontroller?
> 
> This is a M-mode only extension, and we haven't historically been adding M or S mode extensions to the -mcpu lists. Except for `xiangshan-nanhu` having `Svinval`. But maybe there's a microcontroller vs application core distinction we should be making?

I see, I was not aware of this. Thanks for your reply

https://github.com/llvm/llvm-project/pull/83896