[llvm] [clang] [RISCV] Add sifive-p450 CPU. (PR #75760)
Craig Topper via cfe-commits
cfe-commits at lists.llvm.org
Tue Dec 19 22:29:48 PST 2023
https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/75760
>From 22fd20164e9d061a451555c5158f0a8ecb73f77e Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Sun, 17 Dec 2023 18:18:43 -0800
Subject: [PATCH 1/3] [RISCV] Add sifive-p450 CPU.
This is an out of order core with no vector unit. More information:
https://www.sifive.com/cores/performance-p450-470
Scheduler model and other tuning will come in separate patches.
---
clang/test/Misc/target-invalid-cpu-note.c | 4 ++--
llvm/lib/Target/RISCV/RISCVProcessors.td | 19 +++++++++++++++++++
2 files changed, 21 insertions(+), 2 deletions(-)
diff --git a/clang/test/Misc/target-invalid-cpu-note.c b/clang/test/Misc/target-invalid-cpu-note.c
index e840a9208f5a45..48e9f05d9b03de 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -85,7 +85,7 @@
// RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV64
// RISCV64: error: unknown target CPU 'not-a-cpu'
-// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu{{$}}
+// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu{{$}}
// RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
// TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
@@ -93,4 +93,4 @@
// RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
// TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
-// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu, generic, rocket, sifive-7-series{{$}}
+// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu, generic, rocket, sifive-7-series{{$}}
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 58989fd716fa0e..16c79519fcacc1 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -216,6 +216,25 @@ def SIFIVE_X280 : RISCVProcessorModel<"sifive-x280", SiFive7Model,
[TuneSiFive7,
TuneDLenFactor2]>;
+def SIFIVE_P450 : RISCVProcessorModel<"sifive-p450", NoSchedModel,
+ [Feature64Bit,
+ FeatureStdExtZifencei,
+ FeatureStdExtM,
+ FeatureStdExtA,
+ FeatureStdExtF,
+ FeatureStdExtD,
+ FeatureStdExtC,
+ FeatureStdExtZicbop,
+ FeatureStdExtZicbom,
+ FeatureStdExtZicboz,
+ FeatureStdExtZihintntl,
+ FeatureStdExtZihintpause,
+ FeatureStdExtZihpm,
+ FeatureStdExtZba,
+ FeatureStdExtZbb,
+ FeatureStdExtZbs,
+ FeatureStdExtZfhmin]>;
+
def SYNTACORE_SCR1_BASE : RISCVProcessorModel<"syntacore-scr1-base",
SyntacoreSCR1Model,
[Feature32Bit,
>From 11323f0d835931624dc5aa42fdef6b1199107716 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Tue, 19 Dec 2023 16:04:35 -0800
Subject: [PATCH 2/3] fixup! Add test to riscv-cpus.
---
clang/test/Driver/riscv-cpus.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index d7fa7c9854a48f..424e57cc7a3b3d 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -222,6 +222,11 @@
// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zvl512b" "-target-feature" "+zvl64b"
// MCPU-SIFIVE-X280-SAME: "-target-abi" "lp64d"
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -menable-experimental-extensions -mcpu=sifive-p450 | FileCheck -check-prefix=MCPU-SIFIVE-P450 %s
+// MCPU-SIFIVE-P450: "-nostdsysteminc" "-target-cpu" "sifive-p450"
+// MCPU-SIFIVE-P450-SAME: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d" "-target-feature" "+c" "-target-feature" "+zicbom" "-target-feature" "+zicbop" "-target-feature" "+zicboz" "-target-feature" "+zicsr" "-target-feature" "+zifencei" "-target-feature" "+zihintntl" "-target-feature" "+zihintpause" "-target-feature" "+zihpm" "-target-feature" "+zfhmin" "-target-feature" "+zba" "-target-feature" "+zbb" "-target-feature" "+zbs" "-target-feature" "-
+// MCPU-SIFIVE-P450-SAME: "-target-abi" "lp64d"
+//
// Check failed cases
// RUN: not %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv321 | FileCheck -check-prefix=FAIL-MCPU-NAME %s
>From 5f7f381d1ddd19aa8a165787290fa91f4a93a322 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Tue, 19 Dec 2023 22:29:31 -0800
Subject: [PATCH 3/3] Address review feedback
---
clang/test/Driver/riscv-cpus.c | 20 ++++++++++++++++++--
1 file changed, 18 insertions(+), 2 deletions(-)
diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index 424e57cc7a3b3d..f32d511ec3d18b 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -222,9 +222,25 @@
// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zvl512b" "-target-feature" "+zvl64b"
// MCPU-SIFIVE-X280-SAME: "-target-abi" "lp64d"
-// RUN: %clang -target riscv64 -### -c %s 2>&1 -menable-experimental-extensions -mcpu=sifive-p450 | FileCheck -check-prefix=MCPU-SIFIVE-P450 %s
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-p450 | FileCheck -check-prefix=MCPU-SIFIVE-P450 %s
// MCPU-SIFIVE-P450: "-nostdsysteminc" "-target-cpu" "sifive-p450"
-// MCPU-SIFIVE-P450-SAME: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d" "-target-feature" "+c" "-target-feature" "+zicbom" "-target-feature" "+zicbop" "-target-feature" "+zicboz" "-target-feature" "+zicsr" "-target-feature" "+zifencei" "-target-feature" "+zihintntl" "-target-feature" "+zihintpause" "-target-feature" "+zihpm" "-target-feature" "+zfhmin" "-target-feature" "+zba" "-target-feature" "+zbb" "-target-feature" "+zbs" "-target-feature" "-
+// MCPU-SIFIVE-P450-SAME: "-target-feature" "+m"
+// MCPU-SIFIVE-P450-SAME: "-target-feature" "+a"
+// MCPU-SIFIVE-P450-SAME: "-target-feature" "+f"
+// MCPU-SIFIVE-P450-SAME: "-target-feature" "+d"
+// MCPU-SIFIVE-P450-SAME: "-target-feature" "+c"
+// MCPU-SIFIVE-P450-SAME: "-target-feature" "+zicbom"
+// MCPU-SIFIVE-P450-SAME: "-target-feature" "+zicbop"
+// MCPU-SIFIVE-P450-SAME: "-target-feature" "+zicboz"
+// MCPU-SIFIVE-P450-SAME: "-target-feature" "+zicsr"
+// MCPU-SIFIVE-P450-SAME: "-target-feature" "+zifencei"
+// MCPU-SIFIVE-P450-SAME: "-target-feature" "+zihintntl"
+// MCPU-SIFIVE-P450-SAME: "-target-feature" "+zihintpause"
+// MCPU-SIFIVE-P450-SAME: "-target-feature" "+zihpm"
+// MCPU-SIFIVE-P450-SAME: "-target-feature" "+zfhmin"
+// MCPU-SIFIVE-P450-SAME: "-target-feature" "+zba"
+// MCPU-SIFIVE-P450-SAME: "-target-feature" "+zbb"
+// MCPU-SIFIVE-P450-SAME: "-target-feature" "+zbs"
// MCPU-SIFIVE-P450-SAME: "-target-abi" "lp64d"
//
// Check failed cases
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