[llvm] [clang] [RISCV] Add sifive-p450 CPU. (PR #75760)

[Wang Pengcheng via cfe-commits]

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@@ -222,6 +222,11 @@
 // MCPU-SIFIVE-X280-SAME: "-target-feature" "+zvl512b" "-target-feature" "+zvl64b"
 // MCPU-SIFIVE-X280-SAME: "-target-abi" "lp64d"
 
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -menable-experimental-extensions -mcpu=sifive-p450 | FileCheck -check-prefix=MCPU-SIFIVE-P450 %s
+// MCPU-SIFIVE-P450: "-nostdsysteminc" "-target-cpu" "sifive-p450"
+// MCPU-SIFIVE-P450-SAME: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d" "-target-feature" "+c" "-target-feature" "+zicbom" "-target-feature" "+zicbop" "-target-feature" "+zicboz" "-target-feature" "+zicsr" "-target-feature" "+zifencei" "-target-feature" "+zihintntl" "-target-feature" "+zihintpause" "-target-feature" "+zihpm" "-target-feature" "+zfhmin" "-target-feature" "+zba" "-target-feature" "+zbb" "-target-feature" "+zbs" "-target-feature" "-
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wangpc-pp wrote:

I prefer to the form of `veyron-v1` test that there is exactly one line for one feature. We can just test features specified in `RISCVProcessorModel` definitions in `RISCVProcessors.td`. As for implied features, we can ignore them as there are test coverage in other tests and this is not the purpose of `riscv-cpus.c` I think.

https://github.com/llvm/llvm-project/pull/75760