[clang] [RISCV] Add sched model for XiangShan-NanHu (PR #70232)

[Yingwei Zheng via cfe-commits]

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@@ -302,7 +302,7 @@ def FSW : FPStore_r<0b010, "fsw", FPR32, WriteFST32>;
 } // Predicates = [HasStdExtF]
 
 foreach Ext = FExts in {
-  let SchedRW = [WriteFMA32, ReadFMA32, ReadFMA32, ReadFMA32] in {
+  let SchedRW = [WriteFMA32, ReadFMA32, ReadFMA32, ReadFMA32Addend] in {
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dtcxzyw wrote:

Posted as #70241.

https://github.com/llvm/llvm-project/pull/70232