[clang] [clang-format] Properly indent lines inside Verilog case structure (PR #65861)

[Owen Pan via cfe-commits]

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@@ -1599,6 +1600,15 @@ unsigned ContinuationIndenter::moveStateToNextToken(LineState &State,
 
   State.Column += Current.ColumnWidth;
   State.NextToken = State.NextToken->Next;
+  // Verilog case labels are are on the same unwrapped lines as the statements
+  // that follow.  TokenAnnotator identifies them and sets MustBreakBefore.
+  // Indentation is taken care of here.  A case label can only have 1 statement
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owenca wrote:

Typo: `are are`. Also, use single space after `.`.

https://github.com/llvm/llvm-project/pull/65861