[PATCH] D157474: [RISCV] Add missing Xsfvcp extension check in clang sema

[Brandon Wu via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
4vtomat marked an inline comment as done.
Closed by commit rGa23d65ac89ce: [RISCV] Add missing Xsfvcp extension check in clang sema (authored by 4vtomat).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D157474/new/

https://reviews.llvm.org/D157474

Files:
  clang/lib/Sema/SemaRISCVVectorLookup.cpp
  clang/test/Sema/rvv-required-features-invalid.c
  clang/test/Sema/rvv-required-features.c


Index: clang/test/Sema/rvv-required-features.c
===================================================================
--- /dev/null
+++ clang/test/Sema/rvv-required-features.c
@@ -0,0 +1,19 @@
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +xsfvcp %s -fsyntax-only -verify
+
+// expected-no-diagnostics
+
+#include <riscv_vector.h>
+#include <sifive_vector.h>
+
+vint8m1_t test_vloxei64_v_i8m1(const int8_t *base, vuint64m8_t bindex, size_t vl) {
+  return __riscv_vloxei64(base, bindex, vl);
+}
+
+void test_vsoxei64_v_i8m1(int8_t *base, vuint64m8_t bindex, vint8m1_t value, size_t vl) {
+  __riscv_vsoxei64(base, bindex, value, vl);
+}
+
+void test_sf_vc_x_se_u64m1(uint64_t rs1, size_t vl) {
+  __riscv_sf_vc_x_se_u64m1(1, 1, 1, rs1, vl);
+}
Index: clang/test/Sema/rvv-required-features-invalid.c
===================================================================
--- /dev/null
+++ clang/test/Sema/rvv-required-features-invalid.c
@@ -0,0 +1,17 @@
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv32 -target-feature +v %s -fsyntax-only -verify
+
+#include <riscv_vector.h>
+#include <sifive_vector.h>
+
+vint8m1_t test_vloxei64_v_i8m1(const int8_t *base, vuint64m8_t bindex, size_t vl) {
+  return __riscv_vloxei64(base, bindex, vl); // expected-error {{call to undeclared function '__riscv_vloxei64'}} expected-error {{returning 'int' from a function with incompatible result type 'vint8m1_t'}}
+}
+
+void test_vsoxei64_v_i8m1(int8_t *base, vuint64m8_t bindex, vint8m1_t value, size_t vl) {
+  __riscv_vsoxei64(base, bindex, value, vl); // expected-error {{call to undeclared function '__riscv_vsoxei64'}}
+}
+
+void test_xsfvcp_sf_vc_x_se_u64m1(uint64_t rs1, size_t vl) {
+  __riscv_sf_vc_x_se_u64m1(1, 1, 1, rs1, vl); // expected-error {{call to undeclared function '__riscv_sf_vc_x_se_u64m1'}}
+}
Index: clang/lib/Sema/SemaRISCVVectorLookup.cpp
===================================================================
--- clang/lib/Sema/SemaRISCVVectorLookup.cpp
+++ clang/lib/Sema/SemaRISCVVectorLookup.cpp
@@ -202,10 +202,20 @@
 void RISCVIntrinsicManagerImpl::ConstructRVVIntrinsics(
     ArrayRef<RVVIntrinsicRecord> Recs, IntrinsicKind K) {
   const TargetInfo &TI = Context.getTargetInfo();
-  bool HasRV64 = TI.hasFeature("64bit");
+  static const std::pair<const char *, uint8_t> FeatureCheckList[] = {
+      {"64bit", RVV_REQ_RV64},
+      {"xsfvcp", RVV_REQ_Xsfvcp}};
+
   // Construction of RVVIntrinsicRecords need to sync with createRVVIntrinsics
   // in RISCVVEmitter.cpp.
   for (auto &Record : Recs) {
+    // Check requirements.
+    if (llvm::any_of(FeatureCheckList, [&](const auto &Item) {
+          return (Record.RequiredExtensions & Item.second) == Item.second &&
+                 !TI.hasFeature(Item.first);
+        }))
+      continue;
+
     // Create Intrinsics for each type and LMUL.
     BasicType BaseType = BasicType::Unknown;
     ArrayRef<PrototypeDescriptor> BasicProtoSeq =
@@ -251,11 +261,6 @@
       if ((BaseTypeI & Record.TypeRangeMask) != BaseTypeI)
         continue;
 
-      // Check requirement.
-      if (((Record.RequiredExtensions & RVV_REQ_RV64) == RVV_REQ_RV64) &&
-          !HasRV64)
-        continue;
-
       // Expanded with different LMUL.
       for (int Log2LMUL = -3; Log2LMUL <= 3; Log2LMUL++) {
         if (!(Record.Log2LMULMask & (1 << (Log2LMUL + 3))))


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