[PATCH] D156115: [Clang][SVE] Permit specific predicate-as-counter registers in inline assembly

Sander de Smalen via Phabricator via cfe-commits cfe-commits at lists.llvm.org
Mon Jul 24 06:18:27 PDT 2023


sdesmalen added inline comments.


================
Comment at: clang/test/CodeGen/aarch64-sve-inline-asm.c:3
+// RUN:   -emit-llvm -o - %s | FileCheck %s -check-prefix=CHECK
 
 void test_sve_asm(void) {
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Could you also add a RUN line that compiles this to asm, just to make sure that LLVM accepts the inline asm syntax? There don't need to be any checks for the output.
This then probably also requires a `REQUIRES: aarch64-registered-target`.


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Comment at: clang/test/CodeGen/aarch64-sve-inline-asm.c:18
+void test_sve2p1_asm(void) {
+  register __SVCount_t x2 asm("pn0");
+  asm("ptrue pn8.b" ::: "pn8");
----------------
x2 seems unused. Did you forget to assign it and to add some CHECK lines for it?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D156115/new/

https://reviews.llvm.org/D156115



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