[PATCH] D156115: [Clang][SVE] Permit specific predicate-as-counter registers in inline assembly

[Matt Devereau via Phabricator via cfe-commits]

MattDevereau added inline comments.


================
Comment at: clang/test/CodeGen/aarch64-sve-inline-asm.c:17
+
+void test_sve2p1_asm(void) {
+  register __SVCount_t x2 asm("pn0");
----------------
I think it would be better to keep this test similar to `test_sve_asm` in that it tests both ends of the range of predicate registers and also tests it can be used as an operand to other valid instructions. Right now it feels like the bare minimum.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D156115/new/

https://reviews.llvm.org/D156115