[PATCH] D134678: [Clang][AArch64][SME] Add intrinsics for ZA array load/store (LDR/STR)

[Sander de Smalen via Phabricator via cfe-commits]

sdesmalen added inline comments.


================
Comment at: clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_str.c:24
+// CHECK-NEXT:    [[TMP0:%.*]] = getelementptr i8, ptr [[PTR:%.*]], i64 [[MULVL]]
+// CHECK-NEXT:    tail call void @llvm.aarch64.sme.str(i32 [[SLICE_BASE:%.*]], ptr [[TMP0]])
+// CHECK-NEXT:    ret void
----------------
This is missing an `add` of `15` to `%slice_base`.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D134678/new/

https://reviews.llvm.org/D134678